mirror of
https://github.com/amazingfate/rtl8723ds.git
synced 2026-06-18 18:29:01 +01:00
rtl8723ds: Remove WINDOWS code
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
@@ -27,8 +27,6 @@
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#ifdef PLATFORM_LINUX
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#define rsprintf snprintf
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#elif defined(PLATFORM_WINDOWS)
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#define rsprintf sprintf_s
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#endif
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#define DCMD_Printf DBG_BT_INFO
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@@ -3850,9 +3850,6 @@ static void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist)
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static void halbtc8723d1ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
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IN u32 gen_count)
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{
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@@ -3884,9 +3881,6 @@ static void halbtc8723d1ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
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psd_scan->psd_loop_max_value[gen_count - 1] = loop_val_max;
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
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{
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/* reg 0x808[9:0]: FFT data x */
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@@ -3918,9 +3912,6 @@ static u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32
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return psd_report;
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
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IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
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IN u32 avgnum, IN u32 loopcnt)
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@@ -4250,9 +4241,6 @@ static boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static boolean halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist
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*btcoexist)
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{
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@@ -4634,9 +4622,6 @@ static boolean halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static boolean halbtc8723d1ant_psd_antenna_detection_check(IN struct btc_coexist
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*btcoexist)
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{
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@@ -6045,15 +6030,6 @@ void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist)
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board_info->antdetval = psd_scan->ant_det_psd_scan_peak_val/100;
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value = board_info->antdetval;
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#ifdef PLATFORM_WINDOWS
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{
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PWCHAR registryName;
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registryName = L"antdetval";
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PlatformWriteCommonDwordRegistry(registryName, &value);
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}
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#endif
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}
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}
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@@ -6086,9 +6062,6 @@ void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
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}
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist,
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IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
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{
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@@ -4431,9 +4431,6 @@ static void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist)
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static void halbtc8723d2ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
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IN u32 gen_count)
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{
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@@ -4466,10 +4463,6 @@ static void halbtc8723d2ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static u32 halbtc8723d2ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
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{
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/* reg 0x808[9:0]: FFT data x */
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@@ -4501,9 +4494,6 @@ static u32 halbtc8723d2ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32
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return psd_report;
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
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IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
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IN u32 avgnum, IN u32 loopcnt)
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@@ -4833,9 +4823,6 @@ static boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static boolean halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist
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*btcoexist)
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{
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@@ -5216,9 +5203,6 @@ static boolean halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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static boolean halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist
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*btcoexist)
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{
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@@ -6664,9 +6648,6 @@ void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
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}
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}
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#ifdef PLATFORM_WINDOWS
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#pragma optimize("", off)
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#endif
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void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist,
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IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
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{
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@@ -77,47 +77,4 @@
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#define RTL8188ES_HWIMG_SUPPORT 0
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#endif
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#else // PLATFORM_WINDOWS & MacOSX
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//For 92C
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#define RTL8192CE_HWIMG_SUPPORT 1
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#define RTL8192CE_TEST_HWIMG_SUPPORT 1
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#define RTL8192CU_HWIMG_SUPPORT 1
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#define RTL8192CU_TEST_HWIMG_SUPPORT 1
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// For 92D
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#define RTL8192DE_HWIMG_SUPPORT 1
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#define RTL8192DE_TEST_HWIMG_SUPPORT 1
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#define RTL8192DU_HWIMG_SUPPORT 1
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#define RTL8192DU_TEST_HWIMG_SUPPORT 1
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#if defined(UNDER_CE)
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// For 8723
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#define RTL8723E_HWIMG_SUPPORT 0
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#define RTL8723U_HWIMG_SUPPORT 0
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#define RTL8723S_HWIMG_SUPPORT 1
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// For 88E
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#else
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// For 8723
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#define RTL8723E_HWIMG_SUPPORT 1
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//#define RTL_8723E_TEST_HWIMG_SUPPORT 1
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#define RTL8723U_HWIMG_SUPPORT 1
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//#define RTL_8723U_TEST_HWIMG_SUPPORT 1
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#define RTL8723S_HWIMG_SUPPORT 1
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//#define RTL_8723S_TEST_HWIMG_SUPPORT 1
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//For 88E
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#define RTL8188EE_HWIMG_SUPPORT 1
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#define RTL8188EU_HWIMG_SUPPORT 1
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#define RTL8188ES_HWIMG_SUPPORT 1
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#endif
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#endif
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#endif //__INC_HW_IMG_H
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@@ -3567,391 +3567,6 @@ phy_DigitalPredistortion_8723D(
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IN BOOLEAN is2T
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)
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{
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#if (RT_PLATFORM == PLATFORM_WINDOWS)
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
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PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
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#endif
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
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#endif
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#endif
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u4Byte tmpReg, tmpReg2, index, i;
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u1Byte path, pathbound = PATH_NUM;
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u4Byte AFE_backup[IQK_ADDA_REG_NUM];
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u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
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rFPGA0_XCD_SwitchControl, rBlue_Tooth,
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rRx_Wait_CCA, rTx_CCK_RFON,
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rTx_CCK_BBON, rTx_OFDM_RFON,
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rTx_OFDM_BBON, rTx_To_Rx,
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rTx_To_Tx, rRx_CCK,
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rRx_OFDM, rRx_Wait_RIFS,
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rRx_TO_Rx, rStandby,
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rSleep, rPMPD_ANAEN };
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u4Byte BB_backup[DP_BB_REG_NUM];
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u4Byte BB_REG[DP_BB_REG_NUM] = {
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rOFDM0_TRxPathEnable, rFPGA0_RFMOD,
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rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW,
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rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
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rFPGA0_XB_RFInterfaceOE};
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u4Byte BB_settings[DP_BB_REG_NUM] = {
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0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
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0x0, 0x0, 0x0};
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u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
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u4Byte RF_REG[DP_RF_REG_NUM] = {
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RF_TXBIAS_A};
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u4Byte MAC_backup[IQK_MAC_REG_NUM];
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u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
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REG_TXPAUSE, REG_BCN_CTRL,
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REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
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u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
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{0x1e1e1e1e, 0x03901e1e},
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{0x18181818, 0x03901818},
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{0x0e0e0e0e, 0x03900e0e}
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};
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u4Byte AFE_on_off[PATH_NUM] = {
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0x04db25a4, 0x0b1b25a4};
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u1Byte RetryCount = 0;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion_8723D()\n"));
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion_8723D for %s\n", (is2T ? "2T2R" : "1T1R")));
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for (index = 0; index < DP_BB_REG_NUM; index++)
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BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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_PHY_SaveMACRegisters_8723D(pAdapter, BB_REG, MAC_backup);
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#else
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_PHY_SaveMACRegisters_8723D(pDM_Odm, BB_REG, MAC_backup);
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#endif
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for (path = 0; path < DP_PATH_NUM; path++) {
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for (index = 0; index < DP_RF_REG_NUM; index++)
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
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#else
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RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
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#endif
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}
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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_PHY_SaveADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
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#else
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_PHY_SaveADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
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#endif
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for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
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ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4);
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for (index = 0; index < DP_BB_REG_NUM; index++) {
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if (index < 4)
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ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]);
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else if (index == 4)
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ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
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else
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ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00);
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}
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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_PHY_MACSettingCalibration_8723D(pAdapter, MAC_REG, MAC_backup);
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#else
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_PHY_MACSettingCalibration_8723D(pDM_Odm, MAC_REG, MAC_backup);
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#endif
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ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
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ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
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ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
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ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000);
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ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
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for (i = 0; i < 3; i++) {
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for (index = 0; index < 3; index++)
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ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]);
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ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]);
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for (index = 0; index < 4; index++)
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ODM_SetBBReg(pDM_Odm, 0xe10+index*4, bMaskDWord, Tx_AGC[i][0]);
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098);
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ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
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ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788);
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ODM_delay_ms(1);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788);
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ODM_delay_ms(50);
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}
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for (index = 0; index < 3; index++)
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ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, 0x34343434);
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ODM_SetBBReg(pDM_Odm, 0xe08+index*4, bMaskDWord, 0x03903434);
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for (index = 0; index < 4; index++)
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ODM_SetBBReg(pDM_Odm, 0xe10+index*4, bMaskDWord, 0x34343434);
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);
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ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
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ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b);
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c);
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a );
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
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ODM_delay_ms(1);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
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ODM_delay_ms(50);
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while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK)
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{
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018);
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tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord);
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ODM_delay_ms(10);
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f);
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tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord);
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ODM_delay_ms(10);
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tmpReg = (tmpReg & bMaskHWord) >> 16;
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tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
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if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) {
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
|
||||
ODM_delay_ms(1);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
RetryCount++;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2));
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 DPK Success\n"));
|
||||
pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
RetryCount = 0;
|
||||
|
||||
|
||||
if (pDM_Odm->RFCalibrateInfo.bDPPathAOK) {
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000);
|
||||
|
||||
for (i = rPdp_AntA; i <= 0xb3c; i += 4) {
|
||||
ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path S1 ofsset = 0x%x\n", i));
|
||||
}
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040);
|
||||
ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040);
|
||||
ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920);
|
||||
|
||||
for (i = 0xb4c; i <= 0xb5c; i += 4) {
|
||||
ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
|
||||
}
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
|
||||
} else {
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000);
|
||||
}
|
||||
|
||||
|
||||
if (is2T) {
|
||||
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000);
|
||||
ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
|
||||
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
|
||||
for(index = 0; index < 4; index++)
|
||||
ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]);
|
||||
for(index = 0; index < 2; index++)
|
||||
ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]);
|
||||
for(index = 0; index < 2; index++)
|
||||
ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]);
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788);
|
||||
ODM_delay_ms(1);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788);
|
||||
ODM_delay_ms(50);
|
||||
}
|
||||
|
||||
|
||||
for (index = 0; index < 4; index++)
|
||||
ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434);
|
||||
for (index = 0; index < 2; index++)
|
||||
ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434);
|
||||
for (index = 0; index < 2; index++)
|
||||
ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434);
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f);
|
||||
ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103);
|
||||
|
||||
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b);
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c);
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a);
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
|
||||
while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK)
|
||||
{
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018);
|
||||
tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f);
|
||||
tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord);
|
||||
|
||||
tmpReg = (tmpReg & bMaskHWord) >> 16;
|
||||
tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
|
||||
|
||||
if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) {
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x800000);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
|
||||
ODM_delay_ms(1);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
RetryCount++;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2));
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
|
||||
pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (pDM_Odm->RFCalibrateInfo.bDPPathBOK) {
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x400000);
|
||||
for (i = 0xb60; i <= 0xb9c; i += 4) {
|
||||
ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
|
||||
}
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040);
|
||||
ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050);
|
||||
ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920);
|
||||
|
||||
for (i = 0xbac; i <= 0xbbc; i += 4) {
|
||||
ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
|
||||
}
|
||||
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
|
||||
|
||||
} else {
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++)
|
||||
ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
|
||||
|
||||
|
||||
for (path = 0; path < DP_PATH_NUM; path++) {
|
||||
for (i = 0 ; i < DP_RF_REG_NUM ; i++) {
|
||||
ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]);
|
||||
}
|
||||
}
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);
|
||||
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_PHY_ReloadADDARegisters_8723D(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
|
||||
_PHY_ReloadMACRegisters_8723D(pAdapter, MAC_REG, MAC_backup);
|
||||
#else
|
||||
_PHY_ReloadADDARegisters_8723D(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
|
||||
_PHY_ReloadMACRegisters_8723D(pDM_Odm, MAC_REG, MAC_backup);
|
||||
#endif
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.bDPdone = TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion_8723D()\n"));
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
|
||||
Reference in New Issue
Block a user