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https://github.com/amazingfate/rtl8723ds.git
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rtl8723ds: Initial commit of files
This repository contains the Realtek driver V5.1.1.5_20523.20161209_BTCOEX20161208-1212. At inclusion, the only changes from the Realtek version were to fix any compile warnings or errors. With these changes, the driver builds on kernels through 4.11. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
@@ -0,0 +1,123 @@
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#pragma once
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#ifndef __INC_HW_IMG_H
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#define __INC_HW_IMG_H
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//
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// 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
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//
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#if RT_PLATFORM == PLATFORM_LINUX
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#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
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// For 92C
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#define RTL8192CE_HWIMG_SUPPORT 1
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#define RTL8192CE_TEST_HWIMG_SUPPORT 0
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#define RTL8192CU_HWIMG_SUPPORT 0
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||||
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
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// For 92D
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#define RTL8192DE_HWIMG_SUPPORT 1
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#define RTL8192DE_TEST_HWIMG_SUPPORT 0
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#define RTL8192DU_HWIMG_SUPPORT 0
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#define RTL8192DU_TEST_HWIMG_SUPPORT 0
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// For 8723
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#define RTL8723E_HWIMG_SUPPORT 1
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#define RTL8723U_HWIMG_SUPPORT 0
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#define RTL8723S_HWIMG_SUPPORT 0
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//For 88E
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
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// For 92C
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#define RTL8192CE_HWIMG_SUPPORT 0
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#define RTL8192CE_TEST_HWIMG_SUPPORT 0
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#define RTL8192CU_HWIMG_SUPPORT 1
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#define RTL8192CU_TEST_HWIMG_SUPPORT 0
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//For 92D
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#define RTL8192DE_HWIMG_SUPPORT 0
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#define RTL8192DE_TEST_HWIMG_SUPPORT 0
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#define RTL8192DU_HWIMG_SUPPORT 1
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#define RTL8192DU_TEST_HWIMG_SUPPORT 0
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// For 8723
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#define RTL8723E_HWIMG_SUPPORT 0
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#define RTL8723U_HWIMG_SUPPORT 1
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#define RTL8723S_HWIMG_SUPPORT 0
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//For 88E
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
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// For 92C
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#define RTL8192CE_HWIMG_SUPPORT 0
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#define RTL8192CE_TEST_HWIMG_SUPPORT 0
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#define RTL8192CU_HWIMG_SUPPORT 1
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#define RTL8192CU_TEST_HWIMG_SUPPORT 0
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//For 92D
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#define RTL8192DE_HWIMG_SUPPORT 0
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#define RTL8192DE_TEST_HWIMG_SUPPORT 0
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#define RTL8192DU_HWIMG_SUPPORT 1
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#define RTL8192DU_TEST_HWIMG_SUPPORT 0
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// For 8723
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#define RTL8723E_HWIMG_SUPPORT 0
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#define RTL8723U_HWIMG_SUPPORT 0
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#define RTL8723S_HWIMG_SUPPORT 1
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//For 88E
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#endif
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#else // PLATFORM_WINDOWS & MacOSX
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//For 92C
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#define RTL8192CE_HWIMG_SUPPORT 1
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#define RTL8192CE_TEST_HWIMG_SUPPORT 1
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#define RTL8192CU_HWIMG_SUPPORT 1
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#define RTL8192CU_TEST_HWIMG_SUPPORT 1
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// For 92D
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#define RTL8192DE_HWIMG_SUPPORT 1
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#define RTL8192DE_TEST_HWIMG_SUPPORT 1
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#define RTL8192DU_HWIMG_SUPPORT 1
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#define RTL8192DU_TEST_HWIMG_SUPPORT 1
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#if defined(UNDER_CE)
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// For 8723
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#define RTL8723E_HWIMG_SUPPORT 0
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#define RTL8723U_HWIMG_SUPPORT 0
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#define RTL8723S_HWIMG_SUPPORT 1
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// For 88E
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#else
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// For 8723
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#define RTL8723E_HWIMG_SUPPORT 1
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//#define RTL_8723E_TEST_HWIMG_SUPPORT 1
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#define RTL8723U_HWIMG_SUPPORT 1
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//#define RTL_8723U_TEST_HWIMG_SUPPORT 1
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#define RTL8723S_HWIMG_SUPPORT 1
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//#define RTL_8723S_TEST_HWIMG_SUPPORT 1
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//For 88E
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#define RTL8188EE_HWIMG_SUPPORT 1
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#define RTL8188EU_HWIMG_SUPPORT 1
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#define RTL8188ES_HWIMG_SUPPORT 1
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#endif
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#endif
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#endif //__INC_HW_IMG_H
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,179 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
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* You should have received a copy of the GNU General Public License along with
|
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __HAL_PHY_RF_H__
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#define __HAL_PHY_RF_H__
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#include "phydm_powertracking_ap.h"
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#if (RTL8814A_SUPPORT == 1)
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#include "rtl8814a/phydm_iqk_8814a.h"
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#endif
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#if (RTL8822B_SUPPORT == 1)
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#include "rtl8822b/phydm_iqk_8822b.h"
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#endif
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#if (RTL8821C_SUPPORT == 1)
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#include "rtl8822b/phydm_iqk_8821c.h"
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#endif
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typedef enum _PWRTRACK_CONTROL_METHOD {
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BBSWING,
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TXAGC,
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MIX_MODE,
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TSSI_MODE
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} PWRTRACK_METHOD;
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typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte);
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typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte);
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typedef VOID (*FuncLCK)(PVOID);
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//refine by YuChen for 8814A
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typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
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typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
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typedef VOID (*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
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typedef struct _TXPWRTRACK_CFG {
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u1Byte SwingTableSize_CCK;
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u1Byte SwingTableSize_OFDM;
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u1Byte Threshold_IQK;
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u1Byte Threshold_DPK;
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u1Byte AverageThermalNum;
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u1Byte RfPathCount;
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u4Byte ThermalRegAddr;
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FuncSetPwr ODM_TxPwrTrackSetPwr;
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FuncIQK DoIQK;
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FuncLCK PHY_LCCalibrate;
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FuncSwing GetDeltaSwingTable;
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FuncSwing8814only GetDeltaSwingTable8814only;
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FuncAllSwing GetDeltaAllSwingTable;
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} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
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VOID
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ConfigureTxpowerTrack(
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IN PVOID pDM_VOID,
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OUT PTXPWRTRACK_CFG pConfig
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);
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VOID
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ODM_TXPowerTrackingCallback_ThermalMeter(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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IN PVOID pDM_VOID
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#else
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IN PADAPTER Adapter
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#endif
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);
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#if (RTL8192E_SUPPORT==1)
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VOID
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ODM_TXPowerTrackingCallback_ThermalMeter_92E(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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IN PVOID pDM_VOID
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#else
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IN PADAPTER Adapter
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#endif
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);
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#endif
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#if (RTL8814A_SUPPORT == 1)
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VOID
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ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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IN PVOID pDM_VOID
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#else
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IN PADAPTER Adapter
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#endif
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);
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#elif ODM_IC_11AC_SERIES_SUPPORT
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VOID
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ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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IN PVOID pDM_VOID
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#else
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IN PADAPTER Adapter
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#endif
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);
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#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
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VOID
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ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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IN PVOID pDM_VOID
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#else
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IN PADAPTER Adapter
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#endif
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);
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#endif
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#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M )
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#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#define MAX_TOLERANCE 5
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#define IQK_DELAY_TIME 1 //ms
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//
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// BB/MAC/RF other monitor API
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//
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void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
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IN BOOLEAN bEnableMonitorMode );
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//
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// IQ calibrate
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//
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void
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PHY_IQCalibrate_8192C( IN PADAPTER pAdapter,
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IN BOOLEAN bReCovery);
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//
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// LC calibrate
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//
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void
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PHY_LCCalibrate_8192C( IN PADAPTER pAdapter);
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//
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// AP calibrate
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//
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void
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PHY_APCalibrate_8192C( IN PADAPTER pAdapter,
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IN s1Byte delta);
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#endif
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#define ODM_TARGET_CHNL_NUM_2G_5G 59
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VOID
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ODM_ResetIQKResult(
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IN PVOID pDM_VOID
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);
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u1Byte
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ODM_GetRightChnlPlaceforIQK(
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IN u1Byte chnl
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);
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void phydm_rf_init(IN PVOID pDM_VOID);
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void phydm_rf_watchdog(IN PVOID pDM_VOID);
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#endif // #ifndef __HAL_PHY_RF_H__
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@@ -0,0 +1,807 @@
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/******************************************************************************
|
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*
|
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
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******************************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
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do {\
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for(_offset = 0; _offset < _size; _offset++)\
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{\
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if(_deltaThermal < thermalThreshold[_direction][_offset])\
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{\
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if(_offset != 0)\
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_offset--;\
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break;\
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}\
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} \
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if(_offset >= _size)\
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_offset = _size-1;\
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} while(0)
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|
||||
void ConfigureTxpowerTrack(
|
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IN PVOID pDM_VOID,
|
||||
OUT PTXPWRTRACK_CFG pConfig
|
||||
)
|
||||
{
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||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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|
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#if RTL8192E_SUPPORT
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if (pDM_Odm->SupportICType == ODM_RTL8192E)
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ConfigureTxpowerTrack_8192E(pConfig);
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#endif
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#if RTL8821A_SUPPORT
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if (pDM_Odm->SupportICType == ODM_RTL8821)
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ConfigureTxpowerTrack_8821A(pConfig);
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#endif
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#if RTL8812A_SUPPORT
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if (pDM_Odm->SupportICType == ODM_RTL8812)
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ConfigureTxpowerTrack_8812A(pConfig);
|
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#endif
|
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#if RTL8188E_SUPPORT
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if (pDM_Odm->SupportICType == ODM_RTL8188E)
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ConfigureTxpowerTrack_8188E(pConfig);
|
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#endif
|
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|
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#if RTL8723B_SUPPORT
|
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if (pDM_Odm->SupportICType == ODM_RTL8723B)
|
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ConfigureTxpowerTrack_8723B(pConfig);
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8814A)
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||||
ConfigureTxpowerTrack_8814A(pConfig);
|
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#endif
|
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|
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#if RTL8703B_SUPPORT
|
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if (pDM_Odm->SupportICType == ODM_RTL8703B)
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ConfigureTxpowerTrack_8703B(pConfig);
|
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#endif
|
||||
|
||||
#if RTL8188F_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188F)
|
||||
ConfigureTxpowerTrack_8188F(pConfig);
|
||||
#endif
|
||||
#if RTL8723D_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8723D)
|
||||
ConfigureTxpowerTrack_8723D(pConfig);
|
||||
#endif
|
||||
#if RTL8822B_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8822B)
|
||||
ConfigureTxpowerTrack_8822B(pConfig);
|
||||
#endif
|
||||
#if RTL8821C_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8821C)
|
||||
ConfigureTxpowerTrack_8821C(pConfig);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
//======================================================================
|
||||
// <20121113, Kordan> This function should be called when TxAGC changed.
|
||||
// Otherwise the previous compensation is gone, because we record the
|
||||
// delta of temperature between two TxPowerTracking watch dogs.
|
||||
//
|
||||
// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
|
||||
// need to call this function.
|
||||
//======================================================================
|
||||
VOID
|
||||
ODM_ClearTxPowerTrackingState(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
|
||||
u1Byte p = 0;
|
||||
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
|
||||
|
||||
pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex;
|
||||
pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex;
|
||||
pDM_Odm->RFCalibrateInfo.CCK_index = 0;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
|
||||
{
|
||||
pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = 0;
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = 0;
|
||||
pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0;
|
||||
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/
|
||||
pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0;
|
||||
pRFCalibrateInfo->KfreeOffset[p] = 0;
|
||||
}
|
||||
|
||||
pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/
|
||||
pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/
|
||||
pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/
|
||||
pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/
|
||||
pRFCalibrateInfo->Remnant_CCKSwingIdx = 0;
|
||||
pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter;
|
||||
|
||||
pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo
|
||||
pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_TXPowerTrackingCallback_ThermalMeter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
#else
|
||||
IN PADAPTER Adapter
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
|
||||
|
||||
u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
|
||||
s1Byte diff_DPK[4] = {0};
|
||||
u1Byte ThermalValue_AVG_count = 0;
|
||||
u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4;
|
||||
|
||||
u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur
|
||||
u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel)
|
||||
u1Byte PowerTrackingType = pHalData->RfPowerTrackingType;
|
||||
u1Byte XtalOffsetEanble = 0;
|
||||
|
||||
TXPWRTRACK_CFG c;
|
||||
|
||||
//4 1. The following TWO tables decide the final index of OFDM/CCK swing table.
|
||||
pu1Byte deltaSwingTableIdx_TUP_A = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TDOWN_A = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TUP_B = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TDOWN_B = NULL;
|
||||
/*for 8814 add by Yu Chen*/
|
||||
pu1Byte deltaSwingTableIdx_TUP_C = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TDOWN_C = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TUP_D = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TDOWN_D = NULL;
|
||||
/*for Xtal Offset by James.Tung*/
|
||||
ps1Byte deltaSwingTableXtal_UP = NULL;
|
||||
ps1Byte deltaSwingTableXtal_DOWN = NULL;
|
||||
|
||||
//4 2. Initilization ( 7 steps in total )
|
||||
|
||||
ConfigureTxpowerTrack(pDM_Odm, &c);
|
||||
|
||||
(*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A,
|
||||
(pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B);
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/
|
||||
(*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C,
|
||||
(pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D);
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/
|
||||
(*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN);
|
||||
|
||||
pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/
|
||||
pRFCalibrateInfo->bTXPowerTrackingInit = TRUE;
|
||||
|
||||
/*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl;
|
||||
<Kordan> We should keep updating the control variable according to HalData.
|
||||
<Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
pRFCalibrateInfo->RegA24 = 0x090e1317;
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
if (pDM_Odm->mp_mode == TRUE)
|
||||
pRFCalibrateInfo->RegA24 = 0x090e1317;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n",
|
||||
pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex));
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter));
|
||||
ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E
|
||||
|
||||
/*add log by zhao he, check c80/c94/c14/ca0 value*/
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8723D) {
|
||||
RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord);
|
||||
RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord);
|
||||
RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord);
|
||||
Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4));
|
||||
}
|
||||
|
||||
if (!pRFCalibrateInfo->TxPowerTrackControl)
|
||||
return;
|
||||
|
||||
|
||||
/*4 3. Initialize ThermalValues of RFCalibrateInfo*/
|
||||
|
||||
if (pRFCalibrateInfo->bReloadtxpowerindex)
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
|
||||
|
||||
/*4 4. Calculate average thermal meter*/
|
||||
|
||||
pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue;
|
||||
pRFCalibrateInfo->ThermalValue_AVG_index++;
|
||||
if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/
|
||||
pRFCalibrateInfo->ThermalValue_AVG_index = 0;
|
||||
|
||||
for(i = 0; i < c.AverageThermalNum; i++)
|
||||
{
|
||||
if (pRFCalibrateInfo->ThermalValue_AVG[i]) {
|
||||
ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i];
|
||||
ThermalValue_AVG_count++;
|
||||
}
|
||||
}
|
||||
|
||||
if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times
|
||||
{
|
||||
ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
}
|
||||
|
||||
//4 5. Calculate delta, delta_LCK, delta_IQK.
|
||||
|
||||
//"delta" here is used to determine whether thermal value changes or not.
|
||||
delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue);
|
||||
delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue);
|
||||
delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue);
|
||||
|
||||
if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/
|
||||
pRFCalibrateInfo->ThermalValue_IQK = ThermalValue;
|
||||
delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n"));
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p];
|
||||
|
||||
/*4 6. If necessary, do LCK.*/
|
||||
|
||||
if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/
|
||||
if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n"));
|
||||
pRFCalibrateInfo->ThermalValue_LCK = ThermalValue;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) {
|
||||
if (c.PHY_LCCalibrate)
|
||||
(*c.PHY_LCCalibrate)(pDM_Odm);
|
||||
}
|
||||
|
||||
delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue);
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
|
||||
|
||||
/* Delta temperature is equal to or larger than 20 centigrade.*/
|
||||
if (delta_LCK >= c.Threshold_IQK) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK));
|
||||
pRFCalibrateInfo->ThermalValue_LCK = ThermalValue;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) {
|
||||
if (c.PHY_LCCalibrate)
|
||||
(*c.PHY_LCCalibrate)(pDM_Odm);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
|
||||
|
||||
if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl)
|
||||
{
|
||||
//"delta" here is used to record the absolute value of differrence.
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
|
||||
#else
|
||||
delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
|
||||
#endif
|
||||
if (delta >= TXPWR_TRACK_TABLE_SIZE)
|
||||
delta = TXPWR_TRACK_TABLE_SIZE - 1;
|
||||
|
||||
/*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
if(ThermalValue > pHalData->EEPROMThermalMeter) {
|
||||
#else
|
||||
if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta]));
|
||||
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta]));
|
||||
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta]));
|
||||
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta]));
|
||||
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save XtalOffset from Xtal table*/
|
||||
pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta]));
|
||||
pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta];
|
||||
|
||||
if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset)
|
||||
XtalOffsetEanble = 0;
|
||||
else
|
||||
XtalOffsetEanble = 1;
|
||||
}
|
||||
|
||||
} else {
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/
|
||||
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta]));
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta]));
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta]));
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta]));
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save XtalOffset from Xtal table*/
|
||||
pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta]));
|
||||
pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta];
|
||||
|
||||
if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset)
|
||||
XtalOffsetEanble = 0;
|
||||
else
|
||||
XtalOffsetEanble = 1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p));
|
||||
|
||||
if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = 0;
|
||||
else
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p]));
|
||||
|
||||
pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p];
|
||||
pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p];
|
||||
|
||||
pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index;
|
||||
pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p];
|
||||
|
||||
/*************Print BB Swing Base and Index Offset*************/
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p]));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p]));
|
||||
|
||||
/*4 7.1 Handle boundary conditions of index.*/
|
||||
|
||||
if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1)
|
||||
pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1;
|
||||
else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index)
|
||||
pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n========================================================================================================\n"));
|
||||
|
||||
if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1)
|
||||
pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1;
|
||||
else if (pRFCalibrateInfo->CCK_index <= 0)
|
||||
pRFCalibrateInfo->CCK_index = 0;
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n",
|
||||
pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue));
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = 0;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
|
||||
pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n",
|
||||
pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p]));
|
||||
}
|
||||
|
||||
if ((pDM_Odm->SupportICType & ODM_RTL8814A)) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType));
|
||||
|
||||
if (PowerTrackingType == 0) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
|
||||
} else if (PowerTrackingType == 1) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0);
|
||||
} else if (PowerTrackingType == 2) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0);
|
||||
} else if (PowerTrackingType == 3) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0);
|
||||
}
|
||||
pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/
|
||||
|
||||
} else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 ||
|
||||
pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 ||
|
||||
pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 ||
|
||||
pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) &&
|
||||
pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) {
|
||||
//4 7.2 Configure the Swing Table to adjust Tx Power.
|
||||
|
||||
pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/
|
||||
//
|
||||
// 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
|
||||
// to increase TX power. Otherwise, EVM will be bad.
|
||||
//
|
||||
// 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
|
||||
if (ThermalValue > pRFCalibrateInfo->ThermalValue) {
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue));
|
||||
}
|
||||
} else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue));
|
||||
}
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (ThermalValue > pHalData->EEPROMThermalMeter)
|
||||
#else
|
||||
if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)
|
||||
#endif
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8723D || pDM_Odm->SupportICType == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8723D || pDM_Odm->SupportICType == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel);
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p];
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue));
|
||||
|
||||
pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/
|
||||
|
||||
}
|
||||
|
||||
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) {
|
||||
|
||||
if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) {
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (ThermalValue > pHalData->EEPROMThermalMeter) {
|
||||
#else
|
||||
if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
(*c.ODM_TxXtalTrackSetXtal)(pDM_Odm);
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
(*c.ODM_TxXtalTrackSetXtal)(pDM_Odm);
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
if (!IS_HARDWARE_TYPE_8723B(Adapter)) {
|
||||
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
|
||||
if (delta_IQK >= c.Threshold_IQK) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK));
|
||||
if (!pRFCalibrateInfo->bIQKInProgress)
|
||||
(*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8);
|
||||
}
|
||||
}
|
||||
if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK));
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) {
|
||||
s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value);
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0);
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK));
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) {
|
||||
s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value);
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0);
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n"));
|
||||
|
||||
pRFCalibrateInfo->TXPowercount = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//3============================================================
|
||||
//3 IQ Calibration
|
||||
//3============================================================
|
||||
|
||||
VOID
|
||||
ODM_ResetIQKResult(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
|
||||
{
|
||||
u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
|
||||
{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165};
|
||||
u1Byte place = chnl;
|
||||
|
||||
|
||||
if(chnl > 14)
|
||||
{
|
||||
for(place = 14; place<sizeof(channel_all); place++)
|
||||
{
|
||||
if(channel_all[place] == chnl)
|
||||
{
|
||||
return place-13;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
VOID
|
||||
odm_IQCalibrate(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (*pDM_Odm->pIsFcsModeEnable)
|
||||
return;
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter))
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (pDM_Odm->bLinked) {
|
||||
if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) {
|
||||
pDM_Odm->preChannel = *pDM_Odm->pChannel;
|
||||
pDM_Odm->LinkedInterval = 0;
|
||||
}
|
||||
|
||||
if (pDM_Odm->LinkedInterval < 3)
|
||||
pDM_Odm->LinkedInterval++;
|
||||
|
||||
if (pDM_Odm->LinkedInterval == 2) {
|
||||
if (IS_HARDWARE_TYPE_8814A(Adapter)) {
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
PHY_IQCalibrate_8814A(pDM_Odm, FALSE);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
else if (IS_HARDWARE_TYPE_8822B(Adapter))
|
||||
PHY_IQCalibrate_8822B(pDM_Odm, FALSE);
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
else if (IS_HARDWARE_TYPE_8821C(Adapter))
|
||||
PHY_IQCalibrate_8821C(pDM_Odm, FALSE);
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
else if (IS_HARDWARE_TYPE_8821(Adapter))
|
||||
PHY_IQCalibrate_8821A(pDM_Odm, FALSE);
|
||||
#endif
|
||||
}
|
||||
} else
|
||||
pDM_Odm->LinkedInterval = 0;
|
||||
}
|
||||
|
||||
void phydm_rf_init(IN PVOID pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
odm_TXPowerTrackingInit(pDM_Odm);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
ODM_ClearTxPowerTrackingState(pDM_Odm);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
PHY_IQCalibrate_8814A_Init(pDM_Odm);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void phydm_rf_watchdog(IN PVOID pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
ODM_TXPowerTrackingCheck(pDM_Odm);
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
|
||||
odm_IQCalibrate(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,118 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
|
||||
#include "phydm_kfree.h"
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#include "rtl8814a/phydm_iqk_8814a.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#include "rtl8822b/phydm_iqk_8822b.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#include "rtl8821c/phydm_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
#include "phydm_powertracking_ce.h"
|
||||
|
||||
|
||||
typedef enum _SPUR_CAL_METHOD {
|
||||
PLL_RESET,
|
||||
AFE_PHASE_SEL
|
||||
} SPUR_CAL_METHOD;
|
||||
|
||||
typedef enum _PWRTRACK_CONTROL_METHOD {
|
||||
BBSWING,
|
||||
TXAGC,
|
||||
MIX_MODE,
|
||||
TSSI_MODE,
|
||||
MIX_2G_TSSI_5G_MODE,
|
||||
MIX_5G_TSSI_2G_MODE
|
||||
} PWRTRACK_METHOD;
|
||||
|
||||
typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte);
|
||||
typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte);
|
||||
typedef VOID (*FuncLCK)(PVOID);
|
||||
typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
|
||||
typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
|
||||
typedef VOID(*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*);
|
||||
typedef VOID(*FuncSetXtal)(PVOID);
|
||||
|
||||
typedef struct _TXPWRTRACK_CFG {
|
||||
u1Byte SwingTableSize_CCK;
|
||||
u1Byte SwingTableSize_OFDM;
|
||||
u1Byte Threshold_IQK;
|
||||
u1Byte Threshold_DPK;
|
||||
u1Byte AverageThermalNum;
|
||||
u1Byte RfPathCount;
|
||||
u4Byte ThermalRegAddr;
|
||||
FuncSetPwr ODM_TxPwrTrackSetPwr;
|
||||
FuncIQK DoIQK;
|
||||
FuncLCK PHY_LCCalibrate;
|
||||
FuncSwing GetDeltaSwingTable;
|
||||
FuncSwing8814only GetDeltaSwingTable8814only;
|
||||
FuncSwingXtal GetDeltaSwingXtalTable;
|
||||
FuncSetXtal ODM_TxXtalTrackSetXtal;
|
||||
} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
|
||||
|
||||
VOID
|
||||
ConfigureTxpowerTrack(
|
||||
IN PVOID pDM_VOID,
|
||||
OUT PTXPWRTRACK_CFG pConfig
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
ODM_ClearTxPowerTrackingState(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_TXPowerTrackingCallback_ThermalMeter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
IN PVOID pDM_VOID
|
||||
#else
|
||||
IN PADAPTER Adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
|
||||
VOID
|
||||
ODM_ResetIQKResult(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
u1Byte
|
||||
ODM_GetRightChnlPlaceforIQK(
|
||||
IN u1Byte chnl
|
||||
);
|
||||
|
||||
void phydm_rf_init( IN PVOID pDM_VOID);
|
||||
void phydm_rf_watchdog( IN PVOID pDM_VOID);
|
||||
|
||||
#endif // #ifndef __HAL_PHY_RF_H__
|
||||
|
||||
@@ -0,0 +1,792 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
|
||||
do {\
|
||||
for(_offset = 0; _offset < _size; _offset++)\
|
||||
{\
|
||||
if(_deltaThermal < thermalThreshold[_direction][_offset])\
|
||||
{\
|
||||
if(_offset != 0)\
|
||||
_offset--;\
|
||||
break;\
|
||||
}\
|
||||
} \
|
||||
if(_offset >= _size)\
|
||||
_offset = _size-1;\
|
||||
} while(0)
|
||||
|
||||
void ConfigureTxpowerTrack(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT PTXPWRTRACK_CFG pConfig
|
||||
)
|
||||
{
|
||||
#if RTL8192E_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8192E)
|
||||
ConfigureTxpowerTrack_8192E(pConfig);
|
||||
#endif
|
||||
#if RTL8821A_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8821)
|
||||
ConfigureTxpowerTrack_8821A(pConfig);
|
||||
#endif
|
||||
#if RTL8812A_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8812)
|
||||
ConfigureTxpowerTrack_8812A(pConfig);
|
||||
#endif
|
||||
#if RTL8188E_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E)
|
||||
ConfigureTxpowerTrack_8188E(pConfig);
|
||||
#endif
|
||||
|
||||
#if RTL8188F_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188F)
|
||||
ConfigureTxpowerTrack_8188F(pConfig);
|
||||
#endif
|
||||
|
||||
#if RTL8723B_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8723B)
|
||||
ConfigureTxpowerTrack_8723B(pConfig);
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8814A)
|
||||
ConfigureTxpowerTrack_8814A(pConfig);
|
||||
#endif
|
||||
|
||||
#if RTL8703B_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8703B)
|
||||
ConfigureTxpowerTrack_8703B(pConfig);
|
||||
#endif
|
||||
|
||||
#if RTL8822B_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8822B)
|
||||
ConfigureTxpowerTrack_8822B(pConfig);
|
||||
#endif
|
||||
|
||||
#if RTL8723D_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8723D)
|
||||
ConfigureTxpowerTrack_8723D(pConfig);
|
||||
#endif
|
||||
|
||||
#if RTL8821C_SUPPORT
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8821C)
|
||||
ConfigureTxpowerTrack_8821C(pConfig);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
//======================================================================
|
||||
// <20121113, Kordan> This function should be called when TxAGC changed.
|
||||
// Otherwise the previous compensation is gone, because we record the
|
||||
// delta of temperature between two TxPowerTracking watch dogs.
|
||||
//
|
||||
// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
|
||||
// need to call this function.
|
||||
//======================================================================
|
||||
VOID
|
||||
ODM_ClearTxPowerTrackingState(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
|
||||
u1Byte p = 0;
|
||||
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
|
||||
|
||||
pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex;
|
||||
pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex;
|
||||
pRFCalibrateInfo->CCK_index = 0;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
|
||||
{
|
||||
pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = 0;
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = 0;
|
||||
pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0;
|
||||
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/
|
||||
pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0;
|
||||
pRFCalibrateInfo->KfreeOffset[p] = 0;
|
||||
}
|
||||
|
||||
pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/
|
||||
pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/
|
||||
pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/
|
||||
pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/
|
||||
pRFCalibrateInfo->Remnant_CCKSwingIdx = 0;
|
||||
pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter;
|
||||
|
||||
pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo
|
||||
pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_TXPowerTrackingCallback_ThermalMeter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
#else
|
||||
IN PADAPTER Adapter
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
|
||||
|
||||
u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
|
||||
s1Byte diff_DPK[4] = {0};
|
||||
u1Byte ThermalValue_AVG_count = 0;
|
||||
u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4;
|
||||
|
||||
u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur
|
||||
u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel)
|
||||
u1Byte PowerTrackingType = pHalData->RfPowerTrackingType;
|
||||
u1Byte XtalOffsetEanble = 0;
|
||||
|
||||
TXPWRTRACK_CFG c;
|
||||
|
||||
//4 1. The following TWO tables decide the final index of OFDM/CCK swing table.
|
||||
pu1Byte deltaSwingTableIdx_TUP_A = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TDOWN_A = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TUP_B = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TDOWN_B = NULL;
|
||||
/*for 8814 add by Yu Chen*/
|
||||
pu1Byte deltaSwingTableIdx_TUP_C = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TDOWN_C = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TUP_D = NULL;
|
||||
pu1Byte deltaSwingTableIdx_TDOWN_D = NULL;
|
||||
/*for Xtal Offset by James.Tung*/
|
||||
ps1Byte deltaSwingTableXtal_UP = NULL;
|
||||
ps1Byte deltaSwingTableXtal_DOWN = NULL;
|
||||
|
||||
//4 2. Initilization ( 7 steps in total )
|
||||
|
||||
ConfigureTxpowerTrack(pDM_Odm, &c);
|
||||
|
||||
(*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A,
|
||||
(pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B);
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/
|
||||
(*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C,
|
||||
(pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D);
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/
|
||||
(*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN);
|
||||
|
||||
|
||||
pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/
|
||||
pRFCalibrateInfo->bTXPowerTrackingInit = TRUE;
|
||||
|
||||
/*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl;
|
||||
<Kordan> We should keep updating the control variable according to HalData.
|
||||
<Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
pRFCalibrateInfo->RegA24 = 0x090e1317;
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
if (pDM_Odm->mp_mode == TRUE)
|
||||
pRFCalibrateInfo->RegA24 = 0x090e1317;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n",
|
||||
pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex));
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter));
|
||||
ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E
|
||||
|
||||
/*add log by zhao he, check c80/c94/c14/ca0 value*/
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8723D) {
|
||||
RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord);
|
||||
RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord);
|
||||
RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord);
|
||||
Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4));
|
||||
}
|
||||
|
||||
if (!pRFCalibrateInfo->TxPowerTrackControl)
|
||||
return;
|
||||
|
||||
|
||||
/*4 3. Initialize ThermalValues of RFCalibrateInfo*/
|
||||
|
||||
if (pRFCalibrateInfo->bReloadtxpowerindex)
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
|
||||
|
||||
/*4 4. Calculate average thermal meter*/
|
||||
|
||||
pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue;
|
||||
pRFCalibrateInfo->ThermalValue_AVG_index++;
|
||||
if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/
|
||||
pRFCalibrateInfo->ThermalValue_AVG_index = 0;
|
||||
|
||||
for(i = 0; i < c.AverageThermalNum; i++)
|
||||
{
|
||||
if (pRFCalibrateInfo->ThermalValue_AVG[i]) {
|
||||
ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i];
|
||||
ThermalValue_AVG_count++;
|
||||
}
|
||||
}
|
||||
|
||||
if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times
|
||||
{
|
||||
ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
}
|
||||
|
||||
//4 5. Calculate delta, delta_LCK, delta_IQK.
|
||||
|
||||
//"delta" here is used to determine whether thermal value changes or not.
|
||||
delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue);
|
||||
delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue);
|
||||
delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue);
|
||||
|
||||
if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/
|
||||
pRFCalibrateInfo->ThermalValue_IQK = ThermalValue;
|
||||
delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n"));
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p];
|
||||
|
||||
/*4 6. If necessary, do LCK.*/
|
||||
|
||||
if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/
|
||||
if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n"));
|
||||
pRFCalibrateInfo->ThermalValue_LCK = ThermalValue;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) {
|
||||
if (c.PHY_LCCalibrate)
|
||||
(*c.PHY_LCCalibrate)(pDM_Odm);
|
||||
}
|
||||
|
||||
delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue);
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
|
||||
|
||||
/* Delta temperature is equal to or larger than 20 centigrade.*/
|
||||
if (delta_LCK >= c.Threshold_IQK) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK));
|
||||
pRFCalibrateInfo->ThermalValue_LCK = ThermalValue;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) {
|
||||
if (c.PHY_LCCalibrate)
|
||||
(*c.PHY_LCCalibrate)(pDM_Odm);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
|
||||
|
||||
if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl)
|
||||
{
|
||||
//"delta" here is used to record the absolute value of differrence.
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
|
||||
#else
|
||||
delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
|
||||
#endif
|
||||
if (delta >= TXPWR_TRACK_TABLE_SIZE)
|
||||
delta = TXPWR_TRACK_TABLE_SIZE - 1;
|
||||
|
||||
/*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
if(ThermalValue > pHalData->EEPROMThermalMeter) {
|
||||
#else
|
||||
if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta]));
|
||||
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta]));
|
||||
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta]));
|
||||
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta]));
|
||||
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save XtalOffset from Xtal table*/
|
||||
pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta]));
|
||||
pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta];
|
||||
|
||||
if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset)
|
||||
XtalOffsetEanble = 0;
|
||||
else
|
||||
XtalOffsetEanble = 1;
|
||||
}
|
||||
|
||||
} else {
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/
|
||||
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta]));
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta]));
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta]));
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta]));
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta];
|
||||
pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save XtalOffset from Xtal table*/
|
||||
pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta]));
|
||||
pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta];
|
||||
|
||||
if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset)
|
||||
XtalOffsetEanble = 0;
|
||||
else
|
||||
XtalOffsetEanble = 1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p));
|
||||
|
||||
if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = 0;
|
||||
else
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p]));
|
||||
|
||||
pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p];
|
||||
pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p];
|
||||
|
||||
pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index;
|
||||
pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p];
|
||||
|
||||
/*************Print BB Swing Base and Index Offset*************/
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p]));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p]));
|
||||
|
||||
/*4 7.1 Handle boundary conditions of index.*/
|
||||
|
||||
if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1)
|
||||
pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1;
|
||||
else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index)
|
||||
pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n========================================================================================================\n"));
|
||||
|
||||
if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1)
|
||||
pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1;
|
||||
else if (pRFCalibrateInfo->CCK_index <= 0)
|
||||
pRFCalibrateInfo->CCK_index = 0;
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n",
|
||||
pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue));
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = 0;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
|
||||
pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n",
|
||||
pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p]));
|
||||
}
|
||||
|
||||
if ((pDM_Odm->SupportICType & ODM_RTL8814A)) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType));
|
||||
|
||||
if (PowerTrackingType == 0) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
|
||||
} else if (PowerTrackingType == 1) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0);
|
||||
} else if (PowerTrackingType == 2) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0);
|
||||
} else if (PowerTrackingType == 3) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0);
|
||||
}
|
||||
pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/
|
||||
|
||||
} else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 ||
|
||||
pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 ||
|
||||
pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 ||
|
||||
pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) &&
|
||||
pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) {
|
||||
//4 7.2 Configure the Swing Table to adjust Tx Power.
|
||||
|
||||
pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/
|
||||
//
|
||||
// 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
|
||||
// to increase TX power. Otherwise, EVM will be bad.
|
||||
//
|
||||
// 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
|
||||
if (ThermalValue > pRFCalibrateInfo->ThermalValue) {
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue));
|
||||
}
|
||||
} else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue));
|
||||
}
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (ThermalValue > pHalData->EEPROMThermalMeter)
|
||||
#else
|
||||
if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)
|
||||
#endif
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8723D || pDM_Odm->SupportICType == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8723D || pDM_Odm->SupportICType == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel);
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p];
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue));
|
||||
|
||||
pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/
|
||||
|
||||
}
|
||||
|
||||
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) {
|
||||
|
||||
if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) {
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (ThermalValue > pHalData->EEPROMThermalMeter) {
|
||||
#else
|
||||
if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
(*c.ODM_TxXtalTrackSetXtal)(pDM_Odm);
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
|
||||
(*c.ODM_TxXtalTrackSetXtal)(pDM_Odm);
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
if (!IS_HARDWARE_TYPE_8723B(Adapter)) {
|
||||
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
|
||||
if (delta_IQK >= c.Threshold_IQK) {
|
||||
pRFCalibrateInfo->ThermalValue_IQK = ThermalValue;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK));
|
||||
if (!pRFCalibrateInfo->bIQKInProgress)
|
||||
(*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8);
|
||||
}
|
||||
}
|
||||
if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK));
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) {
|
||||
s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value);
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0);
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK));
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) {
|
||||
s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value);
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0);
|
||||
ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n"));
|
||||
|
||||
pRFCalibrateInfo->TXPowercount = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//3============================================================
|
||||
//3 IQ Calibration
|
||||
//3============================================================
|
||||
|
||||
VOID
|
||||
ODM_ResetIQKResult(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
|
||||
{
|
||||
u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
|
||||
{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165};
|
||||
u1Byte place = chnl;
|
||||
|
||||
|
||||
if(chnl > 14)
|
||||
{
|
||||
for(place = 14; place<sizeof(channel_all); place++)
|
||||
{
|
||||
if(channel_all[place] == chnl)
|
||||
{
|
||||
return place-13;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
VOID
|
||||
odm_IQCalibrate(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (*pDM_Odm->pIsFcsModeEnable)
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (pDM_Odm->bLinked) {
|
||||
|
||||
if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) {
|
||||
pDM_Odm->preChannel = *pDM_Odm->pChannel;
|
||||
pDM_Odm->LinkedInterval = 0;
|
||||
}
|
||||
|
||||
if (pDM_Odm->LinkedInterval < 3)
|
||||
pDM_Odm->LinkedInterval++;
|
||||
|
||||
if (pDM_Odm->LinkedInterval == 2) {
|
||||
PHY_IQCalibrate(Adapter, FALSE);
|
||||
}
|
||||
} else
|
||||
pDM_Odm->LinkedInterval = 0;
|
||||
|
||||
}
|
||||
|
||||
void phydm_rf_init(IN PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
|
||||
odm_TXPowerTrackingInit(pDM_Odm);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
ODM_ClearTxPowerTrackingState(pDM_Odm);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
PHY_IQCalibrate_8814A_Init(pDM_Odm);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void phydm_rf_watchdog(IN PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
|
||||
|
||||
if(!pMgntInfo->IQKBeforeConnection)
|
||||
{
|
||||
ODM_TXPowerTrackingCheck(pDM_Odm);
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
|
||||
odm_IQCalibrate(pDM_Odm);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
|
||||
#include "phydm_kfree.h"
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#include "rtl8814a/phydm_iqk_8814a.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#include "rtl8822b/phydm_iqk_8822b.h"
|
||||
#include "../mac/Halmac_type.h"
|
||||
#endif
|
||||
#include "phydm_powertracking_win.h"
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#include "rtl8821c/phydm_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
typedef enum _SPUR_CAL_METHOD {
|
||||
PLL_RESET,
|
||||
AFE_PHASE_SEL
|
||||
} SPUR_CAL_METHOD;
|
||||
|
||||
typedef enum _PWRTRACK_CONTROL_METHOD {
|
||||
BBSWING,
|
||||
TXAGC,
|
||||
MIX_MODE,
|
||||
TSSI_MODE,
|
||||
MIX_2G_TSSI_5G_MODE,
|
||||
MIX_5G_TSSI_2G_MODE
|
||||
} PWRTRACK_METHOD;
|
||||
|
||||
typedef VOID(*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte);
|
||||
typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte);
|
||||
typedef VOID(*FuncLCK)(PVOID);
|
||||
typedef VOID(*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
|
||||
typedef VOID(*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
|
||||
typedef VOID (*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*);
|
||||
typedef VOID (*FuncSetXtal)(PVOID);
|
||||
typedef VOID(*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
|
||||
|
||||
typedef struct _TXPWRTRACK_CFG {
|
||||
u1Byte SwingTableSize_CCK;
|
||||
u1Byte SwingTableSize_OFDM;
|
||||
u1Byte Threshold_IQK;
|
||||
u1Byte Threshold_DPK;
|
||||
u1Byte AverageThermalNum;
|
||||
u1Byte RfPathCount;
|
||||
u4Byte ThermalRegAddr;
|
||||
FuncSetPwr ODM_TxPwrTrackSetPwr;
|
||||
FuncIQK DoIQK;
|
||||
FuncLCK PHY_LCCalibrate;
|
||||
FuncSwing GetDeltaSwingTable;
|
||||
FuncSwing8814only GetDeltaSwingTable8814only;
|
||||
FuncSwingXtal GetDeltaSwingXtalTable;
|
||||
FuncSetXtal ODM_TxXtalTrackSetXtal;
|
||||
FuncAllSwing GetDeltaAllSwingTable;
|
||||
} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
|
||||
|
||||
VOID
|
||||
ConfigureTxpowerTrack(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT PTXPWRTRACK_CFG pConfig
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
ODM_ClearTxPowerTrackingState(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_TXPowerTrackingCallback_ThermalMeter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
#else
|
||||
IN PADAPTER Adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
|
||||
VOID
|
||||
ODM_ResetIQKResult(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u1Byte
|
||||
ODM_GetRightChnlPlaceforIQK(
|
||||
IN u1Byte chnl
|
||||
);
|
||||
|
||||
VOID odm_IQCalibrate(IN PDM_ODM_T pDM_Odm);
|
||||
VOID phydm_rf_init( IN PDM_ODM_T pDM_Odm);
|
||||
VOID phydm_rf_watchdog( IN PDM_ODM_T pDM_Odm);
|
||||
|
||||
#endif // #ifndef __HAL_PHY_RF_H__
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
+3340
File diff suppressed because it is too large
Load Diff
+1299
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,106 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMACS_H__
|
||||
#define __PHYDMACS_H__
|
||||
|
||||
#define ACS_VERSION "1.1" /*20150729 by YuChen*/
|
||||
#define CLM_VERSION "1.0"
|
||||
|
||||
#define ODM_MAX_CHANNEL_2G 14
|
||||
#define ODM_MAX_CHANNEL_5G 24
|
||||
|
||||
// For phydm_AutoChannelSelectSettingAP()
|
||||
#define STORE_DEFAULT_NHM_SETTING 0
|
||||
#define RESTORE_DEFAULT_NHM_SETTING 1
|
||||
#define ACS_NHM_SETTING 2
|
||||
|
||||
typedef struct _ACS_
|
||||
{
|
||||
BOOLEAN bForceACSResult;
|
||||
u1Byte CleanChannel_2G;
|
||||
u1Byte CleanChannel_5G;
|
||||
u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times
|
||||
u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G];
|
||||
|
||||
#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
|
||||
u1Byte ACS_Step;
|
||||
// NHM Count 0-11
|
||||
u1Byte NHM_Cnt[14][11];
|
||||
|
||||
// AC-Series, for storing previous setting
|
||||
u4Byte Reg0x990;
|
||||
u4Byte Reg0x994;
|
||||
u4Byte Reg0x998;
|
||||
u4Byte Reg0x99C;
|
||||
u1Byte Reg0x9A0; // u1Byte
|
||||
|
||||
// N-Series, for storing previous setting
|
||||
u4Byte Reg0x890;
|
||||
u4Byte Reg0x894;
|
||||
u4Byte Reg0x898;
|
||||
u4Byte Reg0x89C;
|
||||
u1Byte Reg0xE28; // u1Byte
|
||||
#endif
|
||||
|
||||
}ACS, *PACS;
|
||||
|
||||
|
||||
VOID
|
||||
odm_AutoChannelSelectInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_AutoChannelSelectReset(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_AutoChannelSelect(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Channel
|
||||
);
|
||||
|
||||
u1Byte
|
||||
ODM_GetAutoChannelSelectResult(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Band
|
||||
);
|
||||
|
||||
#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
|
||||
|
||||
VOID
|
||||
phydm_AutoChannelSelectSettingAP(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte Setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING
|
||||
IN u4Byte acs_step
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_GetNHMStatisticsAP(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte idx, // @ 2G, Real channel number = idx+1
|
||||
IN u4Byte acs_step
|
||||
);
|
||||
|
||||
#endif //#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
|
||||
|
||||
#endif //#ifndef __PHYDMACS_H__
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,222 @@
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMADAPTIVITY_H__
|
||||
#define __PHYDMADAPTIVITY_H__
|
||||
|
||||
#define ADAPTIVITY_VERSION "9.3.4" /*20160512 changed by Kevin, modify 0xce8[13]=1 for 8197F when adaptivity is enabled*/
|
||||
|
||||
#define PwdBUpperBound 7
|
||||
#define DFIRloss 5
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
typedef enum _tag_PhyDM_REGULATION_Type {
|
||||
REGULATION_FCC = 0,
|
||||
REGULATION_MKK = 1,
|
||||
REGULATION_ETSI = 2,
|
||||
REGULATION_WW = 3,
|
||||
|
||||
MAX_REGULATION_NUM = 4
|
||||
} PhyDM_REGULATION_TYPE;
|
||||
#endif
|
||||
|
||||
typedef enum _PHYDM_ADAPTIVITY_Info_Definition {
|
||||
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
|
||||
PHYDM_ADAPINFO_DCBACKOFF,
|
||||
PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
|
||||
PHYDM_ADAPINFO_TH_L2H_INI,
|
||||
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
|
||||
PHYDM_ADAPINFO_AP_NUM_TH
|
||||
|
||||
} PHYDM_ADAPINFO_E;
|
||||
|
||||
|
||||
|
||||
typedef enum tag_PhyDM_set_LNA {
|
||||
PhyDM_disable_LNA = 0,
|
||||
PhyDM_enable_LNA = 1,
|
||||
} PhyDM_set_LNA;
|
||||
|
||||
|
||||
typedef enum tag_PhyDM_TRx_MUX_Type
|
||||
{
|
||||
PhyDM_SHUTDOWN = 0,
|
||||
PhyDM_STANDBY_MODE = 1,
|
||||
PhyDM_TX_MODE = 2,
|
||||
PhyDM_RX_MODE = 3
|
||||
}PhyDM_Trx_MUX_Type;
|
||||
|
||||
typedef enum tag_PhyDM_MACEDCCA_Type
|
||||
{
|
||||
PhyDM_IGNORE_EDCCA = 0,
|
||||
PhyDM_DONT_IGNORE_EDCCA = 1
|
||||
}PhyDM_MACEDCCA_Type;
|
||||
|
||||
typedef struct _ADAPTIVITY_STATISTICS {
|
||||
s1Byte TH_L2H_ini_backup;
|
||||
s1Byte TH_EDCCA_HL_diff_backup;
|
||||
s1Byte IGI_Base;
|
||||
u1Byte IGI_target;
|
||||
u1Byte NHMWait;
|
||||
s1Byte H2L_lb;
|
||||
s1Byte L2H_lb;
|
||||
BOOLEAN bFirstLink;
|
||||
BOOLEAN bCheck;
|
||||
BOOLEAN DynamicLinkAdaptivity;
|
||||
u1Byte APNumTH;
|
||||
u1Byte AdajustIGILevel;
|
||||
BOOLEAN AcsForAdaptivity;
|
||||
s1Byte backupL2H;
|
||||
s1Byte backupH2L;
|
||||
BOOLEAN bStopEDCCA;
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_WORK_ITEM phydm_pauseEDCCAWorkItem;
|
||||
RT_WORK_ITEM phydm_resumeEDCCAWorkItem;
|
||||
#endif
|
||||
} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS;
|
||||
|
||||
VOID
|
||||
phydm_pauseEDCCA(
|
||||
IN PVOID pDM_VOID,
|
||||
IN BOOLEAN bPasueEDCCA
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_CheckAdaptivity(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_CheckEnvironment(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_NHMCounterStatisticsInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_NHMCounterStatistics(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_NHMCounterStatisticsReset(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_GetNHMCounterStatistics(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_MACEDCCAState(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PhyDM_MACEDCCA_Type State
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_SetEDCCAThreshold(
|
||||
IN PVOID pDM_VOID,
|
||||
IN s1Byte H2L,
|
||||
IN s1Byte L2H
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_SetTRxMux(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PhyDM_Trx_MUX_Type txMode,
|
||||
IN PhyDM_Trx_MUX_Type rxMode
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Phydm_CalNHMcnt(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_SearchPwdBLowerBound(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_adaptivityInfoInit(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PHYDM_ADAPINFO_E CmnInfo,
|
||||
IN u4Byte Value
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_AdaptivityInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_Adaptivity(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte IGI
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_setEDCCAThresholdAPI(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte IGI
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
Phydm_DisableEDCCA(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_DynamicEDCCA(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Phydm_AdaptivityBSOD(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
VOID
|
||||
phydm_pauseEDCCA_WorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_resumeEDCCA_WorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,374 @@
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8197F_SUPPORT == 1)||(RTL8822B_SUPPORT == 1))
|
||||
#include "rtl8197f/Hal8197FPhyReg.h"
|
||||
#include "WlanHAL/HalMac88XX/halmac_reg2.h"
|
||||
#else
|
||||
#include "WlanHAL/HalHeader/HalComReg.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (PHYDM_LA_MODE_SUPPORT == 1)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
BOOLEAN
|
||||
ADCSmp_BufferAllocate(
|
||||
IN PADAPTER Adapter,
|
||||
IN PRT_ADCSMP AdcSmp
|
||||
)
|
||||
{
|
||||
PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf);
|
||||
|
||||
if (ADCSmpBuf->Length == 0) {
|
||||
if (PlatformAllocateMemoryWithZero(Adapter, (void **)&(ADCSmpBuf->Octet), ADCSmpBuf->buffer_size) == RT_STATUS_SUCCESS)
|
||||
ADCSmpBuf->Length = ADCSmpBuf->buffer_size;
|
||||
else
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
#endif
|
||||
|
||||
VOID
|
||||
ADCSmp_GetTxPktBuf(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PRT_ADCSMP_STRING ADCSmpBuf
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u4Byte i = 0, value32, DataL = 0, DataH = 0;
|
||||
u4Byte Addr, Finish_Addr;
|
||||
u4Byte End_Addr = (ADCSmpBuf->start_pos + ADCSmpBuf->buffer_size)-1; /*End_Addr = 0x3ffff;*/
|
||||
BOOLEAN bRoundUp;
|
||||
static u4Byte page = 0xFF;
|
||||
u4Byte while_cnt = 0;
|
||||
|
||||
ODM_Memory_Set(pDM_Odm, ADCSmpBuf->Octet, 0, ADCSmpBuf->Length);
|
||||
ODM_Write1Byte(pDM_Odm, 0x0106, 0x69);
|
||||
|
||||
DbgPrint("%s\n", __func__);
|
||||
|
||||
value32 = ODM_Read4Byte(pDM_Odm, 0x7c0);
|
||||
bRoundUp = (BOOLEAN)((value32 & BIT31) >> 31);
|
||||
Finish_Addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
|
||||
|
||||
if (bRoundUp)
|
||||
Addr = (Finish_Addr+1)<<3;
|
||||
else
|
||||
Addr = ADCSmpBuf->start_pos;
|
||||
|
||||
DbgPrint("bRoundUp = %d, Finish_Addr=0x%x, value32=0x%x\n", bRoundUp, Finish_Addr, value32);
|
||||
DbgPrint("End_Addr = %x, ADCSmpBuf->start_pos = 0x%x, ADCSmpBuf->buffer_size = 0x%x\n", End_Addr, ADCSmpBuf->start_pos, ADCSmpBuf->buffer_size);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_stop(pDM_Odm->priv);
|
||||
#endif
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8197F) {
|
||||
for (Addr = 0x0, i = 0; Addr < End_Addr; Addr += 8, i += 2) { /*64K byte*/
|
||||
if ((Addr&0xfff) == 0)
|
||||
ODM_SetBBReg(pDM_Odm, 0x0140, bMaskLWord, 0x780+(Addr >> 12));
|
||||
DataL = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff), bMaskDWord);
|
||||
DataH = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff)+4, bMaskDWord);
|
||||
|
||||
DbgPrint("%08x%08x\n", DataH, DataL);
|
||||
}
|
||||
} else {
|
||||
while (Addr != (Finish_Addr<<3)) {
|
||||
if (page != (Addr >> 12)) {
|
||||
/*Reg140=0x780+(Addr>>12), Addr=0x30~0x3F, total 16 pages*/
|
||||
page = (Addr >> 12);
|
||||
}
|
||||
ODM_SetBBReg(pDM_Odm, 0x0140, bMaskLWord, 0x780+page);
|
||||
|
||||
/*pDataL = 0x8000+(Addr&0xfff);*/
|
||||
DataL = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff), bMaskDWord);
|
||||
DataH = ODM_GetBBReg(pDM_Odm, 0x8000+(Addr&0xfff)+4, bMaskDWord);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
ADCSmpBuf->Octet[i] = DataH;
|
||||
ADCSmpBuf->Octet[i+1] = DataL;
|
||||
#endif
|
||||
DbgPrint("%08x%08x\n", DataH, DataL);
|
||||
i = i + 2;
|
||||
|
||||
if ((Addr+8) >= End_Addr)
|
||||
Addr = ADCSmpBuf->start_pos;
|
||||
else
|
||||
Addr = Addr + 8;
|
||||
|
||||
while_cnt = while_cnt + 1;
|
||||
if (while_cnt > ((ADCSmpBuf->buffer_size)>>3))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_resume(pDM_Odm->priv);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ADCSmp_Start(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PRT_ADCSMP AdcSmp
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte tmpU1b;
|
||||
PRT_ADCSMP_STRING Buffer = &(AdcSmp->ADCSmpBuf);
|
||||
RT_ADCSMP_TRIG_SIG_SEL TrigSigSel = AdcSmp->ADCSmpTrigSigSel;
|
||||
u1Byte backup_DMA, while_cnt = 0;
|
||||
|
||||
DbgPrint("%s\n", __func__);
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8197F)
|
||||
ODM_SetBBReg(pDM_Odm, 0x9a0, 0xf00, AdcSmp->ADCSmpDmaDataSigSel); /*0x9A0[11:8]*/
|
||||
else
|
||||
ODM_SetBBReg(pDM_Odm , ODM_ADC_TRIGGER_Jaguar2, 0xf00, AdcSmp->ADCSmpDmaDataSigSel); /*0x95C[11:8]*/
|
||||
|
||||
ODM_Write1Byte(pDM_Odm, 0x7c0+1, AdcSmp->ADCSmpTriggerTime);
|
||||
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8197F)
|
||||
ODM_SetBBReg(pDM_Odm, 0xd00, BIT26, 0x1);
|
||||
else { /*for 8814A and 8822B?*/
|
||||
ODM_Write1Byte(pDM_Odm, 0x198c, 0x7);
|
||||
ODM_Write1Byte(pDM_Odm, 0x8b4, 0x80);
|
||||
}
|
||||
|
||||
if (AdcSmp->ADCSmpTrigSel == ADCSMP_MAC_TRIG) { /* trigger by MAC*/
|
||||
if (TrigSigSel == ADCSMP_TRIG_REG) { /* manual trigger 0x7C0[5] = 0 -> 1*/
|
||||
ODM_Write1Byte(pDM_Odm, 0x7c0, 0xCB); /*0x7C0[7:0]=8'b1100_1011*/
|
||||
ODM_Write1Byte(pDM_Odm, 0x7c0, 0xEB); /*0x7C0[7:0]=8'b1110_1011*/
|
||||
} else if (TrigSigSel == ADCSMP_TRIG_CCA)
|
||||
ODM_Write1Byte(pDM_Odm, 0x7c0, 0x8B); /*0x7C0[7:0]=8'b1000_1011*/
|
||||
else if (TrigSigSel == ADCSMP_TRIG_CRCFAIL)
|
||||
ODM_Write1Byte(pDM_Odm, 0x7c0, 0x4B); /*0x7C0[7:0]=8'b0100_1011*/
|
||||
else if (TrigSigSel == ADCSMP_TRIG_CRCOK)
|
||||
ODM_Write1Byte(pDM_Odm, 0x7c0, 0x0B); /*0x7C0[7:0]=8'b0000_1011*/
|
||||
} else { /*trigger by BB*/
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8197F)
|
||||
ODM_SetBBReg(pDM_Odm, 0x9a0, 0x1f, TrigSigSel); /*0x9A0[4:0]*/
|
||||
else
|
||||
ODM_SetBBReg(pDM_Odm , ODM_ADC_TRIGGER_Jaguar2, 0x1f, TrigSigSel); /*0x95C[4:0], 0x1F: trigger by CCA*/
|
||||
ODM_Write1Byte(pDM_Odm, 0x7c0, 0x03); /*0x7C0[7:0]=8'b0000_0011*/
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_stop(pDM_Odm->priv);
|
||||
#endif
|
||||
|
||||
/*Polling time always use 100ms, when it exceed 2s, break while loop*/
|
||||
do {
|
||||
tmpU1b = ODM_Read1Byte(pDM_Odm, 0x7c0);
|
||||
|
||||
if (AdcSmp->ADCSmpState != ADCSMP_STATE_SET) {
|
||||
DbgPrint("ADCSmpState != ADCSMP_STATE_SET\n");
|
||||
break;
|
||||
|
||||
} else if (tmpU1b & BIT1) {
|
||||
ODM_delay_ms(100);
|
||||
while_cnt = while_cnt + 1;
|
||||
continue;
|
||||
} else {
|
||||
DbgPrint("%s Query OK\n", __func__);
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8197F)
|
||||
ODM_SetBBReg(pDM_Odm, 0x7c0, BIT0, 0x0);
|
||||
break;
|
||||
}
|
||||
} while (while_cnt < 20);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_resume(pDM_Odm->priv);
|
||||
#if (RTL8197F_SUPPORT == 1)
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8197F) {
|
||||
/*Stop DMA*/
|
||||
backup_DMA = ODM_GetMACReg(pDM_Odm, 0x300, bMaskLWord);
|
||||
ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA|0x7fff);
|
||||
|
||||
/*move LA mode content from IMEM to TxPktBuffer
|
||||
Src : OCPBASE_IMEM 0x00000000
|
||||
Dest : OCPBASE_TXBUF 0x18780000
|
||||
Len : 64K*/
|
||||
GET_HAL_INTERFACE(pDM_Odm->priv)->InitDDMAHandler(pDM_Odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET)
|
||||
ADCSmp_GetTxPktBuf(pDM_Odm, Buffer);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8197F)
|
||||
ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA); /*Resume DMA*/
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET)
|
||||
AdcSmp->ADCSmpState = ADCSMP_STATE_QUERY;
|
||||
#endif
|
||||
|
||||
DbgPrint("%s Status %d\n", __func__, AdcSmp->ADCSmpState);
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
VOID
|
||||
ADCSmpWorkItemCallback(
|
||||
IN PVOID pContext
|
||||
)
|
||||
{
|
||||
PADAPTER Adapter = (PADAPTER)pContext;
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp);
|
||||
|
||||
ADCSmp_Start(pDM_Odm, AdcSmp);
|
||||
ADCSmp_Stop(pDM_Odm);
|
||||
}
|
||||
#endif
|
||||
|
||||
VOID
|
||||
ADCSmp_Set(
|
||||
IN PVOID pDM_VOID,
|
||||
IN RT_ADCSMP_TRIG_SEL TrigSel,
|
||||
IN RT_ADCSMP_TRIG_SIG_SEL TrigSigSel,
|
||||
IN u1Byte DmaDataSigSel,
|
||||
IN u1Byte TriggerTime,
|
||||
IN u2Byte PollingTime
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
BOOLEAN retValue = TRUE;
|
||||
PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp);
|
||||
|
||||
AdcSmp->ADCSmpTrigSel = TrigSel;
|
||||
AdcSmp->ADCSmpTrigSigSel = TrigSigSel;
|
||||
AdcSmp->ADCSmpDmaDataSigSel = DmaDataSigSel;
|
||||
AdcSmp->ADCSmpTriggerTime = TriggerTime;
|
||||
AdcSmp->ADCSmpPollingTime = PollingTime;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (AdcSmp->ADCSmpState != ADCSMP_STATE_IDLE)
|
||||
retValue = FALSE;
|
||||
else if (AdcSmp->ADCSmpBuf.Length == 0)
|
||||
retValue = ADCSmp_BufferAllocate(pDM_Odm->Adapter, AdcSmp);
|
||||
#endif
|
||||
|
||||
if (retValue) {
|
||||
AdcSmp->ADCSmpState = ADCSMP_STATE_SET;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
ODM_ScheduleWorkItem(&(AdcSmp->ADCSmpWorkItem));
|
||||
#else
|
||||
ADCSmp_Start(pDM_Odm, AdcSmp);
|
||||
#endif
|
||||
}
|
||||
|
||||
DbgPrint("ADCSmpState %d Return Status %d\n", AdcSmp->ADCSmpState, retValue);
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_STATUS
|
||||
ADCSmp_Query(
|
||||
IN PVOID pDM_VOID,
|
||||
IN ULONG InformationBufferLength,
|
||||
OUT PVOID InformationBuffer,
|
||||
OUT PULONG BytesWritten
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp);
|
||||
RT_STATUS retStatus = RT_STATUS_SUCCESS;
|
||||
PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf);
|
||||
|
||||
DbgPrint("%s ADCSmpState %d", __func__, AdcSmp->ADCSmpState);
|
||||
|
||||
if (InformationBufferLength != ADCSmpBuf->buffer_size) {
|
||||
*BytesWritten = 0;
|
||||
retStatus = RT_STATUS_RESOURCE;
|
||||
} else if (ADCSmpBuf->Length != ADCSmpBuf->buffer_size) {
|
||||
*BytesWritten = 0;
|
||||
retStatus = RT_STATUS_RESOURCE;
|
||||
} else if (AdcSmp->ADCSmpState != ADCSMP_STATE_QUERY) {
|
||||
*BytesWritten = 0;
|
||||
retStatus = RT_STATUS_PENDING;
|
||||
} else {
|
||||
ODM_MoveMemory(pDM_Odm, InformationBuffer, ADCSmpBuf->Octet, ADCSmpBuf->buffer_size);
|
||||
*BytesWritten = ADCSmpBuf->buffer_size;
|
||||
|
||||
AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE;
|
||||
}
|
||||
|
||||
DbgPrint("Return Status %d\n", retStatus);
|
||||
|
||||
return retStatus;
|
||||
}
|
||||
#endif
|
||||
|
||||
VOID
|
||||
ADCSmp_Stop(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp);
|
||||
|
||||
AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE;
|
||||
|
||||
DbgPrint("%s status %d\n", __func__, AdcSmp->ADCSmpState);
|
||||
}
|
||||
|
||||
VOID
|
||||
ADCSmp_Init(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp);
|
||||
PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf);
|
||||
|
||||
AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A) {
|
||||
ADCSmpBuf->start_pos = 0x30000;
|
||||
ADCSmpBuf->buffer_size = 0x10000;
|
||||
} else if (pDM_Odm->SupportICType & ODM_RTL8822B) {
|
||||
ADCSmpBuf->start_pos = 0x20000;
|
||||
ADCSmpBuf->buffer_size = 0x20000;
|
||||
} else if (pDM_Odm->SupportICType & ODM_RTL8197F) {
|
||||
ADCSmpBuf->start_pos = 0x00000;
|
||||
ADCSmpBuf->buffer_size = 0x10000;
|
||||
} else if (pDM_Odm->SupportICType & ODM_RTL8821C) {
|
||||
ADCSmpBuf->start_pos = 0x8000;
|
||||
ADCSmpBuf->buffer_size = 0x8000;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
VOID
|
||||
ADCSmp_DeInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp);
|
||||
PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf);
|
||||
|
||||
ADCSmp_Stop(pDM_Odm);
|
||||
|
||||
if (ADCSmpBuf->Length != 0x0) {
|
||||
ODM_FreeMemory(pDM_Odm, ADCSmpBuf->Octet, ADCSmpBuf->Length);
|
||||
ADCSmpBuf->Length = 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
#ifndef __INC_ADCSMP_H
|
||||
#define __INC_ADCSMP_H
|
||||
|
||||
typedef struct _RT_ADCSMP_STRING {
|
||||
pu4Byte Octet;
|
||||
u4Byte Length;
|
||||
u4Byte buffer_size;
|
||||
u4Byte start_pos;
|
||||
} RT_ADCSMP_STRING, *PRT_ADCSMP_STRING;
|
||||
|
||||
|
||||
typedef enum _RT_ADCSMP_TRIG_SEL {
|
||||
ADCSMP_BB_TRIG,
|
||||
ADCSMP_MAC_TRIG,
|
||||
} RT_ADCSMP_TRIG_SEL, *PRT_ADCSMP_TRIG_SEL;
|
||||
|
||||
|
||||
typedef enum _RT_ADCSMP_TRIG_SIG_SEL {
|
||||
ADCSMP_TRIG_CRCOK,
|
||||
ADCSMP_TRIG_CRCFAIL,
|
||||
ADCSMP_TRIG_CCA,
|
||||
ADCSMP_TRIG_REG,
|
||||
} RT_ADCSMP_TRIG_SIG_SEL, *PRT_ADCSMP_TRIG_SIG_SEL;
|
||||
|
||||
|
||||
typedef enum _RT_ADCSMP_STATE {
|
||||
ADCSMP_STATE_IDLE,
|
||||
ADCSMP_STATE_SET,
|
||||
ADCSMP_STATE_QUERY,
|
||||
} RT_ADCSMP_STATE, *PRT_ADCSMP_STATE;
|
||||
|
||||
|
||||
typedef struct _RT_ADCSMP {
|
||||
RT_ADCSMP_STRING ADCSmpBuf;
|
||||
RT_ADCSMP_STATE ADCSmpState;
|
||||
RT_ADCSMP_TRIG_SEL ADCSmpTrigSel;
|
||||
RT_ADCSMP_TRIG_SIG_SEL ADCSmpTrigSigSel;
|
||||
u1Byte ADCSmpDmaDataSigSel;
|
||||
u1Byte ADCSmpTriggerTime;
|
||||
u2Byte ADCSmpPollingTime;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_WORK_ITEM ADCSmpWorkItem;
|
||||
#endif
|
||||
} RT_ADCSMP, *PRT_ADCSMP;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
VOID
|
||||
ADCSmpWorkItemCallback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
#endif
|
||||
|
||||
VOID
|
||||
ADCSmp_Set(
|
||||
IN PVOID pDM_VOID,
|
||||
IN RT_ADCSMP_TRIG_SEL TrigSel,
|
||||
IN RT_ADCSMP_TRIG_SIG_SEL TrigSigSel,
|
||||
IN u1Byte DmaDataSigSel,
|
||||
IN u1Byte TriggerTime,
|
||||
IN u2Byte PollingTime
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_STATUS
|
||||
ADCSmp_Query(
|
||||
IN PVOID pDM_VOID,
|
||||
IN ULONG InformationBufferLength,
|
||||
OUT PVOID InformationBuffer,
|
||||
OUT PULONG BytesWritten
|
||||
);
|
||||
#endif
|
||||
VOID
|
||||
ADCSmp_Stop(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ADCSmp_Init(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
VOID
|
||||
ADCSmp_DeInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,964 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
|
||||
#if(defined(CONFIG_ANT_DETECTION))
|
||||
|
||||
//IS_ANT_DETECT_SUPPORT_SINGLE_TONE(Adapter)
|
||||
//IS_ANT_DETECT_SUPPORT_RSSI(Adapter)
|
||||
//IS_ANT_DETECT_SUPPORT_PSD(Adapter)
|
||||
|
||||
//1 [1. Single Tone Method] ===================================================
|
||||
|
||||
//
|
||||
// Description:
|
||||
// Set Single/Dual Antenna default setting for products that do not do detection in advance.
|
||||
//
|
||||
// Added by Joseph, 2012.03.22
|
||||
//
|
||||
VOID
|
||||
ODM_SingleDualAntennaDefaultSetting(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
|
||||
PADAPTER pAdapter = pDM_Odm->Adapter;
|
||||
|
||||
u1Byte btAntNum=BT_GetPgAntNum(pAdapter);
|
||||
// Set default antenna A and B status
|
||||
if(btAntNum == 2)
|
||||
{
|
||||
pDM_SWAT_Table->ANTA_ON=TRUE;
|
||||
pDM_SWAT_Table->ANTB_ON=TRUE;
|
||||
|
||||
}
|
||||
else if(btAntNum == 1)
|
||||
{// Set antenna A as default
|
||||
pDM_SWAT_Table->ANTA_ON=TRUE;
|
||||
pDM_SWAT_Table->ANTB_ON=FALSE;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
RT_ASSERT(FALSE, ("Incorrect antenna number!!\n"));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//2 8723A ANT DETECT
|
||||
//
|
||||
// Description:
|
||||
// Implement IQK single tone for RF DPK loopback and BB PSD scanning.
|
||||
// This function is cooperated with BB team Neil.
|
||||
//
|
||||
// Added by Roger, 2011.12.15
|
||||
//
|
||||
BOOLEAN
|
||||
ODM_SingleDualAntennaDetection(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte mode
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PADAPTER pAdapter = pDM_Odm->Adapter;
|
||||
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
|
||||
u4Byte CurrentChannel,RfLoopReg;
|
||||
u1Byte n;
|
||||
u4Byte Reg88c, Regc08, Reg874, Regc50, Reg948, Regb2c, Reg92c, Reg930, Reg064, AFE_rRx_Wait_CCA;
|
||||
u1Byte initial_gain = 0x5a;
|
||||
u4Byte PSD_report_tmp;
|
||||
u4Byte AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
|
||||
BOOLEAN bResult = TRUE;
|
||||
u4Byte AFE_Backup[16];
|
||||
u4Byte AFE_REG_8723A[16] = {
|
||||
rRx_Wait_CCA, rTx_CCK_RFON,
|
||||
rTx_CCK_BBON, rTx_OFDM_RFON,
|
||||
rTx_OFDM_BBON, rTx_To_Rx,
|
||||
rTx_To_Tx, rRx_CCK,
|
||||
rRx_OFDM, rRx_Wait_RIFS,
|
||||
rRx_TO_Rx, rStandby,
|
||||
rSleep, rPMPD_ANAEN,
|
||||
rFPGA0_XCD_SwitchControl, rBlue_Tooth};
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============>\n"));
|
||||
|
||||
|
||||
if (!(pDM_Odm->SupportICType & ODM_RTL8723B))
|
||||
return bResult;
|
||||
|
||||
// Retrieve antenna detection registry info, added by Roger, 2012.11.27.
|
||||
if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter))
|
||||
return bResult;
|
||||
|
||||
//1 Backup Current RF/BB Settings
|
||||
|
||||
CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
|
||||
RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask);
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
|
||||
Reg92c = ODM_GetBBReg(pDM_Odm, rDPDT_control, bMaskDWord);
|
||||
Reg930 = ODM_GetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord);
|
||||
Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
|
||||
Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord);
|
||||
Reg064 = ODM_GetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29);
|
||||
ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1);
|
||||
ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77);
|
||||
ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, 0x1); //dbg 7
|
||||
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3c0, 0x0);//dbg 8
|
||||
ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x0);
|
||||
}
|
||||
|
||||
ODM_StallExecution(10);
|
||||
|
||||
//Store A Path Register 88c, c08, 874, c50
|
||||
Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
|
||||
Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
|
||||
Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
|
||||
Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
|
||||
|
||||
// Store AFE Registers
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8723B)
|
||||
AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord);
|
||||
|
||||
//Set PSD 128 pts
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts
|
||||
|
||||
// To SET CH1 to do
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401); //Channel 1
|
||||
|
||||
// AFE all on step
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8723B)
|
||||
ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016);
|
||||
|
||||
// 3 wire Disable
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
|
||||
|
||||
//BB IQK Setting
|
||||
ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
|
||||
|
||||
//IQK setting tone@ 4.34Mhz
|
||||
ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
|
||||
ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
|
||||
|
||||
//Page B init
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
|
||||
ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
|
||||
ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
|
||||
ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150016);
|
||||
ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150016);
|
||||
}
|
||||
ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
|
||||
ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7f, initial_gain);
|
||||
|
||||
//IQK Single tone start
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000);
|
||||
ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
|
||||
ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
|
||||
|
||||
ODM_StallExecution(10000);
|
||||
|
||||
// PSD report of antenna A
|
||||
PSD_report_tmp=0x0;
|
||||
for (n=0;n<2;n++)
|
||||
{
|
||||
PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
|
||||
if(PSD_report_tmp >AntA_report)
|
||||
AntA_report=PSD_report_tmp;
|
||||
}
|
||||
|
||||
// change to Antenna B
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
|
||||
//ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2);
|
||||
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280);
|
||||
ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1);
|
||||
}
|
||||
|
||||
ODM_StallExecution(10);
|
||||
|
||||
// PSD report of antenna B
|
||||
PSD_report_tmp=0x0;
|
||||
for (n=0;n<2;n++)
|
||||
{
|
||||
PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
|
||||
if(PSD_report_tmp > AntB_report)
|
||||
AntB_report=PSD_report_tmp;
|
||||
}
|
||||
|
||||
//Close IQK Single Tone function
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
|
||||
|
||||
//1 Return to antanna A
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
|
||||
// external DPDT
|
||||
ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c);
|
||||
|
||||
//internal S0/S1
|
||||
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
|
||||
ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c);
|
||||
ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord, Reg930);
|
||||
ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, Reg064);
|
||||
}
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
|
||||
ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
|
||||
ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
|
||||
ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel);
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg);
|
||||
|
||||
//Reload AFE Registers
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8723B)
|
||||
ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA);
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report));
|
||||
|
||||
//2 Test Ant B based on Ant A is ON
|
||||
if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 135) && (AntB_report <= 135))
|
||||
{
|
||||
u1Byte TH1=2, TH2=6;
|
||||
|
||||
if((AntA_report - AntB_report < TH1) || (AntB_report - AntA_report < TH1))
|
||||
{
|
||||
pDM_SWAT_Table->ANTA_ON=TRUE;
|
||||
pDM_SWAT_Table->ANTB_ON=TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
|
||||
}
|
||||
else if(((AntA_report - AntB_report >= TH1) && (AntA_report - AntB_report <= TH2)) ||
|
||||
((AntB_report - AntA_report >= TH1) && (AntB_report - AntA_report <= TH2)))
|
||||
{
|
||||
pDM_SWAT_Table->ANTA_ON=FALSE;
|
||||
pDM_SWAT_Table->ANTB_ON=FALSE;
|
||||
bResult = FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_SWAT_Table->ANTA_ON = TRUE;
|
||||
pDM_SWAT_Table->ANTB_ON=FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna\n"));
|
||||
}
|
||||
pDM_Odm->AntDetectedInfo.bAntDetected= TRUE;
|
||||
pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report;
|
||||
pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report;
|
||||
pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n"));
|
||||
bResult = FALSE;
|
||||
}
|
||||
}
|
||||
return bResult;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
//1 [2. Scan AP RSSI Method] ==================================================
|
||||
|
||||
|
||||
|
||||
|
||||
BOOLEAN
|
||||
ODM_SwAntDivCheckBeforeLink(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
|
||||
#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
|
||||
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
|
||||
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
|
||||
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
|
||||
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
|
||||
s1Byte Score = 0;
|
||||
PRT_WLAN_BSS pTmpBssDesc, pTestBssDesc;
|
||||
u1Byte power_target_L = 9, power_target_H = 16;
|
||||
u1Byte tmp_power_diff = 0,power_diff = 0,avg_power_diff = 0,max_power_diff = 0,min_power_diff = 0xff;
|
||||
u2Byte index, counter = 0;
|
||||
static u1Byte ScanChannel;
|
||||
u4Byte tmp_SWAS_NoLink_BK_Reg948;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", pDM_Odm->DM_SWAT_Table.ANTA_ON, pDM_Odm->DM_SWAT_Table.ANTB_ON));
|
||||
|
||||
//if(HP id)
|
||||
{
|
||||
if(pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult==TRUE && pDM_Odm->SupportICType == ODM_RTL8723B)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n"));
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if(pDM_Odm->SupportICType == ODM_RTL8723B)
|
||||
{
|
||||
if(pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 == 0xff)
|
||||
pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch );
|
||||
}
|
||||
}
|
||||
|
||||
if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413
|
||||
{ // The ODM structure is not initialized.
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
// Retrieve antenna detection registry info, added by Roger, 2012.11.27.
|
||||
if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter))
|
||||
{
|
||||
return FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI Method\n"));
|
||||
}
|
||||
|
||||
// Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
|
||||
PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
|
||||
if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
|
||||
{
|
||||
PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
|
||||
pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState));
|
||||
|
||||
pDM_SWAT_Table->SWAS_NoLink_State = 0;
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State));
|
||||
//1 Run AntDiv mechanism "Before Link" part.
|
||||
if(pDM_SWAT_Table->SWAS_NoLink_State == 0)
|
||||
{
|
||||
//1 Prepare to do Scan again to check current antenna state.
|
||||
|
||||
// Set check state to next step.
|
||||
pDM_SWAT_Table->SWAS_NoLink_State = 1;
|
||||
|
||||
// Copy Current Scan list.
|
||||
pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc;
|
||||
PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
|
||||
|
||||
// Go back to scan function again.
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n"));
|
||||
pMgntInfo->ScanStep=0;
|
||||
pMgntInfo->bScanAntDetect = TRUE;
|
||||
ScanChannel = odm_SwAntDivSelectScanChnl(Adapter);
|
||||
|
||||
|
||||
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
|
||||
{
|
||||
if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
|
||||
ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
|
||||
else
|
||||
ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
|
||||
if(ScanChannel == 0)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
|
||||
|
||||
if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
|
||||
{
|
||||
pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
|
||||
}
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")));
|
||||
} else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) {
|
||||
/*Switch Antenna to another one.*/
|
||||
|
||||
tmp_SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch);
|
||||
|
||||
if ((pDM_SWAT_Table->CurAntenna == MAIN_ANT) && (tmp_SWAS_NoLink_BK_Reg948 == 0x200)) {
|
||||
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280);
|
||||
ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1);
|
||||
pDM_SWAT_Table->CurAntenna = AUX_ANT;
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_SWAS_NoLink_BK_Reg948));
|
||||
return FALSE;
|
||||
}
|
||||
ODM_StallExecution(10);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Change to (( %s-ant)) for testing.\n", (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?"MAIN":"AUX"));
|
||||
}
|
||||
|
||||
odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
|
||||
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
else //pDM_SWAT_Table->SWAS_NoLink_State == 1
|
||||
{
|
||||
//1 ScanComple() is called after antenna swiched.
|
||||
//1 Check scan result and determine which antenna is going
|
||||
//1 to be used.
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" tmpNumBssDesc= (( %d )) \n",pMgntInfo->tmpNumBssDesc));// debug for Dino
|
||||
|
||||
for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++)
|
||||
{
|
||||
pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1
|
||||
pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2
|
||||
|
||||
if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n"));
|
||||
continue;
|
||||
}
|
||||
|
||||
if(pDM_Odm->SupportICType != ODM_RTL8723B)
|
||||
{
|
||||
if(pTmpBssDesc->ChannelNumber == ScanChannel)
|
||||
{
|
||||
if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n"));
|
||||
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
|
||||
|
||||
Score++;
|
||||
PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
|
||||
}
|
||||
else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n"));
|
||||
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
|
||||
Score--;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000)
|
||||
{
|
||||
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else // 8723B
|
||||
{
|
||||
if(pTmpBssDesc->ChannelNumber == ScanChannel)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ChannelNumber == ScanChannel -> (( %d )) \n", pTmpBssDesc->ChannelNumber ));
|
||||
|
||||
if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) // Pow(Ant1) > Pow(Ant2)
|
||||
{
|
||||
counter++;
|
||||
tmp_power_diff=(u1Byte)(pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower);
|
||||
power_diff = power_diff + tmp_power_diff;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
|
||||
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
|
||||
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
|
||||
|
||||
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d)) \n", tmp_power_diff,max_power_diff,min_power_diff));
|
||||
if(tmp_power_diff > max_power_diff)
|
||||
max_power_diff=tmp_power_diff;
|
||||
if(tmp_power_diff < min_power_diff)
|
||||
min_power_diff=tmp_power_diff;
|
||||
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d)) \n",max_power_diff,min_power_diff));
|
||||
|
||||
PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
|
||||
}
|
||||
else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower) // Pow(Ant1) < Pow(Ant2)
|
||||
{
|
||||
counter++;
|
||||
tmp_power_diff=(u1Byte)(pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower);
|
||||
power_diff = power_diff + tmp_power_diff;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
|
||||
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
|
||||
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
|
||||
if(tmp_power_diff > max_power_diff)
|
||||
max_power_diff=tmp_power_diff;
|
||||
if(tmp_power_diff < min_power_diff)
|
||||
min_power_diff=tmp_power_diff;
|
||||
}
|
||||
else // Pow(Ant1) = Pow(Ant2)
|
||||
{
|
||||
if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp) // Stamp(Ant1) < Stamp(Ant2)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
|
||||
if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000)
|
||||
{
|
||||
counter++;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
|
||||
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
|
||||
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
|
||||
min_power_diff = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
|
||||
{
|
||||
if(pMgntInfo->NumBssDesc!=0 && Score<0)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
|
||||
|
||||
if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
|
||||
ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
|
||||
else
|
||||
ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
|
||||
}
|
||||
|
||||
if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
|
||||
{
|
||||
pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
|
||||
}
|
||||
}
|
||||
else if(pDM_Odm->SupportICType == ODM_RTL8723B)
|
||||
{
|
||||
if(counter == 0)
|
||||
{
|
||||
if(pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec == FALSE)
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = TRUE;
|
||||
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again \n"));
|
||||
|
||||
//3 [ Scan again ]
|
||||
odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
|
||||
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
|
||||
return TRUE;
|
||||
}
|
||||
else// Pre_Aux_FailDetec == TRUE
|
||||
{
|
||||
//2 [ Single Antenna ]
|
||||
pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE;
|
||||
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Still cannot find any AP ]] \n"));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
|
||||
}
|
||||
pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE;
|
||||
|
||||
if(counter==3)
|
||||
{
|
||||
avg_power_diff = ((power_diff-max_power_diff - min_power_diff)>>1)+ ((max_power_diff + min_power_diff)>>2);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff));
|
||||
}
|
||||
else if(counter>=4)
|
||||
{
|
||||
avg_power_diff=(power_diff-max_power_diff - min_power_diff) / (counter - 2);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff));
|
||||
|
||||
}
|
||||
else//counter==1,2
|
||||
{
|
||||
avg_power_diff=power_diff/counter;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d )) \n", avg_power_diff,counter, power_diff));
|
||||
}
|
||||
|
||||
//2 [ Retry ]
|
||||
if( (avg_power_diff >=power_target_L) && (avg_power_diff <=power_target_H) )
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.Retry_Counter++;
|
||||
|
||||
if(pDM_Odm->DM_SWAT_Table.Retry_Counter<=3)
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]] \n", avg_power_diff));
|
||||
|
||||
//3 [ Scan again ]
|
||||
odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
|
||||
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
|
||||
return TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( Retry_Counter > 3 )) \n"));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
|
||||
}
|
||||
|
||||
}
|
||||
//2 [ Dual Antenna ]
|
||||
else if( (pMgntInfo->NumBssDesc != 0) && (avg_power_diff < power_target_L) )
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
|
||||
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
|
||||
pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
|
||||
pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter++;
|
||||
|
||||
// set bt coexDM from 1ant coexDM to 2ant coexDM
|
||||
BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
|
||||
|
||||
//3 [ Init antenna diversity ]
|
||||
pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
|
||||
ODM_AntDivInit(pDM_Odm);
|
||||
}
|
||||
//2 [ Single Antenna ]
|
||||
else if(avg_power_diff > power_target_H)
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
|
||||
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
|
||||
pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
|
||||
//BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1);
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
|
||||
pDM_Odm->DM_SWAT_Table.Single_Ant_Counter++;
|
||||
}
|
||||
}
|
||||
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bResult=(( %d ))\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Dual_Ant_Counter = (( %d )), Single_Ant_Counter = (( %d )) , Retry_Counter = (( %d )) , Aux_FailDetec_Counter = (( %d ))\n\n\n",
|
||||
pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter,pDM_Odm->DM_SWAT_Table.Single_Ant_Counter,pDM_Odm->DM_SWAT_Table.Retry_Counter,pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter));
|
||||
|
||||
//2 recover the antenna setting
|
||||
|
||||
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
|
||||
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, (pDM_SWAT_Table->SWAS_NoLink_BK_Reg948));
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bResult=(( %d )), Recover Reg[948]= (( %x )) \n\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult, pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 ));
|
||||
|
||||
|
||||
}
|
||||
|
||||
// Check state reset to default and wait for next time.
|
||||
pDM_SWAT_Table->SWAS_NoLink_State = 0;
|
||||
pMgntInfo->bScanAntDetect = FALSE;
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
#else
|
||||
return FALSE;
|
||||
#endif
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//1 [3. PSD Method] ==========================================================
|
||||
|
||||
|
||||
|
||||
|
||||
u4Byte
|
||||
odm_GetPSDData(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u2Byte point,
|
||||
IN u1Byte initial_gain)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u4Byte psd_report;
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
|
||||
ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); //Start PSD calculation, Reg808[22]=0->1
|
||||
ODM_StallExecution(150);//Wait for HW PSD report
|
||||
ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);//Stop PSD calculation, Reg808[22]=1->0
|
||||
psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;//Read PSD report, Reg8B4[15:0]
|
||||
|
||||
psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report));//+(u4Byte)(initial_gain);
|
||||
return psd_report;
|
||||
}
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
ODM_SingleDualAntennaDetection_PSD(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u4Byte Channel_ori;
|
||||
u1Byte initial_gain = 0x36;
|
||||
u1Byte tone_idx;
|
||||
u1Byte Tone_lenth_1=7, Tone_lenth_2=4;
|
||||
u2Byte Tone_idx_1[7]={88, 104, 120, 8, 24, 40, 56};
|
||||
u2Byte Tone_idx_2[4]={8, 24, 40, 56};
|
||||
u4Byte PSD_report_Main[11]={0}, PSD_report_Aux[11]={0};
|
||||
//u1Byte Tone_lenth_1=4, Tone_lenth_2=2;
|
||||
//u2Byte Tone_idx_1[4]={88, 120, 24, 56};
|
||||
//u2Byte Tone_idx_2[2]={ 24, 56};
|
||||
//u4Byte PSD_report_Main[6]={0}, PSD_report_Aux[6]={0};
|
||||
|
||||
u4Byte PSD_report_temp,MAX_PSD_report_Main=0,MAX_PSD_report_Aux=0;
|
||||
u4Byte PSD_power_threshold;
|
||||
u4Byte Main_psd_result=0, Aux_psd_result=0;
|
||||
u4Byte Regc50, Reg948, Regb2c,Regc14,Reg908;
|
||||
u4Byte i=0,test_num=8;
|
||||
|
||||
|
||||
if(pDM_Odm->SupportICType != ODM_RTL8723B)
|
||||
return;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection_PSD()============> \n"));
|
||||
|
||||
//2 [ Backup Current RF/BB Settings ]
|
||||
|
||||
Channel_ori = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
|
||||
Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
|
||||
Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord);
|
||||
Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
|
||||
Regc14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord);
|
||||
Reg908 = ODM_GetBBReg(pDM_Odm, 0x908, bMaskDWord);
|
||||
|
||||
//2 [ Setting for doing PSD function (CH4)]
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); //disable whole CCK block
|
||||
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // Turn off TX -> Pause TX Queue
|
||||
ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); // [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA]
|
||||
|
||||
// PHYTXON while loop
|
||||
ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, 0x803);
|
||||
while (ODM_GetBBReg(pDM_Odm, 0xdf4, BIT6))
|
||||
{
|
||||
i++;
|
||||
if (i > 1000000)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain);
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH4 & 40M
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pt //Set PSD 128 ptss
|
||||
ODM_StallExecution(3000);
|
||||
|
||||
|
||||
//2 [ Doing PSD Function in (CH4)]
|
||||
|
||||
//Antenna A
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n"));
|
||||
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200);
|
||||
ODM_StallExecution(10);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n"));
|
||||
for (i=0;i<test_num;i++)
|
||||
{
|
||||
for (tone_idx=0;tone_idx<Tone_lenth_1;tone_idx++)
|
||||
{
|
||||
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_1[tone_idx], initial_gain);
|
||||
//if( PSD_report_temp>PSD_report_Main[tone_idx] )
|
||||
PSD_report_Main[tone_idx]+=PSD_report_temp;
|
||||
}
|
||||
}
|
||||
//Antenna B
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n"));
|
||||
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280);
|
||||
ODM_StallExecution(10);
|
||||
for (i=0;i<test_num;i++)
|
||||
{
|
||||
for (tone_idx=0;tone_idx<Tone_lenth_1;tone_idx++)
|
||||
{
|
||||
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_1[tone_idx], initial_gain);
|
||||
//if( PSD_report_temp>PSD_report_Aux[tone_idx] )
|
||||
PSD_report_Aux[tone_idx]+=PSD_report_temp;
|
||||
}
|
||||
}
|
||||
//2 [ Doing PSD Function in (CH8)]
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0
|
||||
ODM_StallExecution(3000);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain);
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH8 & 40M
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf
|
||||
ODM_StallExecution(3000);
|
||||
|
||||
//Antenna A
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n"));
|
||||
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200);
|
||||
ODM_StallExecution(10);
|
||||
|
||||
for (i=0;i<test_num;i++)
|
||||
{
|
||||
for (tone_idx=0;tone_idx<Tone_lenth_2;tone_idx++)
|
||||
{
|
||||
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_2[tone_idx], initial_gain);
|
||||
//if( PSD_report_temp>PSD_report_Main[tone_idx] )
|
||||
PSD_report_Main[Tone_lenth_1+tone_idx]+=PSD_report_temp;
|
||||
}
|
||||
}
|
||||
|
||||
//Antenna B
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n"));
|
||||
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280);
|
||||
ODM_StallExecution(10);
|
||||
|
||||
for (i=0;i<test_num;i++)
|
||||
{
|
||||
for (tone_idx=0;tone_idx<Tone_lenth_2;tone_idx++)
|
||||
{
|
||||
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_2[tone_idx], initial_gain);
|
||||
//if( PSD_report_temp>PSD_report_Aux[tone_idx] )
|
||||
PSD_report_Aux[Tone_lenth_1+tone_idx]+=PSD_report_temp;
|
||||
}
|
||||
}
|
||||
|
||||
//2 [ Calculate Result ]
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL) \n"));
|
||||
for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Main[tone_idx] ));
|
||||
Main_psd_result+= PSD_report_Main[tone_idx];
|
||||
if(PSD_report_Main[tone_idx]>MAX_PSD_report_Main)
|
||||
MAX_PSD_report_Main=PSD_report_Main[tone_idx];
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", Main_psd_result));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", MAX_PSD_report_Main));
|
||||
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL) \n"));
|
||||
for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Aux[tone_idx] ));
|
||||
Aux_psd_result+= PSD_report_Aux[tone_idx];
|
||||
if(PSD_report_Aux[tone_idx]>MAX_PSD_report_Aux)
|
||||
MAX_PSD_report_Aux=PSD_report_Aux[tone_idx];
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", Aux_psd_result));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", MAX_PSD_report_Aux));
|
||||
|
||||
//Main_psd_result=Main_psd_result-MAX_PSD_report_Main;
|
||||
//Aux_psd_result=Aux_psd_result-MAX_PSD_report_Aux;
|
||||
PSD_power_threshold=(Main_psd_result*7)>>3;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result , Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", Main_psd_result, Aux_psd_result,PSD_power_threshold));
|
||||
|
||||
//3 [ Dual Antenna ]
|
||||
if(Aux_psd_result >= PSD_power_threshold )
|
||||
{
|
||||
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
|
||||
pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
|
||||
|
||||
// set bt coexDM from 1ant coexDM to 2ant coexDM
|
||||
//BT_SetBtCoexAntNum(pAdapter, BT_COEX_ANT_TYPE_DETECTED, 2);
|
||||
|
||||
// Init antenna diversity
|
||||
pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
|
||||
ODM_AntDivInit(pDM_Odm);
|
||||
}
|
||||
//3 [ Single Antenna ]
|
||||
else
|
||||
{
|
||||
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
|
||||
{
|
||||
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
|
||||
pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
|
||||
}
|
||||
|
||||
//2 [ Recover all parameters ]
|
||||
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,Channel_ori);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0
|
||||
ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, Regc50);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
|
||||
ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); //enable whole CCK block
|
||||
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x0); //Turn on TX // Resume TX Queue
|
||||
ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, Regc14); // [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA]
|
||||
ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, Reg908);
|
||||
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
void
|
||||
odm_SwAntDetectInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
#if(defined(CONFIG_ANT_DETECTION))
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
|
||||
|
||||
//pDM_SWAT_Table->PreAntenna = MAIN_ANT;
|
||||
//pDM_SWAT_Table->CurAntenna = MAIN_ANT;
|
||||
pDM_SWAT_Table->SWAS_NoLink_State = 0;
|
||||
pDM_SWAT_Table->Pre_Aux_FailDetec = FALSE;
|
||||
pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = 0xff;
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMANTDECT_H__
|
||||
#define __PHYDMANTDECT_H__
|
||||
|
||||
#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/
|
||||
|
||||
#if(defined(CONFIG_ANT_DETECTION))
|
||||
//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
|
||||
//ANT Test
|
||||
#define ANTTESTALL 0x00 /*Ant A or B will be Testing*/
|
||||
#define ANTTESTA 0x01 /*Ant A will be Testing*/
|
||||
#define ANTTESTB 0x02 /*Ant B will be testing*/
|
||||
|
||||
#define MAX_ANTENNA_DETECTION_CNT 10
|
||||
|
||||
|
||||
typedef struct _ANT_DETECTED_INFO{
|
||||
BOOLEAN bAntDetected;
|
||||
u4Byte dBForAntA;
|
||||
u4Byte dBForAntB;
|
||||
u4Byte dBForAntO;
|
||||
}ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
|
||||
|
||||
|
||||
typedef enum tag_SW_Antenna_Switch_Definition
|
||||
{
|
||||
Antenna_A = 1,
|
||||
Antenna_B = 2,
|
||||
Antenna_MAX = 3,
|
||||
}DM_SWAS_E;
|
||||
|
||||
|
||||
|
||||
//1 [1. Single Tone Method] ===================================================
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
ODM_SingleDualAntennaDefaultSetting(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
ODM_SingleDualAntennaDetection(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte mode
|
||||
);
|
||||
|
||||
//1 [2. Scan AP RSSI Method] ==================================================
|
||||
|
||||
#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink
|
||||
|
||||
BOOLEAN
|
||||
ODM_SwAntDivCheckBeforeLink(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
//1 [3. PSD Method] ==========================================================
|
||||
|
||||
|
||||
VOID
|
||||
ODM_SingleDualAntennaDetection_PSD(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
VOID
|
||||
odm_SwAntDetectInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,634 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMANTDIV_H__
|
||||
#define __PHYDMANTDIV_H__
|
||||
|
||||
/*#define ANTDIV_VERSION "2.0" //2014.11.04*/
|
||||
/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
|
||||
/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/
|
||||
/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/
|
||||
/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/
|
||||
/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT,
|
||||
because antenna diversity only works when BT is disable or radio off*/
|
||||
/*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/
|
||||
/*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/
|
||||
/*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */
|
||||
/*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */
|
||||
/*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */
|
||||
#define ANTDIV_VERSION "3.9" /*2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */
|
||||
|
||||
//1 ============================================================
|
||||
//1 Definition
|
||||
//1 ============================================================
|
||||
|
||||
#define ANTDIV_INIT 0xff
|
||||
#define MAIN_ANT 1 /*Ant A or Ant Main or S1*/
|
||||
#define AUX_ANT 2 /*AntB or Ant Aux or S0*/
|
||||
#define MAX_ANT 3 /* 3 for AP using*/
|
||||
|
||||
#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
|
||||
#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
|
||||
/*smart antenna*/
|
||||
#define SUPPORT_RF_PATH_NUM 4
|
||||
#define SUPPORT_BEAM_PATTERN_NUM 4
|
||||
#define NUM_ANTENNA_8821A 2
|
||||
|
||||
#define NO_FIX_TX_ANT 0
|
||||
#define FIX_TX_AT_MAIN 1
|
||||
#define FIX_AUX_AT_MAIN 2
|
||||
|
||||
//Antenna Diversty Control Type
|
||||
#define ODM_AUTO_ANT 0
|
||||
#define ODM_FIX_MAIN_ANT 1
|
||||
#define ODM_FIX_AUX_ANT 2
|
||||
|
||||
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8195A)
|
||||
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821C)
|
||||
#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT|ODM_AC_ANTDIV_SUPPORT)
|
||||
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
|
||||
#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821)
|
||||
|
||||
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A|ODM_RTL8188F|ODM_RTL8723D)
|
||||
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821C)
|
||||
|
||||
#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
|
||||
|
||||
#define ODM_ANTDIV_2G BIT0
|
||||
#define ODM_ANTDIV_5G BIT1
|
||||
|
||||
#define ANTDIV_ON 1
|
||||
#define ANTDIV_OFF 0
|
||||
|
||||
#define FAT_ON 1
|
||||
#define FAT_OFF 0
|
||||
|
||||
#define TX_BY_DESC 1
|
||||
#define TX_BY_REG 0
|
||||
|
||||
#define RSSI_METHOD 0
|
||||
#define EVM_METHOD 1
|
||||
#define CRC32_METHOD 2
|
||||
|
||||
#define INIT_ANTDIV_TIMMER 0
|
||||
#define CANCEL_ANTDIV_TIMMER 1
|
||||
#define RELEASE_ANTDIV_TIMMER 2
|
||||
|
||||
#define CRC32_FAIL 1
|
||||
#define CRC32_OK 0
|
||||
|
||||
#define Evm_RSSI_TH_High 25
|
||||
#define Evm_RSSI_TH_Low 20
|
||||
|
||||
#define NORMAL_STATE_MIAN 1
|
||||
#define NORMAL_STATE_AUX 2
|
||||
#define TRAINING_STATE 3
|
||||
|
||||
#define FORCE_RSSI_DIFF 10
|
||||
|
||||
#define CSI_ON 1
|
||||
#define CSI_OFF 0
|
||||
|
||||
#define DIVON_CSIOFF 1
|
||||
#define DIVOFF_CSION 2
|
||||
|
||||
#define BDC_DIV_TRAIN_STATE 0
|
||||
#define BDC_BFer_TRAIN_STATE 1
|
||||
#define BDC_DECISION_STATE 2
|
||||
#define BDC_BF_HOLD_STATE 3
|
||||
#define BDC_DIV_HOLD_STATE 4
|
||||
|
||||
#define BDC_MODE_1 1
|
||||
#define BDC_MODE_2 2
|
||||
#define BDC_MODE_3 3
|
||||
#define BDC_MODE_4 4
|
||||
#define BDC_MODE_NULL 0xff
|
||||
|
||||
/*SW S0S1 antenna diversity*/
|
||||
#define SWAW_STEP_INIT 0xff
|
||||
#define SWAW_STEP_PEEK 0
|
||||
#define SWAW_STEP_DETERMINE 1
|
||||
|
||||
#define RSSI_CHECK_RESET_PERIOD 10
|
||||
#define RSSI_CHECK_THRESHOLD 50
|
||||
|
||||
/*Hong Lin Smart antenna*/
|
||||
#define HL_SMTANT_2WIRE_DATA_LEN 24
|
||||
|
||||
//1 ============================================================
|
||||
//1 structure
|
||||
//1 ============================================================
|
||||
|
||||
|
||||
typedef struct _SW_Antenna_Switch_
|
||||
{
|
||||
u1Byte Double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/
|
||||
u1Byte try_flag;
|
||||
s4Byte PreRSSI;
|
||||
u1Byte CurAntenna;
|
||||
u1Byte PreAntenna;
|
||||
u1Byte RSSI_Trying;
|
||||
u1Byte reset_idx;
|
||||
u1Byte Train_time;
|
||||
u1Byte Train_time_flag; /*base on RSSI difference between two antennas*/
|
||||
RT_TIMER phydm_SwAntennaSwitchTimer;
|
||||
u4Byte PktCnt_SWAntDivByCtrlFrame;
|
||||
BOOLEAN bSWAntDivByCtrlFrame;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if USE_WORKITEM
|
||||
RT_WORK_ITEM phydm_SwAntennaSwitchWorkitem;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* AntDect (Before link Antenna Switch check) need to be moved*/
|
||||
u2Byte Single_Ant_Counter;
|
||||
u2Byte Dual_Ant_Counter;
|
||||
u2Byte Aux_FailDetec_Counter;
|
||||
u2Byte Retry_Counter;
|
||||
u1Byte SWAS_NoLink_State;
|
||||
u4Byte SWAS_NoLink_BK_Reg948;
|
||||
BOOLEAN ANTA_ON; /*To indicate Ant A is or not*/
|
||||
BOOLEAN ANTB_ON; /*To indicate Ant B is on or not*/
|
||||
BOOLEAN Pre_Aux_FailDetec;
|
||||
BOOLEAN RSSI_AntDect_bResult;
|
||||
u1Byte Ant5G;
|
||||
u1Byte Ant2G;
|
||||
|
||||
|
||||
}SWAT_T, *pSWAT_T;
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
|
||||
typedef struct _BF_DIV_COEX_
|
||||
{
|
||||
BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
|
||||
u1Byte BDCcoexType_wBfer;
|
||||
u1Byte num_Txbfee_Client;
|
||||
u1Byte num_Txbfer_Client;
|
||||
u1Byte BDC_Try_counter;
|
||||
u1Byte BDC_Hold_counter;
|
||||
u1Byte BDC_Mode;
|
||||
u1Byte BDC_active_Mode;
|
||||
u1Byte BDC_state;
|
||||
u1Byte BDC_RxIdleUpdate_counter;
|
||||
u1Byte num_Client;
|
||||
u1Byte pre_num_Client;
|
||||
u1Byte num_BfTar;
|
||||
u1Byte num_DivTar;
|
||||
|
||||
BOOLEAN bAll_DivSta_Idle;
|
||||
BOOLEAN bAll_BFSta_Idle;
|
||||
BOOLEAN BDC_Try_flag;
|
||||
BOOLEAN BF_pass;
|
||||
BOOLEAN DIV_pass;
|
||||
}BDC_T,*pBDC_T;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
|
||||
typedef struct _SMART_ANTENNA_TRAINNING_ {
|
||||
u4Byte latch_time;
|
||||
BOOLEAN pkt_skip_statistic_en;
|
||||
u4Byte fix_beam_pattern_en;
|
||||
u4Byte fix_training_num_en;
|
||||
u4Byte fix_beam_pattern_codeword;
|
||||
u4Byte update_beam_codeword;
|
||||
u4Byte ant_num; /*number of used smart beam antenna*/
|
||||
u4Byte ant_num_total;/*number of total smart beam antenna*/
|
||||
u4Byte first_train_ant; /*decide witch antenna to train first*/
|
||||
u4Byte rfu_codeword_table[4]; /*2G beam truth table*/
|
||||
u4Byte rfu_codeword_table_5g[4]; /*5G beam truth table*/
|
||||
u4Byte beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/
|
||||
u4Byte data_codeword_bit_num;
|
||||
u1Byte per_beam_training_pkt_num;
|
||||
u1Byte decision_holding_period;
|
||||
u1Byte pkt_counter;
|
||||
u4Byte fast_training_beam_num;
|
||||
u4Byte pre_fast_training_beam_num;
|
||||
u4Byte pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u1Byte beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u1Byte beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u4Byte pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u4Byte pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u4Byte rx_idle_beam[SUPPORT_RF_PATH_NUM];
|
||||
u4Byte pre_codeword;
|
||||
BOOLEAN force_update_beam_en;
|
||||
u4Byte beacon_counter;
|
||||
u4Byte pre_beacon_counter;
|
||||
u1Byte update_beam_idx;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_WORK_ITEM hl_smart_antenna_workitem;
|
||||
RT_WORK_ITEM hl_smart_antenna_decision_workitem;
|
||||
#endif
|
||||
|
||||
} SAT_T, *pSAT_T;
|
||||
#endif
|
||||
|
||||
typedef struct _FAST_ANTENNA_TRAINNING_
|
||||
{
|
||||
u1Byte Bssid[6];
|
||||
u1Byte antsel_rx_keep_0;
|
||||
u1Byte antsel_rx_keep_1;
|
||||
u1Byte antsel_rx_keep_2;
|
||||
u1Byte antsel_rx_keep_3;
|
||||
u4Byte antSumRSSI[7];
|
||||
u4Byte antRSSIcnt[7];
|
||||
u4Byte antAveRSSI[7];
|
||||
u1Byte FAT_State;
|
||||
u4Byte TrainIdx;
|
||||
u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte MainAnt_Sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte AuxAnt_Sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte MainAnt_Cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte AuxAnt_Cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u1Byte RxIdleAnt;
|
||||
u1Byte AntDiv_OnOff;
|
||||
BOOLEAN bBecomeLinked;
|
||||
u4Byte MinMaxRSSI;
|
||||
u1Byte idx_AntDiv_counter_2G;
|
||||
u1Byte idx_AntDiv_counter_5G;
|
||||
u1Byte AntDiv_2G_5G;
|
||||
u4Byte CCK_counter_main;
|
||||
u4Byte CCK_counter_aux;
|
||||
u4Byte OFDM_counter_main;
|
||||
u4Byte OFDM_counter_aux;
|
||||
|
||||
#ifdef ODM_EVM_ENHANCE_ANTDIV
|
||||
u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
BOOLEAN EVM_method_enable;
|
||||
u1Byte TargetAnt_EVM;
|
||||
u1Byte TargetAnt_CRC32;
|
||||
u1Byte TargetAnt_enhance;
|
||||
u1Byte pre_TargetAnt_enhance;
|
||||
u2Byte Main_MPDU_OK_cnt;
|
||||
u2Byte Aux_MPDU_OK_cnt;
|
||||
|
||||
u4Byte CRC32_Ok_Cnt;
|
||||
u4Byte CRC32_Fail_Cnt;
|
||||
u4Byte MainCRC32_Ok_Cnt;
|
||||
u4Byte AuxCRC32_Ok_Cnt;
|
||||
u4Byte MainCRC32_Fail_Cnt;
|
||||
u4Byte AuxCRC32_Fail_Cnt;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
u4Byte CCK_CtrlFrame_Cnt_main;
|
||||
u4Byte CCK_CtrlFrame_Cnt_aux;
|
||||
u4Byte OFDM_CtrlFrame_Cnt_main;
|
||||
u4Byte OFDM_CtrlFrame_Cnt_aux;
|
||||
u4Byte MainAnt_CtrlFrame_Sum;
|
||||
u4Byte AuxAnt_CtrlFrame_Sum;
|
||||
u4Byte MainAnt_CtrlFrame_Cnt;
|
||||
u4Byte AuxAnt_CtrlFrame_Cnt;
|
||||
#endif
|
||||
u1Byte b_fix_tx_ant;
|
||||
BOOLEAN fix_ant_bfee;
|
||||
BOOLEAN enable_ctrl_frame_antdiv;
|
||||
BOOLEAN use_ctrl_frame_antdiv;
|
||||
u1Byte hw_antsw_occur;
|
||||
u1Byte *pForceTxAntByDesc;
|
||||
u1Byte ForceTxAntByDesc; /*A temp value, will hook to driver team's outer parameter later*/
|
||||
u1Byte *pDefaultS0S1;
|
||||
u1Byte DefaultS0S1;
|
||||
}FAT_T,*pFAT_T;
|
||||
|
||||
|
||||
//1 ============================================================
|
||||
//1 enumeration
|
||||
//1 ============================================================
|
||||
|
||||
|
||||
|
||||
typedef enum _FAT_STATE /*Fast antenna training*/
|
||||
{
|
||||
FAT_BEFORE_LINK_STATE = 0,
|
||||
FAT_PREPARE_STATE = 1,
|
||||
FAT_TRAINING_STATE = 2,
|
||||
FAT_DECISION_STATE = 3
|
||||
}FAT_STATE_E, *PFAT_STATE_E;
|
||||
|
||||
typedef enum _ANT_DIV_TYPE
|
||||
{
|
||||
NO_ANTDIV = 0xFF,
|
||||
CG_TRX_HW_ANTDIV = 0x01,
|
||||
CGCS_RX_HW_ANTDIV = 0x02,
|
||||
FIXED_HW_ANTDIV = 0x03,
|
||||
CG_TRX_SMART_ANTDIV = 0x04,
|
||||
CGCS_RX_SW_ANTDIV = 0x05,
|
||||
S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/
|
||||
S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/
|
||||
HL_SW_SMART_ANT_TYPE1 = 0x10 /*Hong-Lin Smart antenna use for 8821AE which is a 2 Ant. entitys, and each Ant. is equipped with 4 antenna patterns*/
|
||||
}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
|
||||
|
||||
|
||||
//1 ============================================================
|
||||
//1 function prototype
|
||||
//1 ============================================================
|
||||
|
||||
|
||||
VOID
|
||||
ODM_StopAntennaSwitchDm(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_enable_antenna_diversity(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_SetAntConfig(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte antSetting // 0=A, 1=B, 2=C, ....
|
||||
);
|
||||
|
||||
|
||||
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
|
||||
|
||||
VOID ODM_SwAntDivRestAfterLink(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
|
||||
|
||||
VOID
|
||||
ODM_UpdateRxIdleAnt(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Ant
|
||||
);
|
||||
|
||||
#if (RTL8723B_SUPPORT == 1)
|
||||
VOID
|
||||
ODM_UpdateRxIdleAnt_8723B(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Ant,
|
||||
IN u4Byte DefaultAnt,
|
||||
IN u4Byte OptionalAnt
|
||||
);
|
||||
#endif
|
||||
|
||||
#if (RTL8188F_SUPPORT == 1)
|
||||
VOID
|
||||
phydm_update_rx_idle_antenna_8188F(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte default_ant
|
||||
);
|
||||
#endif
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
|
||||
VOID
|
||||
phydm_set_tx_ant_pwr_8723d(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Ant
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
ODM_SW_AntDiv_Callback(
|
||||
IN PRT_TIMER pTimer
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_SW_AntDiv_WorkitemCallback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
VOID
|
||||
ODM_SW_AntDiv_WorkitemCallback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_SW_AntDiv_Callback(
|
||||
void *FunctionContext
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
VOID
|
||||
odm_S0S1_SwAntDivByCtrlFrame(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Step
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_AntselStatisticsOfCtrlFrame(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte antsel_tr_mux,
|
||||
IN u4Byte RxPWDBAll
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PVOID p_phy_info_void,
|
||||
IN PVOID p_pkt_info_void
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef ODM_EVM_ENHANCE_ANTDIV
|
||||
VOID
|
||||
odm_EVM_FastAntTrainingCallback(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
#endif
|
||||
|
||||
VOID
|
||||
odm_HW_AntDiv(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
|
||||
VOID
|
||||
odm_FastAntTraining(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_FastAntTrainingCallback(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_FastAntTrainingWorkItemCallback(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
phydm_beam_switch_workitem_callback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_beam_decision_workitem_callback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
VOID
|
||||
phydm_update_beam_pattern(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte codeword,
|
||||
IN u4Byte codeword_length
|
||||
);
|
||||
|
||||
void
|
||||
phydm_set_all_ant_same_beam_num(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_hl_smart_ant_debug(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *const dm_value,
|
||||
IN u4Byte *_used,
|
||||
OUT char *output,
|
||||
IN u4Byte *_out_len
|
||||
);
|
||||
|
||||
#endif/*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/
|
||||
|
||||
VOID
|
||||
ODM_AntDivInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_AntDiv(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_AntselStatistics(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte antsel_tr_mux,
|
||||
IN u4Byte MacId,
|
||||
IN u4Byte utility,
|
||||
IN u1Byte method,
|
||||
IN u1Byte isCCKrate
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_Process_RSSIForAntDiv(
|
||||
IN OUT PVOID pDM_VOID,
|
||||
IN PVOID p_phy_info_void,
|
||||
IN PVOID p_pkt_info_void
|
||||
);
|
||||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
VOID
|
||||
ODM_SetTxAntByTxInfo(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte pDesc,
|
||||
IN u1Byte macId
|
||||
);
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
struct tx_desc; /*declared tx_desc here or compile error happened when enabled 8822B*/
|
||||
|
||||
VOID
|
||||
ODM_SetTxAntByTxInfo(
|
||||
struct rtl8192cd_priv *priv,
|
||||
struct tx_desc *pdesc,
|
||||
unsigned short aid
|
||||
);
|
||||
|
||||
#if 1/*def def CONFIG_WLAN_HAL*/
|
||||
VOID
|
||||
ODM_SetTxAntByTxInfo_HAL(
|
||||
struct rtl8192cd_priv *priv,
|
||||
PVOID pdesc_data,
|
||||
u2Byte aid
|
||||
);
|
||||
#endif /*#ifdef CONFIG_WLAN_HAL*/
|
||||
#endif
|
||||
|
||||
|
||||
VOID
|
||||
ODM_AntDiv_Config(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_AntDivTimers(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte state
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_antdiv_debug(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *const dm_value,
|
||||
IN u4Byte *_used,
|
||||
OUT char *output,
|
||||
IN u4Byte *_out_len
|
||||
);
|
||||
|
||||
#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/
|
||||
|
||||
VOID
|
||||
ODM_AntDivReset(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_AntennaDiversityInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_AntennaDiversity(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#endif /*#ifndef __ODMANTDIV_H__*/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,367 @@
|
||||
#ifndef __INC_PHYDM_BEAMFORMING_H
|
||||
#define __INC_PHYDM_BEAMFORMING_H
|
||||
|
||||
#ifndef BEAMFORMING_SUPPORT
|
||||
#define BEAMFORMING_SUPPORT 0
|
||||
#endif
|
||||
|
||||
/*Beamforming Related*/
|
||||
#include "txbf/halcomtxbf.h"
|
||||
#include "txbf/haltxbfjaguar.h"
|
||||
#include "txbf/haltxbf8192e.h"
|
||||
#include "txbf/haltxbf8814a.h"
|
||||
#include "txbf/haltxbf8822b.h"
|
||||
#include "txbf/haltxbfinterface.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
#define MAX_BEAMFORMEE_SU 2
|
||||
#define MAX_BEAMFORMER_SU 2
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#define MAX_BEAMFORMEE_MU 6
|
||||
#define MAX_BEAMFORMER_MU 1
|
||||
#else
|
||||
#define MAX_BEAMFORMEE_MU 0
|
||||
#define MAX_BEAMFORMER_MU 0
|
||||
#endif
|
||||
|
||||
#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
|
||||
#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
/*for different naming between WIN and CE*/
|
||||
#define BEACON_QUEUE BCN_QUEUE_INX
|
||||
#define NORMAL_QUEUE MGT_QUEUE_INX
|
||||
#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
|
||||
#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
|
||||
#endif
|
||||
|
||||
typedef enum _BEAMFORMING_ENTRY_STATE {
|
||||
BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
|
||||
BEAMFORMING_ENTRY_STATE_INITIALIZEING,
|
||||
BEAMFORMING_ENTRY_STATE_INITIALIZED,
|
||||
BEAMFORMING_ENTRY_STATE_PROGRESSING,
|
||||
BEAMFORMING_ENTRY_STATE_PROGRESSED
|
||||
} BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE;
|
||||
|
||||
|
||||
typedef enum _BEAMFORMING_NOTIFY_STATE {
|
||||
BEAMFORMING_NOTIFY_NONE,
|
||||
BEAMFORMING_NOTIFY_ADD,
|
||||
BEAMFORMING_NOTIFY_DELETE,
|
||||
BEAMFORMEE_NOTIFY_ADD_SU,
|
||||
BEAMFORMEE_NOTIFY_DELETE_SU,
|
||||
BEAMFORMEE_NOTIFY_ADD_MU,
|
||||
BEAMFORMEE_NOTIFY_DELETE_MU,
|
||||
BEAMFORMING_NOTIFY_RESET
|
||||
} BEAMFORMING_NOTIFY_STATE, *PBEAMFORMING_NOTIFY_STATE;
|
||||
|
||||
typedef enum _BEAMFORMING_CAP {
|
||||
BEAMFORMING_CAP_NONE = 0x0,
|
||||
BEAMFORMER_CAP_HT_EXPLICIT = BIT1,
|
||||
BEAMFORMEE_CAP_HT_EXPLICIT = BIT2,
|
||||
BEAMFORMER_CAP_VHT_SU = BIT5, /* Self has er Cap, because Reg er & peer ee */
|
||||
BEAMFORMEE_CAP_VHT_SU = BIT6, /* Self has ee Cap, because Reg ee & peer er */
|
||||
BEAMFORMER_CAP_VHT_MU = BIT7, /* Self has er Cap, because Reg er & peer ee */
|
||||
BEAMFORMEE_CAP_VHT_MU = BIT8, /* Self has ee Cap, because Reg ee & peer er */
|
||||
BEAMFORMER_CAP = BIT9,
|
||||
BEAMFORMEE_CAP = BIT10,
|
||||
}BEAMFORMING_CAP, *PBEAMFORMING_CAP;
|
||||
|
||||
|
||||
typedef enum _SOUNDING_MODE {
|
||||
SOUNDING_SW_VHT_TIMER = 0x0,
|
||||
SOUNDING_SW_HT_TIMER = 0x1,
|
||||
SOUNDING_STOP_All_TIMER = 0x2,
|
||||
SOUNDING_HW_VHT_TIMER = 0x3,
|
||||
SOUNDING_HW_HT_TIMER = 0x4,
|
||||
SOUNDING_STOP_OID_TIMER = 0x5,
|
||||
SOUNDING_AUTO_VHT_TIMER = 0x6,
|
||||
SOUNDING_AUTO_HT_TIMER = 0x7,
|
||||
SOUNDING_FW_VHT_TIMER = 0x8,
|
||||
SOUNDING_FW_HT_TIMER = 0x9,
|
||||
}SOUNDING_MODE, *PSOUNDING_MODE;
|
||||
|
||||
typedef struct _RT_BEAMFORM_STAINFO {
|
||||
pu1Byte RA;
|
||||
u2Byte AID;
|
||||
u2Byte MacID;
|
||||
u1Byte MyMacAddr[6];
|
||||
WIRELESS_MODE WirelessMode;
|
||||
CHANNEL_WIDTH BW;
|
||||
BEAMFORMING_CAP BeamformCap;
|
||||
u1Byte HtBeamformCap;
|
||||
u2Byte VhtBeamformCap;
|
||||
u1Byte CurBeamform;
|
||||
u2Byte CurBeamformVHT;
|
||||
} RT_BEAMFORM_STAINFO, *PRT_BEAMFORM_STAINFO;
|
||||
|
||||
|
||||
typedef struct _RT_BEAMFORMEE_ENTRY {
|
||||
BOOLEAN bUsed;
|
||||
BOOLEAN bTxBF;
|
||||
BOOLEAN bSound;
|
||||
u2Byte AID; /*Used to construct AID field of NDPA packet.*/
|
||||
u2Byte MacId; /*Used to Set Reg42C in IBSS mode. */
|
||||
u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
|
||||
u2Byte G_ID; /*Used to fill Tx DESC*/
|
||||
u1Byte MyMacAddr[6];
|
||||
u1Byte MacAddr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
|
||||
CHANNEL_WIDTH SoundBW; /*Sounding BandWidth*/
|
||||
u2Byte SoundPeriod;
|
||||
BEAMFORMING_CAP BeamformEntryCap;
|
||||
BEAMFORMING_ENTRY_STATE BeamformEntryState;
|
||||
BOOLEAN bBeamformingInProgress;
|
||||
/*u1Byte LogSeq; // Move to _RT_BEAMFORMER_ENTRY*/
|
||||
/*u2Byte LogRetryCnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/
|
||||
/*u2Byte LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/
|
||||
u2Byte LogStatusFailCnt:5; // 0~21
|
||||
u2Byte DefaultCSICnt:5; // 0~21
|
||||
u1Byte CSIMatrix[327];
|
||||
u2Byte CSIMatrixLen;
|
||||
u1Byte NumofSoundingDim;
|
||||
u1Byte CompSteeringNumofBFer;
|
||||
u1Byte su_reg_index;
|
||||
/*For MU-MIMO*/
|
||||
BOOLEAN is_mu_sta;
|
||||
u1Byte mu_reg_index;
|
||||
u1Byte gid_valid[8];
|
||||
u1Byte user_position[16];
|
||||
} RT_BEAMFORMEE_ENTRY, *PRT_BEAMFORMEE_ENTRY;
|
||||
|
||||
typedef struct _RT_BEAMFORMER_ENTRY {
|
||||
BOOLEAN bUsed;
|
||||
/*P_AID of BFer entry is probably not used*/
|
||||
u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
|
||||
u2Byte G_ID;
|
||||
u1Byte MyMacAddr[6];
|
||||
u1Byte MacAddr[6];
|
||||
BEAMFORMING_CAP BeamformEntryCap;
|
||||
u1Byte NumofSoundingDim;
|
||||
u1Byte ClockResetTimes; /*Modified by Jeffery @2015-04-10*/
|
||||
u1Byte PreLogSeq; /*Modified by Jeffery @2015-03-30*/
|
||||
u1Byte LogSeq; /*Modified by Jeffery @2014-10-29*/
|
||||
u2Byte LogRetryCnt:3; /*Modified by Jeffery @2014-10-29*/
|
||||
u2Byte LogSuccess:2; /*Modified by Jeffery @2014-10-29*/
|
||||
u1Byte su_reg_index;
|
||||
/*For MU-MIMO*/
|
||||
BOOLEAN is_mu_ap;
|
||||
u1Byte gid_valid[8];
|
||||
u1Byte user_position[16];
|
||||
u2Byte AID;
|
||||
} RT_BEAMFORMER_ENTRY, *PRT_BEAMFORMER_ENTRY;
|
||||
|
||||
typedef struct _RT_SOUNDING_INFO {
|
||||
u1Byte SoundIdx;
|
||||
CHANNEL_WIDTH SoundBW;
|
||||
SOUNDING_MODE SoundMode;
|
||||
u2Byte SoundPeriod;
|
||||
} RT_SOUNDING_INFO, *PRT_SOUNDING_INFO;
|
||||
|
||||
|
||||
|
||||
typedef struct _RT_BEAMFORMING_OID_INFO {
|
||||
u1Byte SoundOidIdx;
|
||||
CHANNEL_WIDTH SoundOidBW;
|
||||
SOUNDING_MODE SoundOidMode;
|
||||
u2Byte SoundOidPeriod;
|
||||
} RT_BEAMFORMING_OID_INFO, *PRT_BEAMFORMING_OID_INFO;
|
||||
|
||||
|
||||
typedef struct _RT_BEAMFORMING_INFO {
|
||||
BEAMFORMING_CAP BeamformCap;
|
||||
RT_BEAMFORMEE_ENTRY BeamformeeEntry[BEAMFORMEE_ENTRY_NUM];
|
||||
RT_BEAMFORMER_ENTRY BeamformerEntry[BEAMFORMER_ENTRY_NUM];
|
||||
RT_BEAMFORM_STAINFO BeamformSTAinfo;
|
||||
u1Byte BeamformeeCurIdx;
|
||||
RT_TIMER BeamformingTimer;
|
||||
RT_TIMER mu_timer;
|
||||
RT_SOUNDING_INFO SoundingInfo;
|
||||
RT_BEAMFORMING_OID_INFO BeamformingOidInfo;
|
||||
HAL_TXBF_INFO TxbfInfo;
|
||||
u1Byte SoundingSequence;
|
||||
u1Byte beamformee_su_cnt;
|
||||
u1Byte beamformer_su_cnt;
|
||||
u4Byte beamformee_su_reg_maping;
|
||||
u4Byte beamformer_su_reg_maping;
|
||||
/*For MU-MINO*/
|
||||
u1Byte beamformee_mu_cnt;
|
||||
u1Byte beamformer_mu_cnt;
|
||||
u4Byte beamformee_mu_reg_maping;
|
||||
u1Byte mu_ap_index;
|
||||
BOOLEAN is_mu_sounding;
|
||||
u1Byte FirstMUBFeeIndex;
|
||||
BOOLEAN is_mu_sounding_in_progress;
|
||||
BOOLEAN dbg_disable_mu_tx;
|
||||
BOOLEAN applyVmatrix;
|
||||
BOOLEAN snding3SS;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PADAPTER SourceAdapter;
|
||||
#endif
|
||||
/* Control register */
|
||||
u4Byte RegMUTxCtrl; /* For USB/SDIO interfaces aync I/O */
|
||||
} RT_BEAMFORMING_INFO, *PRT_BEAMFORMING_INFO;
|
||||
|
||||
|
||||
typedef struct _RT_NDPA_STA_INFO {
|
||||
u2Byte AID:12;
|
||||
u2Byte FeedbackType:1;
|
||||
u2Byte NcIndex:3;
|
||||
} RT_NDPA_STA_INFO, *PRT_NDPA_STA_INFO;
|
||||
|
||||
typedef enum _PHYDM_ACTING_TYPE {
|
||||
PhyDM_ACTING_AS_IBSS = 0,
|
||||
PhyDM_ACTING_AS_AP = 1
|
||||
} PHYDM_ACTING_TYPE;
|
||||
|
||||
|
||||
BEAMFORMING_CAP
|
||||
phydm_Beamforming_GetEntryBeamCapByMacId(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte MacId
|
||||
);
|
||||
|
||||
PRT_BEAMFORMEE_ENTRY
|
||||
phydm_Beamforming_GetBFeeEntryByAddr(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
OUT pu1Byte Idx
|
||||
);
|
||||
|
||||
PRT_BEAMFORMER_ENTRY
|
||||
phydm_Beamforming_GetBFerEntryByAddr(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte TA,
|
||||
OUT pu1Byte Idx
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_Beamforming_Notify(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
phydm_actingDetermine(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PHYDM_ACTING_TYPE type
|
||||
);
|
||||
|
||||
VOID
|
||||
Beamforming_Enter(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u2Byte staIdx
|
||||
);
|
||||
|
||||
VOID
|
||||
Beamforming_Leave(
|
||||
IN PVOID pDM_VOID,
|
||||
pu1Byte RA
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
BeamformingStart_FW(
|
||||
IN PVOID pDM_VOID,
|
||||
u1Byte Idx
|
||||
);
|
||||
|
||||
VOID
|
||||
Beamforming_CheckSoundingSuccess(
|
||||
IN PVOID pDM_VOID,
|
||||
BOOLEAN Status
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_Beamforming_End_SW(
|
||||
IN PVOID pDM_VOID,
|
||||
BOOLEAN Status
|
||||
);
|
||||
|
||||
VOID
|
||||
Beamforming_TimerCallback(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_Beamforming_Init(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
|
||||
BEAMFORMING_CAP
|
||||
phydm_Beamforming_GetBeamCap(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PRT_BEAMFORMING_INFO pBeamInfo
|
||||
);
|
||||
|
||||
|
||||
BOOLEAN
|
||||
BeamformingControl_V1(
|
||||
IN PVOID pDM_VOID,
|
||||
pu1Byte RA,
|
||||
u1Byte AID,
|
||||
u1Byte Mode,
|
||||
CHANNEL_WIDTH BW,
|
||||
u1Byte Rate
|
||||
);
|
||||
|
||||
|
||||
BOOLEAN
|
||||
phydm_BeamformingControl_V2(
|
||||
IN PVOID pDM_VOID,
|
||||
u1Byte Idx,
|
||||
u1Byte Mode,
|
||||
CHANNEL_WIDTH BW,
|
||||
u2Byte Period
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_Beamforming_Watchdog(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Beamforming_SWTimerCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PRT_TIMER pTimer
|
||||
#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
void *FunctionContext
|
||||
#endif
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Beamforming_SendHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN CHANNEL_WIDTH BW,
|
||||
IN u1Byte QIdx
|
||||
);
|
||||
|
||||
|
||||
BOOLEAN
|
||||
Beamforming_SendVHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN u2Byte AID,
|
||||
IN CHANNEL_WIDTH BW,
|
||||
IN u1Byte QIdx
|
||||
);
|
||||
|
||||
#else
|
||||
#define Beamforming_GidPAid(Adapter, pTcb)
|
||||
#define phydm_actingDetermine(pDM_Odm, type) FALSE
|
||||
#define Beamforming_Enter(pDM_Odm, staIdx)
|
||||
#define Beamforming_Leave(pDM_Odm, RA)
|
||||
#define Beamforming_End_FW(pDMOdm)
|
||||
#define BeamformingControl_V1(pDM_Odm, RA, AID, Mode, BW, Rate) TRUE
|
||||
#define BeamformingControl_V2(pDM_Odm, Idx, Mode, BW, Period) TRUE
|
||||
#define phydm_Beamforming_End_SW(pDM_Odm, _Status)
|
||||
#define Beamforming_TimerCallback(pDM_Odm)
|
||||
#define phydm_Beamforming_Init(pDM_Odm)
|
||||
#define phydm_BeamformingControl_V2(pDM_Odm, _Idx, _Mode, _BW, _Period) FALSE
|
||||
#define Beamforming_Watchdog(pDM_Odm)
|
||||
#define phydm_Beamforming_Watchdog(pDM_Odm)
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,400 @@
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
/*Set NHM period, threshold, disable ignore cca or not, disable ignore txon or not*/
|
||||
VOID
|
||||
phydm_NHMsetting(
|
||||
IN PVOID pDM_VOID,
|
||||
u1Byte NHMsetting
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
|
||||
|
||||
if (NHMsetting == SET_NHM_SETTING){
|
||||
|
||||
/*Set inexclude_cca, inexclude_txon*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9, CCX_INFO->NHM_inexclude_cca);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10, CCX_INFO->NHM_inexclude_txon);
|
||||
|
||||
/*Set NHM period*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord, CCX_INFO->NHM_period);
|
||||
|
||||
/*Set NHM threshold*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0, CCX_INFO->NHM_th[0]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1, CCX_INFO->NHM_th[1]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2, CCX_INFO->NHM_th[2]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3, CCX_INFO->NHM_th[3]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0, CCX_INFO->NHM_th[4]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1, CCX_INFO->NHM_th[5]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2, CCX_INFO->NHM_th[6]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3, CCX_INFO->NHM_th[7]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, CCX_INFO->NHM_th[8]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2, CCX_INFO->NHM_th[9]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3, CCX_INFO->NHM_th[10]);
|
||||
|
||||
/*CCX EN*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8, CCX_EN);
|
||||
|
||||
}
|
||||
else if (NHMsetting == STORE_NHM_SETTING) {
|
||||
|
||||
/*Store pervious disable_ignore_cca, disable_ignore_txon*/
|
||||
CCX_INFO->NHM_inexclude_cca_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9);
|
||||
CCX_INFO->NHM_inexclude_txon_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10);
|
||||
|
||||
/*Store pervious NHM period*/
|
||||
CCX_INFO->NHM_period_restore = (u2Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord);
|
||||
|
||||
/*Store NHM threshold*/
|
||||
CCX_INFO->NHM_th_restore[0] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0);
|
||||
CCX_INFO->NHM_th_restore[1] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1);
|
||||
CCX_INFO->NHM_th_restore[2] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2);
|
||||
CCX_INFO->NHM_th_restore[3] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3);
|
||||
CCX_INFO->NHM_th_restore[4] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0);
|
||||
CCX_INFO->NHM_th_restore[5] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1);
|
||||
CCX_INFO->NHM_th_restore[6] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2);
|
||||
CCX_INFO->NHM_th_restore[7] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3);
|
||||
CCX_INFO->NHM_th_restore[8] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0);
|
||||
CCX_INFO->NHM_th_restore[9] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2);
|
||||
CCX_INFO->NHM_th_restore[10] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3);
|
||||
}
|
||||
else if (NHMsetting == RESTORE_NHM_SETTING) {
|
||||
|
||||
/*Set disable_ignore_cca, disable_ignore_txon*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9, CCX_INFO->NHM_inexclude_cca_restore);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10, CCX_INFO->NHM_inexclude_txon_restore);
|
||||
|
||||
/*Set NHM period*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord, CCX_INFO->NHM_period);
|
||||
|
||||
/*Set NHM threshold*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[0]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1, CCX_INFO->NHM_th_restore[1]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[2]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[3]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[4]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1, CCX_INFO->NHM_th_restore[5]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[6]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[7]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[8]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[9]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[10]);
|
||||
}
|
||||
else
|
||||
return;
|
||||
}
|
||||
|
||||
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
|
||||
|
||||
if (NHMsetting == SET_NHM_SETTING){
|
||||
|
||||
/*Set disable_ignore_cca, disable_ignore_txon*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9, CCX_INFO->NHM_inexclude_cca);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10, CCX_INFO->NHM_inexclude_txon);
|
||||
|
||||
/*Set NHM period*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord, CCX_INFO->NHM_period);
|
||||
|
||||
/*Set NHM threshold*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0, CCX_INFO->NHM_th[0]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1, CCX_INFO->NHM_th[1]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2, CCX_INFO->NHM_th[2]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3, CCX_INFO->NHM_th[3]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0, CCX_INFO->NHM_th[4]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1, CCX_INFO->NHM_th[5]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2, CCX_INFO->NHM_th[6]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3, CCX_INFO->NHM_th[7]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0, CCX_INFO->NHM_th[8]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2, CCX_INFO->NHM_th[9]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3, CCX_INFO->NHM_th[10]);
|
||||
|
||||
/*CCX EN*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT8, CCX_EN);
|
||||
}
|
||||
else if (NHMsetting == STORE_NHM_SETTING) {
|
||||
|
||||
/*Store pervious disable_ignore_cca, disable_ignore_txon*/
|
||||
CCX_INFO->NHM_inexclude_cca_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9);
|
||||
CCX_INFO->NHM_inexclude_txon_restore= (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10);
|
||||
|
||||
/*Store pervious NHM period*/
|
||||
CCX_INFO->NHM_period_restore= (u2Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord);
|
||||
|
||||
/*Store NHM threshold*/
|
||||
CCX_INFO->NHM_th_restore[0] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0);
|
||||
CCX_INFO->NHM_th_restore[1] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1);
|
||||
CCX_INFO->NHM_th_restore[2] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2);
|
||||
CCX_INFO->NHM_th_restore[3] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3);
|
||||
CCX_INFO->NHM_th_restore[4] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0);
|
||||
CCX_INFO->NHM_th_restore[5] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1);
|
||||
CCX_INFO->NHM_th_restore[6] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2);
|
||||
CCX_INFO->NHM_th_restore[7] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3);
|
||||
CCX_INFO->NHM_th_restore[8] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0);
|
||||
CCX_INFO->NHM_th_restore[9] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2);
|
||||
CCX_INFO->NHM_th_restore[10] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3);
|
||||
|
||||
}
|
||||
else if (NHMsetting == RESTORE_NHM_SETTING) {
|
||||
|
||||
/*Set disable_ignore_cca, disable_ignore_txon*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9, CCX_INFO->NHM_inexclude_cca_restore);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10, CCX_INFO->NHM_inexclude_txon_restore);
|
||||
|
||||
/*Set NHM period*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord, CCX_INFO->NHM_period_restore);
|
||||
|
||||
/*Set NHM threshold*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0, CCX_INFO->NHM_th_restore[0]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1, CCX_INFO->NHM_th_restore[1]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2, CCX_INFO->NHM_th_restore[2]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3, CCX_INFO->NHM_th_restore[3]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0, CCX_INFO->NHM_th_restore[4]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1, CCX_INFO->NHM_th_restore[5]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2, CCX_INFO->NHM_th_restore[6]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3, CCX_INFO->NHM_th_restore[7]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0, CCX_INFO->NHM_th_restore[8]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2, CCX_INFO->NHM_th_restore[9]);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3, CCX_INFO->NHM_th_restore[10]);
|
||||
}
|
||||
else
|
||||
return;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_NHMtrigger(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
|
||||
|
||||
/*Trigger NHM*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
|
||||
}
|
||||
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
|
||||
|
||||
/*Trigger NHM*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_getNHMresult(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u4Byte value32;
|
||||
PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
|
||||
|
||||
value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT_11AC);
|
||||
CCX_INFO->NHM_result[0] = (u1Byte)(value32 & bMaskByte0);
|
||||
CCX_INFO->NHM_result[1] = (u1Byte)((value32 & bMaskByte1) >> 8);
|
||||
CCX_INFO->NHM_result[2] = (u1Byte)((value32 & bMaskByte2) >> 16);
|
||||
CCX_INFO->NHM_result[3] = (u1Byte)((value32 & bMaskByte3) >> 24);
|
||||
|
||||
value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
|
||||
CCX_INFO->NHM_result[4] = (u1Byte)(value32 & bMaskByte0);
|
||||
CCX_INFO->NHM_result[5] = (u1Byte)((value32 & bMaskByte1) >> 8);
|
||||
CCX_INFO->NHM_result[6] = (u1Byte)((value32 & bMaskByte2) >> 16);
|
||||
CCX_INFO->NHM_result[7] = (u1Byte)((value32 & bMaskByte3) >> 24);
|
||||
|
||||
value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC);
|
||||
CCX_INFO->NHM_result[8] = (u1Byte)(value32 & bMaskByte0);
|
||||
CCX_INFO->NHM_result[9] = (u1Byte)((value32 & bMaskByte1) >> 8);
|
||||
CCX_INFO->NHM_result[10] = (u1Byte)((value32 & bMaskByte2) >> 16);
|
||||
CCX_INFO->NHM_result[11] = (u1Byte)((value32 & bMaskByte3) >> 24);
|
||||
|
||||
/*Get NHM duration*/
|
||||
value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC);
|
||||
CCX_INFO->NHM_duration = (u2Byte)(value32 & bMaskLWord);
|
||||
|
||||
}
|
||||
|
||||
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
|
||||
|
||||
value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT_11N);
|
||||
CCX_INFO->NHM_result[0] = (u1Byte)(value32 & bMaskByte0);
|
||||
CCX_INFO->NHM_result[1] = (u1Byte)((value32 & bMaskByte1) >> 8);
|
||||
CCX_INFO->NHM_result[2] = (u1Byte)((value32 & bMaskByte2) >> 16);
|
||||
CCX_INFO->NHM_result[3] = (u1Byte)((value32 & bMaskByte3) >> 24);
|
||||
|
||||
value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
|
||||
CCX_INFO->NHM_result[4] = (u1Byte)(value32 & bMaskByte0);
|
||||
CCX_INFO->NHM_result[5] = (u1Byte)((value32 & bMaskByte1) >> 8);
|
||||
CCX_INFO->NHM_result[6] = (u1Byte)((value32 & bMaskByte2) >> 16);
|
||||
CCX_INFO->NHM_result[7] = (u1Byte)((value32 & bMaskByte3) >> 24);
|
||||
|
||||
value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT9_TO_CNT8_11N);
|
||||
CCX_INFO->NHM_result[8] = (u1Byte)((value32 & bMaskByte2) >> 16);
|
||||
CCX_INFO->NHM_result[9] = (u1Byte)((value32 & bMaskByte3) >> 24);
|
||||
|
||||
value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
|
||||
CCX_INFO->NHM_result[10] = (u1Byte)((value32 & bMaskByte2) >> 16);
|
||||
CCX_INFO->NHM_result[11] = (u1Byte)((value32 & bMaskByte3) >> 24);
|
||||
|
||||
/*Get NHM duration*/
|
||||
value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
|
||||
CCX_INFO->NHM_duration = (u2Byte)(value32 & bMaskLWord);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
phydm_checkNHMready(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u4Byte value32 = 0;
|
||||
u1Byte i;
|
||||
BOOLEAN ret = FALSE;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
|
||||
|
||||
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord);
|
||||
|
||||
for (i = 0; i < 200; i ++) {
|
||||
|
||||
ODM_delay_ms(1);
|
||||
if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT17)) {
|
||||
ret = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
|
||||
|
||||
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord);
|
||||
|
||||
for (i = 0; i < 200; i ++) {
|
||||
|
||||
ODM_delay_ms(1);
|
||||
if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT17) ) {
|
||||
ret = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_storeNHMsetting(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
|
||||
|
||||
|
||||
}
|
||||
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
|
||||
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_CLMsetting(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO;
|
||||
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskLWord, CCX_INFO->CLM_period); /*4us sample 1 time*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT8, 0x1); /*Enable CCX for CLM*/
|
||||
|
||||
} else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskLWord, CCX_INFO->CLM_period); /*4us sample 1 time*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT8, 0x1); /*Enable CCX for CLM*/
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, CCX_INFO->CLM_period*4));
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_CLMtrigger(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x0); /*Trigger CLM*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x1);
|
||||
} else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x0); /*Trigger CLM*/
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x1);
|
||||
}
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
phydm_checkCLMready(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u4Byte value32 = 0;
|
||||
BOOLEAN ret = FALSE;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
|
||||
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*make sure CLM calc is ready*/
|
||||
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
|
||||
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord); /*make sure CLM calc is ready*/
|
||||
|
||||
if ((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (value32 & BIT16))
|
||||
ret = TRUE;
|
||||
else if ((pDM_Odm->SupportICType & ODM_IC_11N_SERIES) && (value32 & BIT17))
|
||||
ret = TRUE;
|
||||
else
|
||||
ret = FALSE;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void
|
||||
phydm_getCLMresult(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO;
|
||||
|
||||
u4Byte value32 = 0;
|
||||
u2Byte results = 0;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
|
||||
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*read CLM calc result*/
|
||||
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
|
||||
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11N, bMaskDWord); /*read CLM calc result*/
|
||||
|
||||
CCX_INFO->CLM_result = (u2Byte)(value32 & bMaskLWord);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, CCX_INFO->CLM_result*4));
|
||||
|
||||
}
|
||||
@@ -0,0 +1,102 @@
|
||||
#ifndef __PHYDMCCX_H__
|
||||
#define __PHYDMCCX_H__
|
||||
|
||||
#define CCX_EN 1
|
||||
|
||||
#define SET_NHM_SETTING 0
|
||||
#define STORE_NHM_SETTING 1
|
||||
#define RESTORE_NHM_SETTING 2
|
||||
|
||||
/*
|
||||
#define NHM_EXCLUDE_CCA 0
|
||||
#define NHM_INCLUDE_CCA 1
|
||||
#define NHM_EXCLUDE_TXON 0
|
||||
#define NHM_INCLUDE_TXON 1
|
||||
*/
|
||||
|
||||
typedef enum NHM_inexclude_cca {
|
||||
NHM_EXCLUDE_CCA,
|
||||
NHM_INCLUDE_CCA
|
||||
}NHM_INEXCLUDE_CCA;
|
||||
|
||||
typedef enum NHM_inexclude_txon {
|
||||
NHM_EXCLUDE_TXON,
|
||||
NHM_INCLUDE_TXON
|
||||
}NHM_INEXCLUDE_TXON;
|
||||
|
||||
|
||||
typedef struct _CCX_INFO{
|
||||
|
||||
/*Settings*/
|
||||
u1Byte NHM_th[11];
|
||||
u2Byte NHM_period; /* 4us per unit */
|
||||
u2Byte CLM_period; /* 4us per unit */
|
||||
NHM_INEXCLUDE_TXON NHM_inexclude_txon;
|
||||
NHM_INEXCLUDE_CCA NHM_inexclude_cca;
|
||||
|
||||
/*Previous Settings*/
|
||||
u1Byte NHM_th_restore[11];
|
||||
u2Byte NHM_period_restore; /* 4us per unit */
|
||||
u2Byte CLM_period_restore; /* 4us per unit */
|
||||
NHM_INEXCLUDE_TXON NHM_inexclude_txon_restore;
|
||||
NHM_INEXCLUDE_CCA NHM_inexclude_cca_restore;
|
||||
|
||||
/*Report*/
|
||||
u1Byte NHM_result[12];
|
||||
u2Byte NHM_duration;
|
||||
u2Byte CLM_result;
|
||||
|
||||
|
||||
BOOLEAN echo_NHM_en;
|
||||
BOOLEAN echo_CLM_en;
|
||||
u1Byte echo_IGI;
|
||||
|
||||
}CCX_INFO, *PCCX_INFO;
|
||||
|
||||
/*NHM*/
|
||||
|
||||
VOID
|
||||
phydm_NHMsetting(
|
||||
IN PVOID pDM_VOID,
|
||||
u1Byte NHMsetting
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_NHMtrigger(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_getNHMresult(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
phydm_checkNHMready(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
/*CLM*/
|
||||
|
||||
VOID
|
||||
phydm_CLMsetting(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_CLMtrigger(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
phydm_checkCLMready(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_getCLMresult(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,381 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
VOID
|
||||
odm_SetCrystalCap(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte CrystalCap
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
|
||||
|
||||
if(pCfoTrack->CrystalCap == CrystalCap)
|
||||
return;
|
||||
|
||||
pCfoTrack->CrystalCap = CrystalCap;
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8188F)) {
|
||||
/* write 0x24[22:17] = 0x24[16:11] = CrystalCap */
|
||||
CrystalCap = CrystalCap & 0x3F;
|
||||
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap|(CrystalCap << 6)));
|
||||
} else if (pDM_Odm->SupportICType & ODM_RTL8812) {
|
||||
/* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */
|
||||
CrystalCap = CrystalCap & 0x3F;
|
||||
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap|(CrystalCap << 6)));
|
||||
} else if ((pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723B|ODM_RTL8192E|ODM_RTL8821))) {
|
||||
/* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */
|
||||
CrystalCap = CrystalCap & 0x3F;
|
||||
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap|(CrystalCap << 6)));
|
||||
} else if (pDM_Odm->SupportICType & ODM_RTL8814A) {
|
||||
/* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap */
|
||||
CrystalCap = CrystalCap & 0x3F;
|
||||
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap|(CrystalCap << 6)));
|
||||
} else if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8821C)) {
|
||||
/* write 0x24[30:25] = 0x28[6:1] = CrystalCap */
|
||||
CrystalCap = CrystalCap & 0x3F;
|
||||
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7e000000, CrystalCap);
|
||||
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7e, CrystalCap);
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n"));
|
||||
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap|(CrystalCap << 6)));
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap));
|
||||
#endif
|
||||
}
|
||||
|
||||
u1Byte
|
||||
odm_GetDefaultCrytaltalCap(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte CrystalCap = 0x20;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
CrystalCap = pHalData->CrystalCap;
|
||||
#else
|
||||
prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
|
||||
if(priv->pmib->dot11RFEntry.xcap > 0)
|
||||
CrystalCap = priv->pmib->dot11RFEntry.xcap;
|
||||
#endif
|
||||
|
||||
CrystalCap = CrystalCap & 0x3f;
|
||||
|
||||
return CrystalCap;
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_SetATCStatus(
|
||||
IN PVOID pDM_VOID,
|
||||
IN BOOLEAN ATCStatus
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
|
||||
|
||||
if(pCfoTrack->bATCStatus == ATCStatus)
|
||||
return;
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus);
|
||||
pCfoTrack->bATCStatus = ATCStatus;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
odm_GetATCStatus(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
BOOLEAN ATCStatus;
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm));
|
||||
return ATCStatus;
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_CfoTrackingReset(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
|
||||
|
||||
pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
|
||||
pCfoTrack->bAdjust = TRUE;
|
||||
|
||||
if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap)
|
||||
{
|
||||
odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap - 1);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD,
|
||||
("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap));
|
||||
} else if (pCfoTrack->CrystalCap < pCfoTrack->DefXCap)
|
||||
{
|
||||
odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap + 1);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD,
|
||||
("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap));
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
odm_SetATCStatus(pDM_Odm, TRUE);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_CfoTrackingInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
|
||||
|
||||
pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
|
||||
pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm);
|
||||
pCfoTrack->bAdjust = TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========>\n"));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x\n", pCfoTrack->bATCStatus, pCfoTrack->DefXCap));
|
||||
|
||||
#if RTL8822B_SUPPORT
|
||||
/* Crystal cap. control by WiFi */
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8822B)
|
||||
ODM_SetBBReg(pDM_Odm, 0x10, 0x40, 0x1);
|
||||
#endif
|
||||
|
||||
#if RTL8821C_SUPPORT
|
||||
/* Crystal cap. control by WiFi */
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8821C)
|
||||
ODM_SetBBReg(pDM_Odm, 0x10, 0x40, 0x1);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_CfoTracking(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
|
||||
s4Byte CFO_ave = 0;
|
||||
u4Byte CFO_rpt_sum, CFO_kHz_avg[4] = {0};
|
||||
s4Byte CFO_ave_diff;
|
||||
s1Byte CrystalCap = pCfoTrack->CrystalCap;
|
||||
u1Byte Adjust_Xtal = 1, i, valid_path_cnt = 0;
|
||||
|
||||
//4 Support ability
|
||||
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n"));
|
||||
|
||||
if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly)
|
||||
{
|
||||
//4 No link or more than one entry
|
||||
ODM_CfoTrackingReset(pDM_Odm);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n",
|
||||
pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly));
|
||||
}
|
||||
else
|
||||
{
|
||||
//3 1. CFO Tracking
|
||||
//4 1.1 No new packet
|
||||
if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n"));
|
||||
return;
|
||||
}
|
||||
pCfoTrack->packetCount_pre = pCfoTrack->packetCount;
|
||||
|
||||
//4 1.2 Calculate CFO
|
||||
for (i = 0; i < pDM_Odm->num_rf_path; i++) {
|
||||
|
||||
if (pCfoTrack->CFO_cnt[i] == 0)
|
||||
continue;
|
||||
|
||||
valid_path_cnt++;
|
||||
CFO_rpt_sum = (u4Byte)((pCfoTrack->CFO_tail[i] < 0) ? (0 - pCfoTrack->CFO_tail[i]) : pCfoTrack->CFO_tail[i]);
|
||||
CFO_kHz_avg[i] = CFO_HW_RPT_2_MHZ(CFO_rpt_sum) / pCfoTrack->CFO_cnt[i];
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[Path %d] CFO_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n",
|
||||
i, CFO_rpt_sum, pCfoTrack->CFO_cnt[i],((pCfoTrack->CFO_tail[i] < 0) ? "-" : " ") ,CFO_kHz_avg[i]));
|
||||
}
|
||||
|
||||
for (i = 0; i < valid_path_cnt; i++) {
|
||||
|
||||
//ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("path [%d], pCfoTrack->CFO_tail = %d\n", i, pCfoTrack->CFO_tail[i]));
|
||||
if (pCfoTrack->CFO_tail[i] < 0) {
|
||||
CFO_ave += (0-(s4Byte)CFO_kHz_avg[i]);
|
||||
//ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("CFO_ave = %d\n", CFO_ave));
|
||||
}
|
||||
else
|
||||
CFO_ave += (s4Byte)CFO_kHz_avg[i];
|
||||
}
|
||||
|
||||
if (valid_path_cnt >= 2)
|
||||
CFO_ave = CFO_ave / valid_path_cnt;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("valid_path_cnt = ((%d)), CFO_ave = ((%d kHz))\n", valid_path_cnt, CFO_ave));
|
||||
|
||||
/*reset counter*/
|
||||
for (i = 0; i < pDM_Odm->num_rf_path; i++) {
|
||||
pCfoTrack->CFO_tail[i] = 0;
|
||||
pCfoTrack->CFO_cnt[i] = 0;
|
||||
}
|
||||
|
||||
//4 1.3 Avoid abnormal large CFO
|
||||
CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre);
|
||||
if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n"));
|
||||
pCfoTrack->largeCFOHit = 1;
|
||||
return;
|
||||
}
|
||||
else
|
||||
pCfoTrack->largeCFOHit = 0;
|
||||
pCfoTrack->CFO_ave_pre = CFO_ave;
|
||||
|
||||
//4 1.4 Dynamic Xtal threshold
|
||||
if(pCfoTrack->bAdjust == FALSE)
|
||||
{
|
||||
if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH))
|
||||
pCfoTrack->bAdjust = TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW))
|
||||
pCfoTrack->bAdjust = FALSE;
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
//4 1.5 BT case: Disable CFO tracking
|
||||
if(pDM_Odm->bBtEnabled)
|
||||
{
|
||||
pCfoTrack->bAdjust = FALSE;
|
||||
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n"));
|
||||
}
|
||||
/*
|
||||
//4 1.6 Big jump
|
||||
if(pCfoTrack->bAdjust)
|
||||
{
|
||||
if(CFO_ave > CFO_TH_XTAL_LOW)
|
||||
Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2);
|
||||
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
|
||||
Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal));
|
||||
}
|
||||
*/
|
||||
#endif
|
||||
|
||||
//4 1.7 Adjust Crystal Cap.
|
||||
if(pCfoTrack->bAdjust)
|
||||
{
|
||||
if(CFO_ave > CFO_TH_XTAL_LOW)
|
||||
CrystalCap = CrystalCap + Adjust_Xtal;
|
||||
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
|
||||
CrystalCap = CrystalCap - Adjust_Xtal;
|
||||
|
||||
if(CrystalCap > 0x3f)
|
||||
CrystalCap = 0x3f;
|
||||
else if (CrystalCap < 0)
|
||||
CrystalCap = 0;
|
||||
|
||||
odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap);
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
|
||||
pCfoTrack->CrystalCap, pCfoTrack->DefXCap));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
|
||||
return;
|
||||
|
||||
//3 2. Dynamic ATC switch
|
||||
if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC)
|
||||
{
|
||||
odm_SetATCStatus(pDM_Odm, FALSE);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n"));
|
||||
}
|
||||
else
|
||||
{
|
||||
odm_SetATCStatus(pDM_Odm, TRUE);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n"));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_ParsingCFO(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PVOID pPktinfo_VOID,
|
||||
IN s1Byte* pcfotail,
|
||||
IN u1Byte num_ss
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID;
|
||||
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
|
||||
u1Byte i;
|
||||
|
||||
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
|
||||
return;
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
if(pPktinfo->bPacketMatchBSSID)
|
||||
#else
|
||||
if(pPktinfo->StationID != 0)
|
||||
#endif
|
||||
{
|
||||
if (num_ss > pDM_Odm->num_rf_path) /*For fool proof*/
|
||||
num_ss = pDM_Odm->num_rf_path;
|
||||
|
||||
/*ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("num_ss = ((%d)), pDM_Odm->num_rf_path = ((%d))\n", num_ss, pDM_Odm->num_rf_path));*/
|
||||
|
||||
|
||||
//3 Update CFO report for path-A & path-B
|
||||
// Only paht-A and path-B have CFO tail and short CFO
|
||||
for(i = 0; i < num_ss; i++)
|
||||
{
|
||||
pCfoTrack->CFO_tail[i] += pcfotail[i];
|
||||
pCfoTrack->CFO_cnt[i] ++;
|
||||
/*ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[ID %d][path %d][Rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n",
|
||||
pPktinfo->StationID, i, pPktinfo->DataRate, pcfotail[i], pCfoTrack->CFO_tail[i], pCfoTrack->CFO_cnt[i]));
|
||||
*/
|
||||
}
|
||||
|
||||
//3 Update packet counter
|
||||
if(pCfoTrack->packetCount == 0xffffffff)
|
||||
pCfoTrack->packetCount = 0;
|
||||
else
|
||||
pCfoTrack->packetCount++;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMCFOTRACK_H__
|
||||
#define __PHYDMCFOTRACK_H__
|
||||
|
||||
#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/
|
||||
|
||||
#define CFO_TH_XTAL_HIGH 20 // kHz
|
||||
#define CFO_TH_XTAL_LOW 10 // kHz
|
||||
#define CFO_TH_ATC 80 // kHz
|
||||
|
||||
typedef struct _CFO_TRACKING_
|
||||
{
|
||||
BOOLEAN bATCStatus;
|
||||
BOOLEAN largeCFOHit;
|
||||
BOOLEAN bAdjust;
|
||||
u1Byte CrystalCap;
|
||||
u1Byte DefXCap;
|
||||
s4Byte CFO_tail[4];
|
||||
u4Byte CFO_cnt[4];
|
||||
s4Byte CFO_ave_pre;
|
||||
u4Byte packetCount;
|
||||
u4Byte packetCount_pre;
|
||||
|
||||
BOOLEAN bForceXtalCap;
|
||||
BOOLEAN bReset;
|
||||
}CFO_TRACKING, *PCFO_TRACKING;
|
||||
|
||||
VOID
|
||||
ODM_CfoTrackingReset(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_CfoTrackingInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_CfoTracking(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_ParsingCFO(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PVOID pPktinfo_VOID,
|
||||
IN s1Byte* pcfotail,
|
||||
IN u1Byte num_ss
|
||||
);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,357 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __ODM_DBG_H__
|
||||
#define __ODM_DBG_H__
|
||||
|
||||
/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
|
||||
/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
|
||||
#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/
|
||||
//-----------------------------------------------------------------------------
|
||||
// Define the debug levels
|
||||
//
|
||||
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
|
||||
// So that, they can help SW engineer to develope or trace states changed
|
||||
// and also help HW enginner to trace every operation to and from HW,
|
||||
// e.g IO, Tx, Rx.
|
||||
//
|
||||
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
|
||||
// which help us to debug SW or HW.
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Never used in a call to ODM_RT_TRACE()!
|
||||
//
|
||||
#define ODM_DBG_OFF 1
|
||||
|
||||
//
|
||||
// Fatal bug.
|
||||
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
|
||||
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
|
||||
//
|
||||
#define ODM_DBG_SERIOUS 2
|
||||
|
||||
//
|
||||
// Abnormal, rare, or unexpeted cases.
|
||||
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
|
||||
//
|
||||
#define ODM_DBG_WARNING 3
|
||||
|
||||
//
|
||||
// Normal case with useful information about current SW or HW state.
|
||||
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
|
||||
// SW protocol state change, dynamic mechanism state change and so on.
|
||||
//
|
||||
#define ODM_DBG_LOUD 4
|
||||
|
||||
//
|
||||
// Normal case with detail execution flow or information.
|
||||
//
|
||||
#define ODM_DBG_TRACE 5
|
||||
|
||||
/*FW DBG MSG*/
|
||||
#define RATE_DECISION BIT0
|
||||
#define INIT_RA_TABLE BIT1
|
||||
#define RATE_UP BIT2
|
||||
#define RATE_DOWN BIT3
|
||||
#define TRY_DONE BIT4
|
||||
#define RA_H2C BIT5
|
||||
#define F_RATE_AP_RPT BIT7
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Define the tracing components
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
/*BB FW Functions*/
|
||||
#define PHYDM_FW_COMP_RA BIT0
|
||||
#define PHYDM_FW_COMP_MU BIT1
|
||||
#define PHYDM_FW_COMP_PATH_DIV BIT2
|
||||
#define PHYDM_FW_COMP_PHY_CONFIG BIT3
|
||||
|
||||
|
||||
/*BB Driver Functions*/
|
||||
#define ODM_COMP_DIG BIT0
|
||||
#define ODM_COMP_RA_MASK BIT1
|
||||
#define ODM_COMP_DYNAMIC_TXPWR BIT2
|
||||
#define ODM_COMP_FA_CNT BIT3
|
||||
#define ODM_COMP_RSSI_MONITOR BIT4
|
||||
#define ODM_COMP_SNIFFER BIT5
|
||||
#define ODM_COMP_ANT_DIV BIT6
|
||||
#define ODM_COMP_DFS BIT7
|
||||
#define ODM_COMP_NOISY_DETECT BIT8
|
||||
#define ODM_COMP_RATE_ADAPTIVE BIT9
|
||||
#define ODM_COMP_PATH_DIV BIT10
|
||||
#define ODM_COMP_CCX BIT11
|
||||
|
||||
#define ODM_COMP_DYNAMIC_PRICCA BIT12
|
||||
/*BIT13 TBD*/
|
||||
#define ODM_COMP_MP BIT14
|
||||
#define ODM_COMP_CFO_TRACKING BIT15
|
||||
#define ODM_COMP_ACS BIT16
|
||||
#define PHYDM_COMP_ADAPTIVITY BIT17
|
||||
#define PHYDM_COMP_RA_DBG BIT18
|
||||
#define PHYDM_COMP_TXBF BIT19
|
||||
//MAC Functions
|
||||
#define ODM_COMP_EDCA_TURBO BIT20
|
||||
/*BIT21 TBD*/
|
||||
#define ODM_FW_DEBUG_TRACE BIT22
|
||||
//RF Functions
|
||||
/*BIT23 TBD*/
|
||||
#define ODM_COMP_TX_PWR_TRACK BIT24
|
||||
/*BIT25 TBD*/
|
||||
#define ODM_COMP_CALIBRATION BIT26
|
||||
//Common Functions
|
||||
/*BIT27 TBD*/
|
||||
#define ODM_PHY_CONFIG BIT28
|
||||
#define ODM_COMP_INIT BIT29
|
||||
#define ODM_COMP_COMMON BIT30
|
||||
#define ODM_COMP_API BIT31
|
||||
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define RT_PRINTK DbgPrint
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define DbgPrint printk
|
||||
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
|
||||
#define RT_DISP(dbgtype, dbgflag, printstr)
|
||||
#else
|
||||
#define DbgPrint panic_printk
|
||||
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
|
||||
#endif
|
||||
|
||||
#ifndef ASSERT
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
#if DBG
|
||||
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
|
||||
do { \
|
||||
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \
|
||||
{ \
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E) \
|
||||
DbgPrint("[PhyDM-8188E] "); \
|
||||
else if(pDM_Odm->SupportICType == ODM_RTL8192E) \
|
||||
DbgPrint("[PhyDM-8192E] "); \
|
||||
else if(pDM_Odm->SupportICType == ODM_RTL8812) \
|
||||
DbgPrint("[PhyDM-8812A] "); \
|
||||
else if(pDM_Odm->SupportICType == ODM_RTL8821) \
|
||||
DbgPrint("[PhyDM-8821A] "); \
|
||||
else if(pDM_Odm->SupportICType == ODM_RTL8814A) \
|
||||
DbgPrint("[PhyDM-8814A] "); \
|
||||
else if(pDM_Odm->SupportICType == ODM_RTL8703B) \
|
||||
DbgPrint("[PhyDM-8703B] "); \
|
||||
else if(pDM_Odm->SupportICType == ODM_RTL8822B) \
|
||||
DbgPrint("[PhyDM-8822B] "); \
|
||||
else if (pDM_Odm->SupportICType == ODM_RTL8188F) \
|
||||
DbgPrint("[PhyDM-8188F] "); \
|
||||
RT_PRINTK fmt; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
|
||||
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
|
||||
{ \
|
||||
RT_PRINTK fmt; \
|
||||
}
|
||||
|
||||
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
|
||||
if(!(expr)) { \
|
||||
DbgPrint( "Assertion failed! %s at ......\n", #expr); \
|
||||
DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
|
||||
RT_PRINTK fmt; \
|
||||
ASSERT(FALSE); \
|
||||
}
|
||||
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); }
|
||||
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); }
|
||||
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); }
|
||||
|
||||
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
|
||||
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
|
||||
{ \
|
||||
int __i; \
|
||||
pu1Byte __ptr = (pu1Byte)ptr; \
|
||||
DbgPrint("[ODM] "); \
|
||||
DbgPrint(title_str); \
|
||||
DbgPrint(" "); \
|
||||
for( __i=0; __i<6; __i++ ) \
|
||||
DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \
|
||||
DbgPrint("\n"); \
|
||||
}
|
||||
#else
|
||||
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
|
||||
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
|
||||
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
|
||||
#define ODM_dbg_enter()
|
||||
#define ODM_dbg_exit()
|
||||
#define ODM_dbg_trace(str)
|
||||
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
|
||||
#endif
|
||||
|
||||
|
||||
VOID
|
||||
PHYDM_InitDebugSetting(IN PDM_ODM_T pDM_Odm);
|
||||
|
||||
VOID phydm_BasicDbgMessage( IN PVOID pDM_VOID);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define PHYDM_DBGPRINT 0
|
||||
#define PHYDM_SSCANF(x, y, z) DCMD_Scanf(x, y, z)
|
||||
#define PHYDM_VAST_INFO_SNPRINTF PHYDM_SNPRINTF
|
||||
#if (PHYDM_DBGPRINT == 1)
|
||||
#define PHYDM_SNPRINTF(msg) \
|
||||
do {\
|
||||
rsprintf msg;\
|
||||
DbgPrint(output);\
|
||||
} while (0)
|
||||
#else
|
||||
#define PHYDM_SNPRINTF(msg) \
|
||||
do {\
|
||||
rsprintf msg;\
|
||||
DCMD_Printf(output);\
|
||||
} while (0)
|
||||
#endif
|
||||
#else
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)
|
||||
#define PHYDM_DBGPRINT 0
|
||||
#else
|
||||
#define PHYDM_DBGPRINT 1
|
||||
#endif
|
||||
#define MAX_ARGC 20
|
||||
#define MAX_ARGV 16
|
||||
#define DCMD_DECIMAL "%d"
|
||||
#define DCMD_CHAR "%c"
|
||||
#define DCMD_HEX "%x"
|
||||
|
||||
#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z)
|
||||
|
||||
#define PHYDM_VAST_INFO_SNPRINTF(msg)\
|
||||
do {\
|
||||
snprintf msg;\
|
||||
DbgPrint(output);\
|
||||
} while (0)
|
||||
|
||||
#if (PHYDM_DBGPRINT == 1)
|
||||
#define PHYDM_SNPRINTF(msg)\
|
||||
do {\
|
||||
snprintf msg;\
|
||||
DbgPrint(output);\
|
||||
} while (0)
|
||||
#else
|
||||
#define PHYDM_SNPRINTF(msg)\
|
||||
do {\
|
||||
if(out_len > used)\
|
||||
used+=snprintf msg;\
|
||||
} while (0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
VOID phydm_BasicProfile(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *_used,
|
||||
OUT char *output,
|
||||
IN u4Byte *_out_len
|
||||
);
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))
|
||||
s4Byte
|
||||
phydm_cmd(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN char *input,
|
||||
IN u4Byte in_len,
|
||||
IN u1Byte flag,
|
||||
OUT char *output,
|
||||
IN u4Byte out_len
|
||||
);
|
||||
#endif
|
||||
VOID
|
||||
phydm_cmd_parser(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN char input[][16],
|
||||
IN u4Byte input_num,
|
||||
IN u1Byte flag,
|
||||
OUT char *output,
|
||||
IN u4Byte out_len
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_la_mode_bb_setting(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte DbgPort,
|
||||
IN BOOLEAN bTriggerEdge,
|
||||
IN u1Byte sampling_rate
|
||||
);
|
||||
|
||||
u1Byte
|
||||
phydm_la_mode_mac_setting(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte TriggerTime_mu_sec
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void phydm_sbd_check(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
void phydm_sbd_callback(
|
||||
PRT_TIMER pTimer
|
||||
);
|
||||
|
||||
void phydm_sbd_workitem_callback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
#endif
|
||||
|
||||
VOID
|
||||
phydm_fw_trace_en_h2c(
|
||||
IN PVOID pDM_VOID,
|
||||
IN BOOLEAN enable,
|
||||
IN u4Byte fw_debug_component,
|
||||
IN u4Byte monitor_mode,
|
||||
IN u4Byte macid
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_fw_trace_handler(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte CmdBuf,
|
||||
IN u1Byte CmdLen
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_fw_trace_handler_code(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte Buffer,
|
||||
IN u1Byte CmdLen
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_fw_trace_handler_8051(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte CmdBuf,
|
||||
IN u1Byte CmdLen
|
||||
);
|
||||
|
||||
#endif // __ODM_DBG_H__
|
||||
|
||||
@@ -0,0 +1,258 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
============================================================
|
||||
include files
|
||||
============================================================
|
||||
*/
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if defined(CONFIG_PHYDM_DFS_MASTER)
|
||||
VOID phydm_radar_detect_reset(PVOID pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0);
|
||||
ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 1);
|
||||
}
|
||||
|
||||
VOID phydm_radar_detect_disable(PVOID pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0);
|
||||
}
|
||||
|
||||
static VOID phydm_radar_detect_with_dbg_parm(PVOID pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, pDM_Odm->radar_detect_reg_918);
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, pDM_Odm->radar_detect_reg_91c);
|
||||
ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, pDM_Odm->radar_detect_reg_920);
|
||||
ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, pDM_Odm->radar_detect_reg_924);
|
||||
}
|
||||
|
||||
/* Init radar detection parameters, called after ch, bw is set */
|
||||
VOID phydm_radar_detect_enable(PVOID pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte region_domain = pDM_Odm->DFS_RegionDomain;
|
||||
u1Byte c_channel = *(pDM_Odm->pChannel);
|
||||
|
||||
if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10);
|
||||
ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06);
|
||||
|
||||
if (pDM_Odm->radar_detect_dbg_parm_en) {
|
||||
phydm_radar_detect_with_dbg_parm(pDM_Odm);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c17ecdf);
|
||||
ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x01528500);
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0fa21a20);
|
||||
ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0f69204);
|
||||
|
||||
} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x01528500);
|
||||
ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67234);
|
||||
|
||||
if (c_channel >= 52 && c_channel <= 64) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf);
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0f141a20);
|
||||
} else {
|
||||
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf);
|
||||
if (pDM_Odm->pBandWidth == ODM_BW20M)
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64721a20);
|
||||
else
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68721a20);
|
||||
}
|
||||
|
||||
} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf);
|
||||
ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x01528500);
|
||||
ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67231);
|
||||
if (pDM_Odm->pBandWidth == ODM_BW20M)
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64741a20);
|
||||
else
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68741a20);
|
||||
} else {
|
||||
/* not supported */
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain));
|
||||
}
|
||||
|
||||
} else if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) {
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10);
|
||||
ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06);
|
||||
|
||||
/* 8822B only, when BW = 20M, DFIR output is 40Mhz, but DFS input is 80MMHz, so it need to upgrade to 80MHz */
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8822B) {
|
||||
if (pDM_Odm->pBandWidth == ODM_BW20M)
|
||||
ODM_SetBBReg(pDM_Odm, 0x1984, BIT26, 1);
|
||||
else
|
||||
ODM_SetBBReg(pDM_Odm, 0x1984, BIT26, 0);
|
||||
}
|
||||
|
||||
if (pDM_Odm->radar_detect_dbg_parm_en) {
|
||||
phydm_radar_detect_with_dbg_parm(pDM_Odm);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf);
|
||||
ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x095a8500);
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0fa21a20);
|
||||
ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0f57204);
|
||||
|
||||
} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x095a8500);
|
||||
ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67234);
|
||||
|
||||
if (c_channel >= 52 && c_channel <= 64) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf);
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0f141a20);
|
||||
} else {
|
||||
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c166cdf);
|
||||
if (pDM_Odm->pBandWidth == ODM_BW20M)
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64721a20);
|
||||
else
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68721a20);
|
||||
}
|
||||
} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c166cdf);
|
||||
ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x095a8500);
|
||||
ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67231);
|
||||
if (pDM_Odm->pBandWidth == ODM_BW20M)
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64741a20);
|
||||
else
|
||||
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68741a20);
|
||||
} else {
|
||||
/* not supported */
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain));
|
||||
}
|
||||
} else {
|
||||
/* not supported IC type*/
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported IC Type:%d\n", pDM_Odm->SupportICType));
|
||||
}
|
||||
|
||||
exit:
|
||||
phydm_radar_detect_reset(pDM_Odm);
|
||||
}
|
||||
|
||||
BOOLEAN phydm_radar_detect(PVOID pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
BOOLEAN enable_DFS = FALSE;
|
||||
BOOLEAN radar_detected = FALSE;
|
||||
u1Byte region_domain = pDM_Odm->DFS_RegionDomain;
|
||||
|
||||
if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n"));
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (ODM_GetBBReg(pDM_Odm , 0x924, BIT15))
|
||||
enable_DFS = TRUE;
|
||||
|
||||
if ((ODM_GetBBReg(pDM_Odm , 0xf98, BIT17))
|
||||
|| (!(region_domain == PHYDM_DFS_DOMAIN_ETSI) && (ODM_GetBBReg(pDM_Odm , 0xf98, BIT19))))
|
||||
radar_detected = TRUE;
|
||||
|
||||
if (enable_DFS && radar_detected) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD
|
||||
, ("Radar detect: enable_DFS:%d, radar_detected:%d\n"
|
||||
, enable_DFS, radar_detected));
|
||||
|
||||
phydm_radar_detect_reset(pDM_Odm);
|
||||
}
|
||||
|
||||
exit:
|
||||
return (enable_DFS && radar_detected);
|
||||
}
|
||||
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
|
||||
|
||||
BOOLEAN
|
||||
phydm_dfs_master_enabled(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
#ifdef CONFIG_PHYDM_DFS_MASTER
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
return *pDM_Odm->dfs_master_enabled ? TRUE : FALSE;
|
||||
#else
|
||||
return FALSE;
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_dfs_debug(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *const argv,
|
||||
IN u4Byte *_used,
|
||||
OUT char *output,
|
||||
IN u4Byte *_out_len
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u4Byte used = *_used;
|
||||
u4Byte out_len = *_out_len;
|
||||
|
||||
switch (argv[0]) {
|
||||
case 1:
|
||||
#if defined(CONFIG_PHYDM_DFS_MASTER)
|
||||
/* set dbg parameters for radar detection instead of the default value */
|
||||
if (argv[1] == 1) {
|
||||
pDM_Odm->radar_detect_reg_918 = argv[2];
|
||||
pDM_Odm->radar_detect_reg_91c = argv[3];
|
||||
pDM_Odm->radar_detect_reg_920 = argv[4];
|
||||
pDM_Odm->radar_detect_reg_924 = argv[5];
|
||||
pDM_Odm->radar_detect_dbg_parm_en = 1;
|
||||
|
||||
PHYDM_SNPRINTF((output+used, out_len-used, "Radar detection with dbg parameter\n"));
|
||||
PHYDM_SNPRINTF((output+used, out_len-used, "reg918:0x%08X\n", pDM_Odm->radar_detect_reg_918));
|
||||
PHYDM_SNPRINTF((output+used, out_len-used, "reg91c:0x%08X\n", pDM_Odm->radar_detect_reg_91c));
|
||||
PHYDM_SNPRINTF((output+used, out_len-used, "reg920:0x%08X\n", pDM_Odm->radar_detect_reg_920));
|
||||
PHYDM_SNPRINTF((output+used, out_len-used, "reg924:0x%08X\n", pDM_Odm->radar_detect_reg_924));
|
||||
} else {
|
||||
pDM_Odm->radar_detect_dbg_parm_en = 0;
|
||||
PHYDM_SNPRINTF((output+used, out_len-used, "Radar detection with default parameter\n"));
|
||||
}
|
||||
phydm_radar_detect_enable(pDM_Odm);
|
||||
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,76 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDM_DFS_H__
|
||||
#define __PHYDM_DFS_H__
|
||||
|
||||
#define DFS_VERSION "0.0"
|
||||
|
||||
/* ============================================================
|
||||
Definition
|
||||
============================================================
|
||||
*/
|
||||
|
||||
/*
|
||||
============================================================
|
||||
1 structure
|
||||
============================================================
|
||||
*/
|
||||
|
||||
/* ============================================================
|
||||
enumeration
|
||||
============================================================
|
||||
*/
|
||||
|
||||
typedef enum _tag_PhyDM_DFS_REGION_DOMAIN {
|
||||
PHYDM_DFS_DOMAIN_UNKNOWN = 0,
|
||||
PHYDM_DFS_DOMAIN_FCC = 1,
|
||||
PHYDM_DFS_DOMAIN_MKK = 2,
|
||||
PHYDM_DFS_DOMAIN_ETSI = 3,
|
||||
} PHYDM_DFS_REGION_DOMAIN;
|
||||
|
||||
/*
|
||||
============================================================
|
||||
function prototype
|
||||
============================================================
|
||||
*/
|
||||
#if defined(CONFIG_PHYDM_DFS_MASTER)
|
||||
VOID phydm_radar_detect_reset(PVOID pDM_VOID);
|
||||
VOID phydm_radar_detect_disable(PVOID pDM_VOID);
|
||||
VOID phydm_radar_detect_enable(PVOID pDM_VOID);
|
||||
BOOLEAN phydm_radar_detect(PVOID pDM_VOID);
|
||||
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
|
||||
|
||||
BOOLEAN
|
||||
phydm_dfs_master_enabled(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_dfs_debug(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *const argv,
|
||||
IN u4Byte *_used,
|
||||
OUT char *output,
|
||||
IN u4Byte *_out_len
|
||||
);
|
||||
|
||||
#endif /*#ifndef __PHYDM_DFS_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,370 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMDIG_H__
|
||||
#define __PHYDMDIG_H__
|
||||
|
||||
#define DIG_VERSION "1.24" /* 2016.06.01 Stanley. Modify IGI setting for 1R-CCA path-B */
|
||||
|
||||
/* Pause DIG & CCKPD */
|
||||
#define DM_DIG_MAX_PAUSE_TYPE 0x7
|
||||
|
||||
typedef enum tag_DIG_GoUpCheck_Level {
|
||||
|
||||
DIG_GOUPCHECK_LEVEL_0,
|
||||
DIG_GOUPCHECK_LEVEL_1,
|
||||
DIG_GOUPCHECK_LEVEL_2
|
||||
|
||||
} DIG_GOUPCHECK_LEVEL;
|
||||
|
||||
typedef struct _Dynamic_Initial_Gain_Threshold_
|
||||
{
|
||||
BOOLEAN bStopDIG; // for debug
|
||||
BOOLEAN bIgnoreDIG;
|
||||
BOOLEAN bPSDInProgress;
|
||||
|
||||
u1Byte Dig_Enable_Flag;
|
||||
u1Byte Dig_Ext_Port_Stage;
|
||||
|
||||
int RssiLowThresh;
|
||||
int RssiHighThresh;
|
||||
|
||||
u4Byte FALowThresh;
|
||||
u4Byte FAHighThresh;
|
||||
|
||||
u1Byte CurSTAConnectState;
|
||||
u1Byte PreSTAConnectState;
|
||||
u1Byte CurMultiSTAConnectState;
|
||||
|
||||
u1Byte PreIGValue;
|
||||
u1Byte CurIGValue;
|
||||
u1Byte BackupIGValue; //MP DIG
|
||||
u1Byte BT30_CurIGI;
|
||||
u1Byte IGIBackup;
|
||||
|
||||
s1Byte BackoffVal;
|
||||
s1Byte BackoffVal_range_max;
|
||||
s1Byte BackoffVal_range_min;
|
||||
u1Byte rx_gain_range_max;
|
||||
u1Byte rx_gain_range_min;
|
||||
u1Byte Rssi_val_min;
|
||||
|
||||
u1Byte PreCCK_CCAThres;
|
||||
u1Byte CurCCK_CCAThres;
|
||||
u1Byte PreCCKPDState;
|
||||
u1Byte CurCCKPDState;
|
||||
u1Byte CCKPDBackup;
|
||||
u1Byte pause_cckpd_level;
|
||||
u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
|
||||
|
||||
u1Byte LargeFAHit;
|
||||
u1Byte LargeFA_Timeout; /*if (LargeFAHit), monitor "LargeFA_Timeout" sec, if timeout, LargeFAHit=0*/
|
||||
u1Byte ForbiddenIGI;
|
||||
u4Byte Recover_cnt;
|
||||
|
||||
u1Byte DIG_Dynamic_MIN_0;
|
||||
u1Byte DIG_Dynamic_MIN_1;
|
||||
BOOLEAN bMediaConnect_0;
|
||||
BOOLEAN bMediaConnect_1;
|
||||
|
||||
u4Byte AntDiv_RSSI_max;
|
||||
u4Byte RSSI_max;
|
||||
|
||||
u1Byte *bP2PInProcess;
|
||||
|
||||
u1Byte pause_dig_level;
|
||||
u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
|
||||
|
||||
u4Byte cckFaMa;
|
||||
DIG_GOUPCHECK_LEVEL DIG_GoUpCheck_Level;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
BOOLEAN bTpTarget;
|
||||
BOOLEAN bNoiseEst;
|
||||
u4Byte TpTrainTH_min;
|
||||
u1Byte IGIOffset_A;
|
||||
u1Byte IGIOffset_B;
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
|
||||
u1Byte rfGainIdx;
|
||||
u1Byte agcTableIdx;
|
||||
u1Byte bigJumpLmt[16];
|
||||
u1Byte enableAdjustBigJump:1;
|
||||
u1Byte bigJumpStep1:3;
|
||||
u1Byte bigJumpStep2:2;
|
||||
u1Byte bigJumpStep3:2;
|
||||
#endif
|
||||
}DIG_T,*pDIG_T;
|
||||
|
||||
typedef struct _FALSE_ALARM_STATISTICS{
|
||||
u4Byte Cnt_Parity_Fail;
|
||||
u4Byte Cnt_Rate_Illegal;
|
||||
u4Byte Cnt_Crc8_fail;
|
||||
u4Byte Cnt_Mcs_fail;
|
||||
u4Byte Cnt_Ofdm_fail;
|
||||
u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A
|
||||
u4Byte Cnt_Cck_fail;
|
||||
u4Byte Cnt_all;
|
||||
u4Byte Cnt_all_pre;
|
||||
u4Byte Cnt_Fast_Fsync;
|
||||
u4Byte Cnt_SB_Search_fail;
|
||||
u4Byte Cnt_OFDM_CCA;
|
||||
u4Byte Cnt_CCK_CCA;
|
||||
u4Byte Cnt_CCA_all;
|
||||
u4Byte Cnt_BW_USC; //Gary
|
||||
u4Byte Cnt_BW_LSC; //Gary
|
||||
u4Byte cnt_cck_crc32_error;
|
||||
u4Byte cnt_cck_crc32_ok;
|
||||
u4Byte cnt_ofdm_crc32_error;
|
||||
u4Byte cnt_ofdm_crc32_ok;
|
||||
u4Byte cnt_ht_crc32_error;
|
||||
u4Byte cnt_ht_crc32_ok;
|
||||
u4Byte cnt_vht_crc32_error;
|
||||
u4Byte cnt_vht_crc32_ok;
|
||||
u4Byte cnt_crc32_error_all;
|
||||
u4Byte cnt_crc32_ok_all;
|
||||
BOOLEAN cck_block_enable;
|
||||
BOOLEAN ofdm_block_enable;
|
||||
u4Byte dbg_port0;
|
||||
BOOLEAN edcca_flag;
|
||||
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
|
||||
|
||||
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
|
||||
{
|
||||
DIG_TYPE_THRESH_HIGH = 0,
|
||||
DIG_TYPE_THRESH_LOW = 1,
|
||||
DIG_TYPE_BACKOFF = 2,
|
||||
DIG_TYPE_RX_GAIN_MIN = 3,
|
||||
DIG_TYPE_RX_GAIN_MAX = 4,
|
||||
DIG_TYPE_ENABLE = 5,
|
||||
DIG_TYPE_DISABLE = 6,
|
||||
DIG_OP_TYPE_MAX
|
||||
}DM_DIG_OP_E;
|
||||
|
||||
/*
|
||||
typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
|
||||
{
|
||||
CCK_PD_STAGE_LowRssi = 0,
|
||||
CCK_PD_STAGE_HighRssi = 1,
|
||||
CCK_PD_STAGE_MAX = 3,
|
||||
}DM_CCK_PDTH_E;
|
||||
|
||||
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
|
||||
{
|
||||
DIG_EXT_PORT_STAGE_0 = 0,
|
||||
DIG_EXT_PORT_STAGE_1 = 1,
|
||||
DIG_EXT_PORT_STAGE_2 = 2,
|
||||
DIG_EXT_PORT_STAGE_3 = 3,
|
||||
DIG_EXT_PORT_STAGE_MAX = 4,
|
||||
}DM_DIG_EXT_PORT_ALG_E;
|
||||
|
||||
typedef enum tag_DIG_Connect_Definition
|
||||
{
|
||||
DIG_STA_DISCONNECT = 0,
|
||||
DIG_STA_CONNECT = 1,
|
||||
DIG_STA_BEFORE_CONNECT = 2,
|
||||
DIG_MultiSTA_DISCONNECT = 3,
|
||||
DIG_MultiSTA_CONNECT = 4,
|
||||
DIG_CONNECT_MAX
|
||||
}DM_DIG_CONNECT_E;
|
||||
|
||||
|
||||
#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
|
||||
|
||||
#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \
|
||||
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)
|
||||
|
||||
#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \
|
||||
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)
|
||||
*/
|
||||
|
||||
typedef enum tag_PHYDM_Pause_Type {
|
||||
PHYDM_PAUSE = BIT0,
|
||||
PHYDM_RESUME = BIT1
|
||||
} PHYDM_PAUSE_TYPE;
|
||||
|
||||
typedef enum tag_PHYDM_Pause_Level {
|
||||
/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
|
||||
PHYDM_PAUSE_LEVEL_0 = 0,
|
||||
PHYDM_PAUSE_LEVEL_1 = 1,
|
||||
PHYDM_PAUSE_LEVEL_2 = 2,
|
||||
PHYDM_PAUSE_LEVEL_3 = 3,
|
||||
PHYDM_PAUSE_LEVEL_4 = 4,
|
||||
PHYDM_PAUSE_LEVEL_5 = 5,
|
||||
PHYDM_PAUSE_LEVEL_6 = 6,
|
||||
PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */
|
||||
} PHYDM_PAUSE_LEVEL;
|
||||
|
||||
#define DM_DIG_THRESH_HIGH 40
|
||||
#define DM_DIG_THRESH_LOW 35
|
||||
|
||||
#define DM_FALSEALARM_THRESH_LOW 400
|
||||
#define DM_FALSEALARM_THRESH_HIGH 1000
|
||||
|
||||
#define DM_DIG_MAX_NIC 0x3e
|
||||
#define DM_DIG_MIN_NIC 0x20
|
||||
#define DM_DIG_MAX_OF_MIN_NIC 0x3e
|
||||
|
||||
#define DM_DIG_MAX_AP 0x3e
|
||||
#define DM_DIG_MIN_AP 0x20
|
||||
#define DM_DIG_MAX_OF_MIN 0x2A //0x32
|
||||
#define DM_DIG_MIN_AP_DFS 0x20
|
||||
|
||||
#define DM_DIG_MAX_NIC_HP 0x46
|
||||
#define DM_DIG_MIN_NIC_HP 0x2e
|
||||
|
||||
#define DM_DIG_MAX_AP_HP 0x42
|
||||
#define DM_DIG_MIN_AP_HP 0x30
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#define DM_DIG_MAX_AP_COVERAGR 0x26
|
||||
#define DM_DIG_MIN_AP_COVERAGE 0x1c
|
||||
#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22
|
||||
|
||||
#define DM_DIG_TP_Target_TH0 500
|
||||
#define DM_DIG_TP_Target_TH1 1000
|
||||
#define DM_DIG_TP_Training_Period 10
|
||||
#endif
|
||||
|
||||
//vivi 92c&92d has different definition, 20110504
|
||||
//this is for 92c
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
|
||||
#define DM_DIG_FA_TH0 0x80//0x20
|
||||
#else
|
||||
#define DM_DIG_FA_TH0 0x200//0x20
|
||||
#endif
|
||||
#else
|
||||
#define DM_DIG_FA_TH0 0x200//0x20
|
||||
#endif
|
||||
|
||||
#define DM_DIG_FA_TH1 0x300
|
||||
#define DM_DIG_FA_TH2 0x400
|
||||
//this is for 92d
|
||||
#define DM_DIG_FA_TH0_92D 0x100
|
||||
#define DM_DIG_FA_TH1_92D 0x400
|
||||
#define DM_DIG_FA_TH2_92D 0x600
|
||||
|
||||
#define DM_DIG_BACKOFF_MAX 12
|
||||
#define DM_DIG_BACKOFF_MIN -4
|
||||
#define DM_DIG_BACKOFF_DEFAULT 10
|
||||
|
||||
#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps
|
||||
#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps
|
||||
#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps
|
||||
#define RSSI_OFFSET_DIG 0x05
|
||||
#define LARGE_FA_TIMEOUT 60
|
||||
|
||||
|
||||
VOID
|
||||
ODM_ChangeDynamicInitGainThresh(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte DM_Type,
|
||||
IN u4Byte DM_Value
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_Write_DIG(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte CurrentIGI
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_PauseDIG(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PHYDM_PAUSE_TYPE PauseType,
|
||||
IN PHYDM_PAUSE_LEVEL pause_level,
|
||||
IN u1Byte IGIValue
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_DIGInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_DIG(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_DIGbyRSSI_LPS(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_FalseAlarmCounterStatistics(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_PauseCCKPacketDetection(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PHYDM_PAUSE_TYPE PauseType,
|
||||
IN PHYDM_PAUSE_LEVEL pause_level,
|
||||
IN u1Byte CCKPDThreshold
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_CCKPacketDetectionThresh(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_Write_CCK_CCA_Thres(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte CurCCK_CCAThres
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
phydm_DIG_GoUpCheck(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
odm_MPT_DIGCallback(
|
||||
PRT_TIMER pTimer
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_MPT_DIGWorkItemCallback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
VOID
|
||||
odm_MPT_DIGCallback(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
|
||||
VOID
|
||||
ODM_MPT_DIG(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,124 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (defined(CONFIG_BB_POWER_SAVING))
|
||||
|
||||
VOID
|
||||
odm_DynamicBBPowerSavingInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
|
||||
|
||||
pDM_PSTable->PreCCAState = CCA_MAX;
|
||||
pDM_PSTable->CurCCAState = CCA_MAX;
|
||||
pDM_PSTable->PreRFState = RF_MAX;
|
||||
pDM_PSTable->CurRFState = RF_MAX;
|
||||
pDM_PSTable->Rssi_val_min = 0;
|
||||
pDM_PSTable->initialize = 0;
|
||||
}
|
||||
|
||||
void
|
||||
ODM_RF_Saving(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte bForceInNormal
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
|
||||
u1Byte Rssi_Up_bound = 30 ;
|
||||
u1Byte Rssi_Low_bound = 25;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
|
||||
{
|
||||
Rssi_Up_bound = 50 ;
|
||||
Rssi_Low_bound = 45;
|
||||
}
|
||||
#endif
|
||||
if(pDM_PSTable->initialize == 0){
|
||||
|
||||
pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
|
||||
pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
|
||||
pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
|
||||
pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
|
||||
//Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
|
||||
pDM_PSTable->initialize = 1;
|
||||
}
|
||||
|
||||
if(!bForceInNormal)
|
||||
{
|
||||
if(pDM_Odm->RSSI_Min != 0xFF)
|
||||
{
|
||||
if(pDM_PSTable->PreRFState == RF_Normal)
|
||||
{
|
||||
if(pDM_Odm->RSSI_Min >= Rssi_Up_bound)
|
||||
pDM_PSTable->CurRFState = RF_Save;
|
||||
else
|
||||
pDM_PSTable->CurRFState = RF_Normal;
|
||||
}
|
||||
else{
|
||||
if(pDM_Odm->RSSI_Min <= Rssi_Low_bound)
|
||||
pDM_PSTable->CurRFState = RF_Normal;
|
||||
else
|
||||
pDM_PSTable->CurRFState = RF_Save;
|
||||
}
|
||||
}
|
||||
else
|
||||
pDM_PSTable->CurRFState=RF_MAX;
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_PSTable->CurRFState = RF_Normal;
|
||||
}
|
||||
|
||||
if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState)
|
||||
{
|
||||
if(pDM_PSTable->CurRFState == RF_Save)
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
|
||||
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0
|
||||
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
|
||||
ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10
|
||||
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
|
||||
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
|
||||
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874);
|
||||
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
|
||||
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
|
||||
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
|
||||
ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0);
|
||||
}
|
||||
pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,58 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__
|
||||
#define __PHYDMDYNAMICBBPOWERSAVING_H__
|
||||
|
||||
#define DYNAMIC_BBPWRSAV_VERSION "1.1"
|
||||
|
||||
#if (defined(CONFIG_BB_POWER_SAVING))
|
||||
|
||||
typedef struct _Dynamic_Power_Saving_
|
||||
{
|
||||
u1Byte PreCCAState;
|
||||
u1Byte CurCCAState;
|
||||
|
||||
u1Byte PreRFState;
|
||||
u1Byte CurRFState;
|
||||
|
||||
int Rssi_val_min;
|
||||
|
||||
u1Byte initialize;
|
||||
u4Byte Reg874,RegC70,Reg85C,RegA74;
|
||||
|
||||
}PS_T,*pPS_T;
|
||||
|
||||
#define dm_RF_Saving ODM_RF_Saving
|
||||
|
||||
void ODM_RF_Saving(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte bForceInNormal
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_DynamicBBPowerSavingInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
#else
|
||||
#define dm_RF_Saving(pDM_VOID, bForceInNormal)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,542 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
/*if (!IS_HARDWARE_TYPE_8814A(Adapter)) {*/
|
||||
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */
|
||||
/* ("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable));*/
|
||||
/* return;*/
|
||||
/*} else*/
|
||||
{
|
||||
pMgntInfo->bDynamicTxPowerEnable = TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
||||
("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable));
|
||||
}
|
||||
|
||||
#if DEV_BUS_TYPE==RT_USB_INTERFACE
|
||||
if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power)
|
||||
{
|
||||
odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
|
||||
pMgntInfo->bDynamicTxPowerEnable = TRUE;
|
||||
}
|
||||
else
|
||||
#else
|
||||
//so 92c pci do not need dynamic tx power? vivi check it later
|
||||
pMgntInfo->bDynamicTxPowerEnable = FALSE;
|
||||
#endif
|
||||
|
||||
|
||||
pHalData->LastDTPLvl = TxHighPwrLevel_Normal;
|
||||
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
pDM_Odm->LastDTPLvl = TxHighPwrLevel_Normal;
|
||||
pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
|
||||
pDM_Odm->tx_agc_ofdm_18_6 = ODM_GetBBReg(pDM_Odm, 0xC24, bMaskDWord); /*TXAGC {18M 12M 9M 6M}*/
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerSavePowerIndex(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
|
||||
u1Byte index;
|
||||
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
for(index = 0; index< 6; index++)
|
||||
pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]);
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerRestorePowerIndex(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
|
||||
u1Byte index;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
for(index = 0; index< 6; index++)
|
||||
PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]);
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerWritePowerIndex(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Value)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte index;
|
||||
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
|
||||
for(index = 0; index< 6; index++)
|
||||
//PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
|
||||
ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerNIC_CE(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte val;
|
||||
u1Byte rssi_tmp = pDM_Odm->RSSI_Min;
|
||||
|
||||
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
|
||||
return;
|
||||
|
||||
if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
|
||||
pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
|
||||
/**/
|
||||
} else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) {
|
||||
pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
|
||||
/**/
|
||||
} else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) {
|
||||
pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
|
||||
/**/
|
||||
}
|
||||
|
||||
if (pDM_Odm->LastDTPLvl != pDM_Odm->DynamicTxHighPowerLvl) {
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", pDM_Odm->LastDTPLvl, pDM_Odm->DynamicTxHighPowerLvl));
|
||||
|
||||
pDM_Odm->LastDTPLvl = pDM_Odm->DynamicTxHighPowerLvl;
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8821)) {
|
||||
|
||||
if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
|
||||
|
||||
ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/
|
||||
|
||||
val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff;
|
||||
if (val >= 0x20)
|
||||
val -= 0x16;
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n"));
|
||||
} else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
|
||||
|
||||
ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/
|
||||
|
||||
val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff;
|
||||
if (val >= 0x20)
|
||||
val -= 0x10;
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n"));
|
||||
} else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) {
|
||||
|
||||
ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 0); /* Resp TXAGC offset = 0dB*/
|
||||
ODM_SetBBReg(pDM_Odm, 0xC24, bMaskDWord, pDM_Odm->tx_agc_ofdm_18_6);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPower(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
//
|
||||
// For AP/ADSL use prtl8192cd_priv
|
||||
// For CE/NIC use PADAPTER
|
||||
//
|
||||
//PADAPTER pAdapter = pDM_Odm->Adapter;
|
||||
// prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
|
||||
return;
|
||||
//
|
||||
// 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
|
||||
// at the same time. In the stage2/3, we need to prive universal interface and merge all
|
||||
// HW dynamic mechanism.
|
||||
//
|
||||
switch (pDM_Odm->SupportPlatform)
|
||||
{
|
||||
case ODM_WIN:
|
||||
odm_DynamicTxPowerNIC(pDM_Odm);
|
||||
break;
|
||||
case ODM_CE:
|
||||
odm_DynamicTxPowerNIC_CE(pDM_Odm);
|
||||
break;
|
||||
case ODM_AP:
|
||||
odm_DynamicTxPowerAP(pDM_Odm);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerNIC(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
|
||||
return;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8814A) {
|
||||
odm_DynamicTxPower_8814A(pDM_Odm);
|
||||
} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter);
|
||||
|
||||
if (pMgntInfo->RegRspPwr == 1) {
|
||||
if (pDM_Odm->RSSI_Min > 60)
|
||||
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); /*Resp TXAGC offset = -3dB*/
|
||||
else if (pDM_Odm->RSSI_Min < 55)
|
||||
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); /*Resp TXAGC offset = 0dB*/
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerAP(
|
||||
IN PVOID pDM_VOID
|
||||
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1))
|
||||
|
||||
|
||||
prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
s4Byte i;
|
||||
s2Byte pwr_thd = 63;
|
||||
|
||||
if(!priv->pshare->rf_ft_var.tx_pwr_ctrl)
|
||||
return;
|
||||
|
||||
#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1))
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A))
|
||||
pwr_thd = TX_POWER_NEAR_FIELD_THRESH_LVL1;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check if station is near by to use lower tx power
|
||||
*/
|
||||
|
||||
if ((priv->up_time % 3) == 0 ) {
|
||||
int disable_pwr_ctrl = ((pDM_Odm->FalseAlmCnt.Cnt_all > 1000 ) || ((pDM_Odm->FalseAlmCnt.Cnt_all > 300 ) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0;
|
||||
|
||||
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
|
||||
PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
|
||||
if(IS_STA_VALID(pstat) ) {
|
||||
if(disable_pwr_ctrl)
|
||||
pstat->hp_level = 0;
|
||||
else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd))
|
||||
pstat->hp_level = 1;
|
||||
else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8)))
|
||||
pstat->hp_level = 0;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_WLAN_HAL_8192EE)
|
||||
if (GET_CHIP_VER(priv) == VERSION_8192E) {
|
||||
if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) {
|
||||
if(pDM_Odm->RSSI_Min > pwr_thd)
|
||||
RRSR_power_control_11n(priv, 1 );
|
||||
else if(pDM_Odm->RSSI_Min < (pwr_thd-8))
|
||||
RRSR_power_control_11n(priv, 0 );
|
||||
} else {
|
||||
RRSR_power_control_11n(priv, 0 );
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WLAN_HAL_8814AE
|
||||
if (GET_CHIP_VER(priv) == VERSION_8814A) {
|
||||
if (!disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff)) {
|
||||
if (pDM_Odm->RSSI_Min > pwr_thd)
|
||||
RRSR_power_control_14(priv, 1);
|
||||
else if (pDM_Odm->RSSI_Min < (pwr_thd-8))
|
||||
RRSR_power_control_14(priv, 0);
|
||||
} else {
|
||||
RRSR_power_control_14(priv, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
//#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPower_8821(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte pDesc,
|
||||
IN u1Byte macId
|
||||
)
|
||||
{
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PSTA_INFO_T pEntry;
|
||||
u1Byte reg0xc56_byte;
|
||||
u1Byte txpwr_offset = 0;
|
||||
|
||||
pEntry = pDM_Odm->pODM_StaInfo[macId];
|
||||
|
||||
reg0xc56_byte = ODM_Read1Byte(pDM_Odm, 0xc56);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte));
|
||||
|
||||
if (pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB > 85) {
|
||||
|
||||
/* Avoid TXAGC error after TX power offset is applied.
|
||||
For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB )
|
||||
Total power = 6-11= -5( overflow!! ), PA may be burned !
|
||||
so txpwr_offset should be adjusted by Reg0xc56*/
|
||||
|
||||
if (reg0xc56_byte < 7)
|
||||
txpwr_offset = 1;
|
||||
else if (reg0xc56_byte < 11)
|
||||
txpwr_offset = 2;
|
||||
else
|
||||
txpwr_offset = 3;
|
||||
|
||||
SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset));
|
||||
|
||||
} else{
|
||||
SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset));
|
||||
|
||||
}
|
||||
#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
|
||||
#endif /*#if (RTL8821A_SUPPORT==1)*/
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
odm_DynamicTxPower_8814A(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
s4Byte UndecoratedSmoothedPWDB;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
||||
("TxLevel=%d pMgntInfo->IOTAction=%x pMgntInfo->bDynamicTxPowerEnable=%d\n",
|
||||
pHalData->DynamicTxHighPowerLvl, pMgntInfo->IOTAction, pMgntInfo->bDynamicTxPowerEnable));
|
||||
|
||||
/*STA not connected and AP not connected*/
|
||||
if ((!pMgntInfo->bMediaConnect) && (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n"));
|
||||
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if ((pMgntInfo->bDynamicTxPowerEnable != TRUE) || pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) {
|
||||
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
|
||||
} else {
|
||||
if (pMgntInfo->bMediaConnect) { /*Default port*/
|
||||
if (ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter)) {
|
||||
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
|
||||
} else {
|
||||
UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
|
||||
}
|
||||
} else {/*associated entry pwdb*/
|
||||
UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
|
||||
}
|
||||
|
||||
/*Should we separate as 2.4G/5G band?*/
|
||||
|
||||
if (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
|
||||
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
|
||||
} else if ((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
|
||||
(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
|
||||
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
|
||||
} else if (UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) {
|
||||
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8814A() Channel = %d\n" , pHalData->CurrentChannel));
|
||||
odm_SetTxPowerLevel8814(Adapter, pHalData->CurrentChannel, pHalData->DynamicTxHighPowerLvl);
|
||||
}
|
||||
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
||||
("odm_DynamicTxPower_8814A() Channel = %d TXpower lvl=%d/%d\n" ,
|
||||
pHalData->CurrentChannel, pHalData->LastDTPLvl, pHalData->DynamicTxHighPowerLvl));
|
||||
|
||||
pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**/
|
||||
/*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/
|
||||
/**/
|
||||
/**/
|
||||
VOID
|
||||
odm_SetTxPowerLevel8814(
|
||||
IN PADAPTER Adapter,
|
||||
IN u1Byte Channel,
|
||||
IN u1Byte PwrLvl
|
||||
)
|
||||
{
|
||||
#if (DEV_BUS_TYPE == RT_USB_INTERFACE)
|
||||
u4Byte i, j, k = 0;
|
||||
u4Byte value[264] = {0};
|
||||
u4Byte path = 0, PowerIndex, txagc_table_wd = 0x00801000;
|
||||
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
u1Byte jaguar2Rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
|
||||
{MGN_6M, MGN_9M, MGN_12M, MGN_18M},
|
||||
{MGN_24M, MGN_36M, MGN_48M, MGN_54M},
|
||||
{MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3},
|
||||
{MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
|
||||
{MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11},
|
||||
{MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
|
||||
{MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19},
|
||||
{MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
|
||||
{MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3},
|
||||
{MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7},
|
||||
{MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1},
|
||||
{MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5},
|
||||
{MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
|
||||
{MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3},
|
||||
{MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7},
|
||||
{MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0} };
|
||||
|
||||
for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) {
|
||||
|
||||
u1Byte usb_host = UsbModeQueryHubUsbType(Adapter);
|
||||
u1Byte usb_rfset = UsbModeQueryRfSet(Adapter);
|
||||
u1Byte usb_rf_type = RT_GetRFType(Adapter);
|
||||
|
||||
for (i = 0; i <= 16; i++) {
|
||||
for (j = 0; j <= 3; j++) {
|
||||
if (jaguar2Rates[i][j] == 0)
|
||||
continue;
|
||||
|
||||
txagc_table_wd = 0x00801000;
|
||||
PowerIndex = (u4Byte) PHY_GetTxPowerIndex(Adapter, (u1Byte)path, jaguar2Rates[i][j], pHalData->CurrentChannelBW, Channel);
|
||||
|
||||
/*for Query bus type to recude tx power.*/
|
||||
if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(Adapter) && usb_rf_type == RF_3T3R) {
|
||||
if (Channel <= 14) {
|
||||
if (PowerIndex >= 16)
|
||||
PowerIndex -= 16;
|
||||
else
|
||||
PowerIndex = 0;
|
||||
} else
|
||||
PowerIndex = 0;
|
||||
}
|
||||
|
||||
if (PwrLvl == TxHighPwrLevel_Level1) {
|
||||
if (PowerIndex >= 0x10)
|
||||
PowerIndex -= 0x10;
|
||||
else
|
||||
PowerIndex = 0;
|
||||
} else if (PwrLvl == TxHighPwrLevel_Level2) {
|
||||
PowerIndex = 0;
|
||||
}
|
||||
|
||||
txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2Rates[i][j]) | (PowerIndex << 24);
|
||||
|
||||
PHY_SetTxPowerIndexShadow(Adapter, (u1Byte)PowerIndex, (u1Byte)path, jaguar2Rates[i][j]);
|
||||
|
||||
value[k++] = txagc_table_wd;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (Adapter->MgntInfo.bScanInProgress == FALSE && Adapter->MgntInfo.RegFWOffload == 2)
|
||||
HalDownloadTxPowerLevel8814(Adapter, value);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,110 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMDYNAMICTXPOWER_H__
|
||||
#define __PHYDMDYNAMICTXPOWER_H__
|
||||
|
||||
/*#define DYNAMIC_TXPWR_VERSION "1.0"*/
|
||||
/*#define DYNAMIC_TXPWR_VERSION "1.3" */ /*2015.08.26, Add 8814 Dynamic TX power*/
|
||||
#define DYNAMIC_TXPWR_VERSION "1.4" /*2015.11.06, Add CE 8821A Dynamic TX power*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
|
||||
#endif
|
||||
|
||||
#define TxHighPwrLevel_Normal 0
|
||||
#define TxHighPwrLevel_Level1 1
|
||||
#define TxHighPwrLevel_Level2 2
|
||||
|
||||
#define TxHighPwrLevel_BT1 3
|
||||
#define TxHighPwrLevel_BT2 4
|
||||
#define TxHighPwrLevel_15 5
|
||||
#define TxHighPwrLevel_35 6
|
||||
#define TxHighPwrLevel_50 7
|
||||
#define TxHighPwrLevel_70 8
|
||||
#define TxHighPwrLevel_100 9
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerRestorePowerIndex(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerNIC(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
VOID
|
||||
odm_DynamicTxPowerSavePowerIndex(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerWritePowerIndex(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Value);
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPower_8821(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte pDesc,
|
||||
IN u1Byte macId
|
||||
);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
odm_DynamicTxPower_8814A(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
odm_SetTxPowerLevel8814(
|
||||
IN PADAPTER Adapter,
|
||||
IN u1Byte Channel,
|
||||
IN u1Byte PwrLvl
|
||||
);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPower(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_DynamicTxPowerAP(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,766 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
VOID
|
||||
ODM_EdcaTurboInit(
|
||||
IN PVOID pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
|
||||
PADAPTER Adapter = NULL;
|
||||
HAL_DATA_TYPE *pHalData = NULL;
|
||||
|
||||
if(pDM_Odm->Adapter==NULL) {
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
Adapter=pDM_Odm->Adapter;
|
||||
pHalData=GET_HAL_DATA(Adapter);
|
||||
|
||||
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
|
||||
pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE;
|
||||
pHalData->bIsAnyNonBEPkts = FALSE;
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
|
||||
pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE;
|
||||
Adapter->recvpriv.bIsAnyNonBEPkts =FALSE;
|
||||
|
||||
#endif
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM)));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM)));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM)));
|
||||
|
||||
|
||||
} // ODM_InitEdcaTurbo
|
||||
|
||||
VOID
|
||||
odm_EdcaTurboCheck(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
//
|
||||
// For AP/ADSL use prtl8192cd_priv
|
||||
// For CE/NIC use PADAPTER
|
||||
//
|
||||
|
||||
//
|
||||
// 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
|
||||
// at the same time. In the stage2/3, we need to prive universal interface and merge all
|
||||
// HW dynamic mechanism.
|
||||
//
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n"));
|
||||
|
||||
if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))
|
||||
return;
|
||||
|
||||
switch (pDM_Odm->SupportPlatform)
|
||||
{
|
||||
case ODM_WIN:
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
|
||||
odm_EdcaTurboCheckMP(pDM_Odm);
|
||||
#endif
|
||||
break;
|
||||
|
||||
case ODM_CE:
|
||||
#if(DM_ODM_SUPPORT_TYPE==ODM_CE)
|
||||
odm_EdcaTurboCheckCE(pDM_Odm);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n"));
|
||||
|
||||
} // odm_CheckEdcaTurbo
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE==ODM_CE)
|
||||
|
||||
|
||||
VOID
|
||||
odm_EdcaTurboCheckCE(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
u32 EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer];
|
||||
u32 EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer];
|
||||
u32 ICType=pDM_Odm->SupportICType;
|
||||
u32 IOTPeer=0;
|
||||
u8 WirelessMode=0xFF; //invalid value
|
||||
u32 trafficIndex;
|
||||
u32 edca_param;
|
||||
u64 cur_tx_bytes = 0;
|
||||
u64 cur_rx_bytes = 0;
|
||||
u8 bbtchange = _FALSE;
|
||||
u8 bBiasOnRx = _FALSE;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
|
||||
struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
|
||||
struct recv_priv *precvpriv = &(Adapter->recvpriv);
|
||||
struct registry_priv *pregpriv = &Adapter->registrypriv;
|
||||
struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv);
|
||||
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
|
||||
|
||||
if(pDM_Odm->bLinked != _TRUE)
|
||||
{
|
||||
precvpriv->bIsAnyNonBEPkts = _FALSE;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0))
|
||||
{
|
||||
precvpriv->bIsAnyNonBEPkts = _FALSE;
|
||||
return;
|
||||
}
|
||||
|
||||
if(pDM_Odm->pWirelessMode!=NULL)
|
||||
WirelessMode=*(pDM_Odm->pWirelessMode);
|
||||
|
||||
IOTPeer = pmlmeinfo->assoc_AP_vendor;
|
||||
|
||||
if (IOTPeer >= HT_IOT_PEER_MAX)
|
||||
{
|
||||
precvpriv->bIsAnyNonBEPkts = _FALSE;
|
||||
return;
|
||||
}
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8188E) {
|
||||
if((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS))
|
||||
bBiasOnRx = _TRUE;
|
||||
}
|
||||
|
||||
// Check if the status needs to be changed.
|
||||
if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) )
|
||||
{
|
||||
cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
|
||||
cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
|
||||
|
||||
//traffic, TX or RX
|
||||
if(bBiasOnRx)
|
||||
{
|
||||
if (cur_tx_bytes > (cur_rx_bytes << 2))
|
||||
{ // Uplink TP is present.
|
||||
trafficIndex = UP_LINK;
|
||||
}
|
||||
else
|
||||
{ // Balance TP is present.
|
||||
trafficIndex = DOWN_LINK;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (cur_rx_bytes > (cur_tx_bytes << 2))
|
||||
{ // Downlink TP is present.
|
||||
trafficIndex = DOWN_LINK;
|
||||
}
|
||||
else
|
||||
{ // Balance TP is present.
|
||||
trafficIndex = UP_LINK;
|
||||
}
|
||||
}
|
||||
|
||||
//if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
|
||||
{
|
||||
if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) {
|
||||
EDCA_BE_UL = 0x6ea42b;
|
||||
EDCA_BE_DL = 0x6ea42b;
|
||||
}
|
||||
|
||||
//92D txop can't be set to 0x3e for cisco1250
|
||||
if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G))
|
||||
{
|
||||
EDCA_BE_DL = edca_setting_DL[IOTPeer];
|
||||
EDCA_BE_UL = edca_setting_UL[IOTPeer];
|
||||
}
|
||||
//merge from 92s_92c_merge temp brunch v2445 20120215
|
||||
else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B)))
|
||||
{
|
||||
EDCA_BE_DL = edca_setting_DL_GMode[IOTPeer];
|
||||
}
|
||||
else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)))
|
||||
{
|
||||
EDCA_BE_DL = 0xa630;
|
||||
}
|
||||
else if(IOTPeer == HT_IOT_PEER_MARVELL)
|
||||
{
|
||||
EDCA_BE_DL = edca_setting_DL[IOTPeer];
|
||||
EDCA_BE_UL = edca_setting_UL[IOTPeer];
|
||||
}
|
||||
else if(IOTPeer == HT_IOT_PEER_ATHEROS)
|
||||
{
|
||||
// Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue.
|
||||
EDCA_BE_DL = edca_setting_DL[IOTPeer];
|
||||
}
|
||||
|
||||
if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8821)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE
|
||||
{
|
||||
EDCA_BE_UL = 0x5ea42b;
|
||||
EDCA_BE_DL = 0x5ea42b;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x",EDCA_BE_UL,EDCA_BE_DL));
|
||||
}
|
||||
|
||||
if (trafficIndex == DOWN_LINK)
|
||||
edca_param = EDCA_BE_DL;
|
||||
else
|
||||
edca_param = EDCA_BE_UL;
|
||||
|
||||
rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
|
||||
|
||||
pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
|
||||
}
|
||||
|
||||
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Turn Off EDCA turbo here.
|
||||
// Restore original EDCA according to the declaration of AP.
|
||||
//
|
||||
if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
|
||||
{
|
||||
rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
|
||||
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE==ODM_WIN)
|
||||
VOID
|
||||
odm_EdcaTurboCheckMP(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter);
|
||||
PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL;
|
||||
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
|
||||
PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos;
|
||||
//[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn
|
||||
u8Byte Ext_curTxOkCnt = 0;
|
||||
u8Byte Ext_curRxOkCnt = 0;
|
||||
//For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
|
||||
u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
|
||||
|
||||
// Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
|
||||
u8Byte curTxOkCnt = 0;
|
||||
u8Byte curRxOkCnt = 0;
|
||||
u4Byte EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer];
|
||||
u4Byte EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer];
|
||||
u4Byte EDCA_BE = 0x5ea42b;
|
||||
u1Byte IOTPeer=0;
|
||||
BOOLEAN *pbIsCurRDLState=NULL;
|
||||
BOOLEAN bLastIsCurRDLState=FALSE;
|
||||
BOOLEAN bBiasOnRx=FALSE;
|
||||
BOOLEAN bEdcaTurboOn=FALSE;
|
||||
u1Byte TxRate = 0xFF;
|
||||
u8Byte value64;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>"));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
|
||||
|
||||
////===============================
|
||||
////list paramter for different platform
|
||||
////===============================
|
||||
bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState;
|
||||
pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState);
|
||||
|
||||
//2012/09/14 MH Add
|
||||
if (pMgntInfo->NumNonBePkt > pMgntInfo->RegEdcaThresh && !(Adapter->MgntInfo.bWiFiConfg & RT_WIFI_LOGO))
|
||||
pHalData->bIsAnyNonBEPkts = TRUE;
|
||||
|
||||
pMgntInfo->NumNonBePkt = 0;
|
||||
|
||||
// Caculate TX/RX TP:
|
||||
curTxOkCnt = pDM_Odm->curTxOkCnt;
|
||||
curRxOkCnt = pDM_Odm->curRxOkCnt;
|
||||
|
||||
|
||||
if(pExtAdapter == NULL)
|
||||
pExtAdapter = pDefaultAdapter;
|
||||
|
||||
Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt;
|
||||
Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt;
|
||||
GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
|
||||
//For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
|
||||
if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
|
||||
{
|
||||
curTxOkCnt = Ext_curTxOkCnt ;
|
||||
curRxOkCnt = Ext_curRxOkCnt ;
|
||||
}
|
||||
//
|
||||
IOTPeer=pMgntInfo->IOTPeer;
|
||||
bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE;
|
||||
bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts))?TRUE:FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx \n",pHalData->bIsAnyNonBEPkts));
|
||||
|
||||
|
||||
////===============================
|
||||
////check if edca turbo is disabled
|
||||
////===============================
|
||||
if(odm_IsEdcaTurboDisable(pDM_Odm))
|
||||
{
|
||||
pHalData->bIsAnyNonBEPkts = FALSE;
|
||||
pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
|
||||
pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
|
||||
pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast;
|
||||
pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast;
|
||||
|
||||
}
|
||||
|
||||
////===============================
|
||||
////remove iot case out
|
||||
////===============================
|
||||
ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL);
|
||||
|
||||
|
||||
////===============================
|
||||
////Check if the status needs to be changed.
|
||||
////===============================
|
||||
if(bEdcaTurboOn)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt));
|
||||
if(bBiasOnRx)
|
||||
odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, TRUE, pbIsCurRDLState);
|
||||
else
|
||||
odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, FALSE, pbIsCurRDLState);
|
||||
|
||||
//modify by Guo.Mingzhi 2011-12-29
|
||||
if( Adapter->AP_EDCA_PARAM[0] != EDCA_BE )
|
||||
EDCA_BE = Adapter->AP_EDCA_PARAM[0];
|
||||
else
|
||||
EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL;
|
||||
if(IS_HARDWARE_TYPE_8821U(Adapter))
|
||||
{
|
||||
if(pMgntInfo->RegTxDutyEnable)
|
||||
{
|
||||
//2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle)
|
||||
if(!pMgntInfo->ForcedDataRate) //auto rate
|
||||
{
|
||||
if(pDM_Odm->TxRate != 0xFF)
|
||||
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
|
||||
}
|
||||
else //force rate
|
||||
{
|
||||
TxRate = (u1Byte) pMgntInfo->ForcedDataRate;
|
||||
}
|
||||
|
||||
value64 = (curRxOkCnt<<2);
|
||||
if(curTxOkCnt < value64) //Downlink
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
|
||||
else //Uplink
|
||||
{
|
||||
/*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/
|
||||
/*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/
|
||||
if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G))
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
|
||||
else
|
||||
{
|
||||
switch (TxRate)
|
||||
{
|
||||
case MGN_VHT1SS_MCS6:
|
||||
case MGN_VHT1SS_MCS5:
|
||||
case MGN_MCS6:
|
||||
case MGN_MCS5:
|
||||
case MGN_48M:
|
||||
case MGN_54M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea42b);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS4:
|
||||
case MGN_MCS4:
|
||||
case MGN_36M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa42b);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS3:
|
||||
case MGN_MCS3:
|
||||
case MGN_24M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa47f);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS2:
|
||||
case MGN_MCS2:
|
||||
case MGN_18M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa57f);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS1:
|
||||
case MGN_MCS1:
|
||||
case MGN_9M:
|
||||
case MGN_12M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa77f);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS0:
|
||||
case MGN_MCS0:
|
||||
case MGN_6M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f);
|
||||
break;
|
||||
default:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
|
||||
}
|
||||
|
||||
}
|
||||
else if (IS_HARDWARE_TYPE_8812AU(Adapter)){
|
||||
if(pMgntInfo->RegTxDutyEnable)
|
||||
{
|
||||
//2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle)
|
||||
// it;s the same issue as 8811AU
|
||||
if(!pMgntInfo->ForcedDataRate) //auto rate
|
||||
{
|
||||
if(pDM_Odm->TxRate != 0xFF)
|
||||
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
|
||||
}
|
||||
else //force rate
|
||||
{
|
||||
TxRate = (u1Byte) pMgntInfo->ForcedDataRate;
|
||||
}
|
||||
|
||||
value64 = (curRxOkCnt<<2);
|
||||
if(curTxOkCnt < value64) //Downlink
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
|
||||
else //Uplink
|
||||
{
|
||||
/*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/
|
||||
/*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/
|
||||
if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G))
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
|
||||
else
|
||||
{
|
||||
switch (TxRate)
|
||||
{
|
||||
case MGN_VHT2SS_MCS9:
|
||||
case MGN_VHT1SS_MCS9:
|
||||
case MGN_VHT1SS_MCS8:
|
||||
case MGN_MCS15:
|
||||
case MGN_MCS7:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea44f);
|
||||
case MGN_VHT2SS_MCS8:
|
||||
case MGN_VHT1SS_MCS7:
|
||||
case MGN_MCS14:
|
||||
case MGN_MCS6:
|
||||
case MGN_54M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa44f);
|
||||
case MGN_VHT2SS_MCS7:
|
||||
case MGN_VHT2SS_MCS6:
|
||||
case MGN_VHT1SS_MCS6:
|
||||
case MGN_VHT1SS_MCS5:
|
||||
case MGN_MCS13:
|
||||
case MGN_MCS5:
|
||||
case MGN_48M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa630);
|
||||
break;
|
||||
case MGN_VHT2SS_MCS5:
|
||||
case MGN_VHT2SS_MCS4:
|
||||
case MGN_VHT1SS_MCS4:
|
||||
case MGN_VHT1SS_MCS3:
|
||||
case MGN_MCS12:
|
||||
case MGN_MCS4:
|
||||
case MGN_MCS3:
|
||||
case MGN_36M:
|
||||
case MGN_24M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa730);
|
||||
break;
|
||||
case MGN_VHT2SS_MCS3:
|
||||
case MGN_VHT2SS_MCS2:
|
||||
case MGN_VHT2SS_MCS1:
|
||||
case MGN_VHT1SS_MCS2:
|
||||
case MGN_VHT1SS_MCS1:
|
||||
case MGN_MCS11:
|
||||
case MGN_MCS10:
|
||||
case MGN_MCS9:
|
||||
case MGN_MCS2:
|
||||
case MGN_MCS1:
|
||||
case MGN_18M:
|
||||
case MGN_12M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa830);
|
||||
break;
|
||||
case MGN_VHT2SS_MCS0:
|
||||
case MGN_VHT1SS_MCS0:
|
||||
case MGN_MCS0:
|
||||
case MGN_MCS8:
|
||||
case MGN_9M:
|
||||
case MGN_6M:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f);
|
||||
break;
|
||||
default:
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
|
||||
}
|
||||
}
|
||||
else
|
||||
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE));
|
||||
|
||||
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
// Turn Off EDCA turbo here.
|
||||
// Restore original EDCA according to the declaration of AP.
|
||||
if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
|
||||
{
|
||||
Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) );
|
||||
|
||||
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx \n",pDM_Odm->WMMEDCA_BE));
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
//check if edca turbo is disabled
|
||||
BOOLEAN
|
||||
odm_IsEdcaTurboDisable(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
|
||||
u4Byte IOTPeer=pMgntInfo->IOTPeer;
|
||||
|
||||
if(pDM_Odm->bBtDisableEdcaTurbo)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n"));
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))||
|
||||
(pDM_Odm->WIFITest & RT_WIFI_LOGO)||
|
||||
(IOTPeer>= HT_IOT_PEER_MAX))
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n"));
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
// 1. We do not turn on EDCA turbo mode for some AP that has IOT issue
|
||||
// 2. User may disable EDCA Turbo mode with OID settings.
|
||||
if(pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO){
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n"));
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
|
||||
|
||||
}
|
||||
|
||||
//add iot case here: for MP/CE
|
||||
VOID
|
||||
ODM_EdcaParaSelByIot(
|
||||
IN PVOID pDM_VOID,
|
||||
OUT u4Byte *EDCA_BE_UL,
|
||||
OUT u4Byte *EDCA_BE_DL
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
u4Byte IOTPeer=0;
|
||||
u4Byte ICType=pDM_Odm->SupportICType;
|
||||
u1Byte WirelessMode=0xFF; //invalid value
|
||||
u4Byte IOTPeerSubType = 0;
|
||||
|
||||
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
|
||||
u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
|
||||
|
||||
if(pDM_Odm->pWirelessMode!=NULL)
|
||||
WirelessMode=*(pDM_Odm->pWirelessMode);
|
||||
|
||||
///////////////////////////////////////////////////////////
|
||||
////list paramter for different platform
|
||||
|
||||
IOTPeer=pMgntInfo->IOTPeer;
|
||||
IOTPeerSubType=pMgntInfo->IOTPeerSubtype;
|
||||
GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
|
||||
|
||||
////============================
|
||||
/// IOT case for MP
|
||||
////============================
|
||||
if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) {
|
||||
(*EDCA_BE_UL) = 0x6ea42b;
|
||||
(*EDCA_BE_DL) = 0x6ea42b;
|
||||
}
|
||||
|
||||
if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
|
||||
{
|
||||
(*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer];
|
||||
(*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer];
|
||||
}
|
||||
|
||||
#if (INTEL_PROXIMITY_SUPPORT == 1)
|
||||
if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE)
|
||||
{
|
||||
(*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
if((pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE)))
|
||||
{// To check whether we shall force turn on TXOP configuration.
|
||||
if(!((*EDCA_BE_UL) & 0xffff0000))
|
||||
(*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL.
|
||||
if(!((*EDCA_BE_DL) & 0xffff0000))
|
||||
(*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL.
|
||||
}
|
||||
|
||||
//92D txop can't be set to 0x3e for cisco1250
|
||||
if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G))
|
||||
{
|
||||
(*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
|
||||
(*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
|
||||
}
|
||||
//merge from 92s_92c_merge temp brunch v2445 20120215
|
||||
else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B)))
|
||||
{
|
||||
(*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer];
|
||||
}
|
||||
else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)))
|
||||
{
|
||||
(*EDCA_BE_DL) = 0xa630;
|
||||
}
|
||||
|
||||
else if(IOTPeer == HT_IOT_PEER_MARVELL)
|
||||
{
|
||||
(*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
|
||||
(*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
|
||||
}
|
||||
else if(IOTPeer == HT_IOT_PEER_ATHEROS && IOTPeerSubType != HT_IOT_PEER_TPLINK_AC1750)
|
||||
{
|
||||
// Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue.
|
||||
if(WirelessMode==ODM_WM_G)
|
||||
(*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer];
|
||||
else
|
||||
(*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
|
||||
|
||||
if(ICType == ODM_RTL8821)
|
||||
(*EDCA_BE_DL) = 0x5ea630;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE
|
||||
{
|
||||
(*EDCA_BE_UL) = 0x5ea42b;
|
||||
(*EDCA_BE_DL) = 0x5ea42b;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL)));
|
||||
}
|
||||
|
||||
if((ICType==ODM_RTL8814A) && (IOTPeer == HT_IOT_PEER_REALTEK)) /*8814AU and 8814AR*/
|
||||
{
|
||||
(*EDCA_BE_UL) = 0x5ea42b;
|
||||
(*EDCA_BE_DL) = 0xa42b;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL)));
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, IOTPeer = %d\n",(*EDCA_BE_UL),(*EDCA_BE_DL), IOTPeer));
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
odm_EdcaChooseTrafficIdx(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u8Byte cur_tx_bytes,
|
||||
IN u8Byte cur_rx_bytes,
|
||||
IN BOOLEAN bBiasOnRx,
|
||||
OUT BOOLEAN *pbIsCurRDLState
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
if(bBiasOnRx)
|
||||
{
|
||||
|
||||
if(cur_tx_bytes>(cur_rx_bytes*4))
|
||||
{
|
||||
*pbIsCurRDLState=FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n "));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
*pbIsCurRDLState=TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
|
||||
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(cur_rx_bytes>(cur_tx_bytes*4))
|
||||
{
|
||||
*pbIsCurRDLState=TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink Traffic\n"));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
*pbIsCurRDLState=FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
|
||||
}
|
||||
}
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,100 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMEDCATURBOCHECK_H__
|
||||
#define __PHYDMEDCATURBOCHECK_H__
|
||||
|
||||
/*#define EDCATURBO_VERSION "2.1"*/
|
||||
#define EDCATURBO_VERSION "2.3" /*2015.07.29 by YuChen*/
|
||||
|
||||
typedef struct _EDCA_TURBO_
|
||||
{
|
||||
BOOLEAN bCurrentTurboEDCA;
|
||||
BOOLEAN bIsCurRDLState;
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE == ODM_CE )
|
||||
u4Byte prv_traffic_idx; // edca turbo
|
||||
#endif
|
||||
|
||||
}EDCA_T,*pEDCA_T;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] =
|
||||
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx)
|
||||
{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
|
||||
|
||||
|
||||
static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] =
|
||||
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx)
|
||||
{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
|
||||
|
||||
static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
|
||||
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP
|
||||
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
odm_EdcaTurboCheck(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
VOID
|
||||
ODM_EdcaTurboInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
|
||||
VOID
|
||||
odm_EdcaTurboCheckMP(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
//check if edca turbo is disabled
|
||||
BOOLEAN
|
||||
odm_IsEdcaTurboDisable(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
//choose edca paramter for special IOT case
|
||||
VOID
|
||||
ODM_EdcaParaSelByIot(
|
||||
IN PVOID pDM_VOID,
|
||||
OUT u4Byte *EDCA_BE_UL,
|
||||
OUT u4Byte *EDCA_BE_DL
|
||||
);
|
||||
//check if it is UL or DL
|
||||
VOID
|
||||
odm_EdcaChooseTrafficIdx(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u8Byte cur_tx_bytes,
|
||||
IN u8Byte cur_rx_bytes,
|
||||
IN BOOLEAN bBiasOnRx,
|
||||
OUT BOOLEAN *pbIsCurRDLState
|
||||
);
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
|
||||
VOID
|
||||
odm_EdcaTurboCheckCE(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,142 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDM_FEATURES_H__
|
||||
#define __PHYDM_FEATURES
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
/*Antenna Diversity*/
|
||||
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
|
||||
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
|
||||
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
|
||||
#define CONFIG_FAT_PATCH
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define SUPPORTABLITY_PHYDMLIZE 1
|
||||
#define RA_MASK_PHYDMLIZE_WIN 1
|
||||
/*#define CONFIG_PATH_DIVERSITY*/
|
||||
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
|
||||
#define CONFIG_ANT_DETECTION
|
||||
/*#define CONFIG_RA_DBG_CMD*/
|
||||
#define CONFIG_RA_FW_DBG_CODE 1
|
||||
/*#define CONFIG_PHYDM_RX_SNIFFER_PARSING*/
|
||||
#define CONFIG_BB_POWER_SAVING
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
#define SUPPORTABLITY_PHYDMLIZE 0
|
||||
#define RA_MASK_PHYDMLIZE_AP 1
|
||||
|
||||
/* #define CONFIG_RA_DBG_CMD*/
|
||||
#define CONFIG_RA_FW_DBG_CODE 0
|
||||
|
||||
/*#define CONFIG_PATH_DIVERSITY*/
|
||||
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
|
||||
#define CONFIG_RA_DYNAMIC_RATE_ID
|
||||
/*#define CONFIG_BB_POWER_SAVING*/
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
/* [ Configure Antenna Diversity ] */
|
||||
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH)
|
||||
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
#define ODM_EVM_ENHANCE_ANTDIV
|
||||
|
||||
/*----------*/
|
||||
|
||||
#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
|
||||
#define CONFIG_NO_2G_DIVERSITY
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NO_5G_DIVERSITY_8881A
|
||||
#define CONFIG_NO_5G_DIVERSITY
|
||||
#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
|
||||
#define CONFIG_5G_CGCS_RX_DIVERSITY
|
||||
#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
|
||||
#define CONFIG_5G_CG_TRX_DIVERSITY
|
||||
#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)
|
||||
#define CONFIG_2G5G_CG_TRX_DIVERSITY
|
||||
#endif
|
||||
#if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
|
||||
#define CONFIG_NO_5G_DIVERSITY
|
||||
#endif
|
||||
/*----------*/
|
||||
#if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
|
||||
#define CONFIG_NOT_SUPPORT_ANTDIV
|
||||
#elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
|
||||
#define CONFIG_2G_SUPPORT_ANTDIV
|
||||
#elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY))
|
||||
#define CONFIG_5G_SUPPORT_ANTDIV
|
||||
#elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY))
|
||||
#define CONFIG_2G5G_SUPPORT_ANTDIV
|
||||
#endif
|
||||
/*----------*/
|
||||
#endif
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
#define SUPPORTABLITY_PHYDMLIZE 0
|
||||
#define RA_MASK_PHYDMLIZE_CE 1
|
||||
|
||||
/*Antenna Diversity*/
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
|
||||
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
|
||||
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
|
||||
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DFS_MASTER
|
||||
#define CONFIG_PHYDM_DFS_MASTER
|
||||
#endif
|
||||
|
||||
/*#define CONFIG_RA_DBG_CMD*/
|
||||
#define CONFIG_RA_FW_DBG_CODE 0
|
||||
/*#define CONFIG_ANT_DETECTION*/
|
||||
/*#define CONFIG_PATH_DIVERSITY*/
|
||||
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
|
||||
#define CONFIG_BB_POWER_SAVING
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#define BT_SUPPORT 1
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,568 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __HALHWOUTSRC_H__
|
||||
#define __HALHWOUTSRC_H__
|
||||
|
||||
|
||||
/*--------------------------Define -------------------------------------------*/
|
||||
#define CCK_RSSI_INIT_COUNT 5
|
||||
|
||||
#define RA_RSSI_STATE_INIT 0
|
||||
#define RA_RSSI_STATE_SEND 1
|
||||
#define RA_RSSI_STATE_HOLD 2
|
||||
|
||||
#define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1))
|
||||
/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */
|
||||
|
||||
#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
|
||||
sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
|
||||
#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
|
||||
sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
|
||||
|
||||
#define AGC_DIFF_CONFIG(ic, band) do {\
|
||||
if (pDM_Odm->bIsMPChip)\
|
||||
AGC_DIFF_CONFIG_MP(ic,band);\
|
||||
else\
|
||||
AGC_DIFF_CONFIG_TC(ic,band);\
|
||||
} while(0)
|
||||
|
||||
|
||||
//============================================================
|
||||
// structure and define
|
||||
//============================================================
|
||||
|
||||
__PACK typedef struct _Phy_Rx_AGC_Info
|
||||
{
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte gain:7,trsw:1;
|
||||
#else
|
||||
u1Byte trsw:1,gain:7;
|
||||
#endif
|
||||
} __WLAN_ATTRIB_PACK__ PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T;
|
||||
|
||||
__PACK typedef struct _Phy_Status_Rpt_8192cd {
|
||||
PHY_RX_AGC_INFO_T path_agc[2];
|
||||
u1Byte ch_corr[2];
|
||||
u1Byte cck_sig_qual_ofdm_pwdb_all;
|
||||
u1Byte cck_agc_rpt_ofdm_cfosho_a;
|
||||
u1Byte cck_rpt_b_ofdm_cfosho_b;
|
||||
u1Byte rsvd_1;/*ch_corr_msb;*/
|
||||
u1Byte noise_power_db_msb;
|
||||
s1Byte path_cfotail[2];
|
||||
u1Byte pcts_mask[2];
|
||||
s1Byte stream_rxevm[2];
|
||||
u1Byte path_rxsnr[2];
|
||||
u1Byte noise_power_db_lsb;
|
||||
u1Byte rsvd_2[3];
|
||||
u1Byte stream_csi[2];
|
||||
u1Byte stream_target_csi[2];
|
||||
s1Byte sig_evm;
|
||||
u1Byte rsvd_3;
|
||||
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/
|
||||
u1Byte sgi_en: 1;
|
||||
u1Byte rxsc: 2;
|
||||
u1Byte idle_long: 1;
|
||||
u1Byte r_ant_train_en: 1;
|
||||
u1Byte ant_sel_b: 1;
|
||||
u1Byte ant_sel: 1;
|
||||
#else /*_BIG_ENDIAN_ */
|
||||
u1Byte ant_sel: 1;
|
||||
u1Byte ant_sel_b: 1;
|
||||
u1Byte r_ant_train_en: 1;
|
||||
u1Byte idle_long: 1;
|
||||
u1Byte rxsc: 2;
|
||||
u1Byte sgi_en: 1;
|
||||
u1Byte antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/
|
||||
#endif
|
||||
} __WLAN_ATTRIB_PACK__ PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T;
|
||||
|
||||
|
||||
typedef struct _Phy_Status_Rpt_8812 {
|
||||
/* DWORD 0*/
|
||||
u1Byte gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
|
||||
u1Byte chl_num_LSB; /*channel number[7:0]*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte chl_num_MSB: 2; /*channel number[9:8]*/
|
||||
u1Byte sub_chnl: 4; /*sub-channel location[3:0]*/
|
||||
u1Byte r_RFMOD: 2; /*RF mode[1:0]*/
|
||||
#else /*_BIG_ENDIAN_ */
|
||||
u1Byte r_RFMOD: 2;
|
||||
u1Byte sub_chnl: 4;
|
||||
u1Byte chl_num_MSB: 2;
|
||||
#endif
|
||||
|
||||
/* DWORD 1*/
|
||||
u1Byte pwdb_all; /*CCK signal quality / OFDM pwdb all*/
|
||||
s1Byte cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM Path-A and Path-B short CFO*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
/*this should be checked again because the definition of 8812 and 8814 is different*/
|
||||
/* u1Byte r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/
|
||||
/* u1Byte cck_rx_path:4; cck rx path[3:0]*/
|
||||
u1Byte resvd_0: 6;
|
||||
u1Byte bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/
|
||||
#else /*_BIG_ENDIAN_*/
|
||||
u1Byte bt_RF_ch_MSB: 2;
|
||||
u1Byte resvd_0: 6;
|
||||
#endif
|
||||
|
||||
/* DWORD 2*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/
|
||||
u1Byte ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/
|
||||
u1Byte bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/
|
||||
#else /*_BIG_ENDIAN_ */
|
||||
u1Byte bt_RF_ch_LSB: 6;
|
||||
u1Byte ant_div_sw_b: 1;
|
||||
u1Byte ant_div_sw_a: 1;
|
||||
#endif
|
||||
s1Byte cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/
|
||||
u1Byte PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
|
||||
u1Byte PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
|
||||
|
||||
/* DWORD 3*/
|
||||
s1Byte rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/
|
||||
s1Byte rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/
|
||||
|
||||
/* DWORD 4*/
|
||||
u1Byte PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/
|
||||
u1Byte pcts_rpt_valid: 1; /*pcts_rpt_valid*/
|
||||
u1Byte resvd_1: 1; /*1'b0*/
|
||||
#else /*_BIG_ENDIAN_*/
|
||||
u1Byte resvd_1: 1;
|
||||
u1Byte pcts_rpt_valid: 1;
|
||||
u1Byte PCTS_MSK_RPT_3: 6;
|
||||
#endif
|
||||
s1Byte rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/
|
||||
|
||||
/* DWORD 5*/
|
||||
u1Byte csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/
|
||||
u1Byte gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/
|
||||
|
||||
/* DWORD 6*/
|
||||
s1Byte sigevm; /*signal field EVM*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/
|
||||
u1Byte antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/
|
||||
u1Byte dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/
|
||||
u1Byte GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/
|
||||
#else /*_BIG_ENDIAN_*/
|
||||
u1Byte GNT_BT_keep: 1;
|
||||
u1Byte dpdt_ctrl_keep: 1;
|
||||
u1Byte antidx_antd: 3;
|
||||
u1Byte antidx_antc: 3;
|
||||
#endif
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte antidx_anta: 3; /*antidx_anta[2:0]*/
|
||||
u1Byte antidx_antb: 3; /*antidx_antb[2:0]*/
|
||||
u1Byte hw_antsw_occur: 2; /*1'b0*/
|
||||
#else /*_BIG_ENDIAN_*/
|
||||
u1Byte hw_antsw_occur: 2;
|
||||
u1Byte antidx_antb: 3;
|
||||
u1Byte antidx_anta: 3;
|
||||
#endif
|
||||
} PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T;
|
||||
|
||||
VOID
|
||||
phydm_reset_rssi_for_dm(
|
||||
IN OUT PDM_ODM_T pDM_Odm,
|
||||
IN u1Byte station_id
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_Init_RSSIForDM(
|
||||
IN OUT PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
phydm_normal_driver_rx_sniffer(
|
||||
IN OUT PDM_ODM_T pDM_Odm,
|
||||
IN pu1Byte pDesc,
|
||||
IN PRT_RFD_STATUS pRtRfdStatus,
|
||||
IN pu1Byte pDrvInfo,
|
||||
IN u1Byte PHYStatus
|
||||
);
|
||||
#endif
|
||||
|
||||
VOID
|
||||
ODM_PhyStatusQuery(
|
||||
IN OUT PDM_ODM_T pDM_Odm,
|
||||
OUT PODM_PHY_INFO_T pPhyInfo,
|
||||
IN pu1Byte pPhyStatus,
|
||||
IN PODM_PACKET_INFO_T pPktinfo
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_MacStatusQuery(
|
||||
IN OUT PDM_ODM_T pDM_Odm,
|
||||
IN pu1Byte pMacStatus,
|
||||
IN u1Byte MacID,
|
||||
IN BOOLEAN bPacketMatchBSSID,
|
||||
IN BOOLEAN bPacketToSelf,
|
||||
IN BOOLEAN bPacketBeacon
|
||||
);
|
||||
|
||||
HAL_STATUS
|
||||
ODM_ConfigRFWithTxPwrTrackHeaderFile(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
HAL_STATUS
|
||||
ODM_ConfigRFWithHeaderFile(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN ODM_RF_Config_Type ConfigType,
|
||||
IN ODM_RF_RADIO_PATH_E eRFPath
|
||||
);
|
||||
|
||||
HAL_STATUS
|
||||
ODM_ConfigBBWithHeaderFile(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN ODM_BB_Config_Type ConfigType
|
||||
);
|
||||
|
||||
HAL_STATUS
|
||||
ODM_ConfigMACWithHeaderFile(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
HAL_STATUS
|
||||
ODM_ConfigFWWithHeaderFile(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN ODM_FW_Config_Type ConfigType,
|
||||
OUT u1Byte *pFirmware,
|
||||
OUT u4Byte *pSize
|
||||
);
|
||||
|
||||
u4Byte
|
||||
ODM_GetHWImgVersion(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
s4Byte
|
||||
odm_SignalScaleMapping(
|
||||
IN OUT PDM_ODM_T pDM_Odm,
|
||||
IN s4Byte CurrSig
|
||||
);
|
||||
|
||||
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
|
||||
/*For 8822B only!! need to move to FW finally */
|
||||
/*==============================================*/
|
||||
VOID
|
||||
phydm_RxPhyStatusNewType(
|
||||
IN PDM_ODM_T pPhydm,
|
||||
IN pu1Byte pPhyStatus,
|
||||
IN PODM_PACKET_INFO_T pPktinfo,
|
||||
OUT PODM_PHY_INFO_T pPhyInfo
|
||||
);
|
||||
|
||||
typedef struct _Phy_Status_Rpt_Jaguar2_Type0 {
|
||||
/* DW0 */
|
||||
u1Byte page_num;
|
||||
u1Byte pwdb;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte gain: 6;
|
||||
u1Byte rsvd_0: 1;
|
||||
u1Byte trsw: 1;
|
||||
#else
|
||||
u1Byte trsw: 1;
|
||||
u1Byte rsvd_0: 1;
|
||||
u1Byte gain: 6;
|
||||
#endif
|
||||
u1Byte rsvd_1;
|
||||
|
||||
/* DW1 */
|
||||
u1Byte rsvd_2;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte rxsc: 4;
|
||||
u1Byte agc_table: 4;
|
||||
#else
|
||||
u1Byte agc_table: 4;
|
||||
u1Byte rxsc: 4;
|
||||
#endif
|
||||
u1Byte channel;
|
||||
u1Byte band;
|
||||
|
||||
/* DW2 */
|
||||
u2Byte length;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte antidx_a: 3;
|
||||
u1Byte antidx_b: 3;
|
||||
u1Byte rsvd_3: 2;
|
||||
u1Byte antidx_c: 3;
|
||||
u1Byte antidx_d: 3;
|
||||
u1Byte rsvd_4:2;
|
||||
#else
|
||||
u1Byte rsvd_3: 2;
|
||||
u1Byte antidx_b: 3;
|
||||
u1Byte antidx_a: 3;
|
||||
u1Byte rsvd_4:2;
|
||||
u1Byte antidx_d: 3;
|
||||
u1Byte antidx_c: 3;
|
||||
#endif
|
||||
|
||||
/* DW3 */
|
||||
u1Byte signal_quality;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte vga:5;
|
||||
u1Byte lna_l:3;
|
||||
u1Byte bb_power:6;
|
||||
u1Byte rsvd_9:1;
|
||||
u1Byte lna_h:1;
|
||||
#else
|
||||
u1Byte lna_l:3;
|
||||
u1Byte vga:5;
|
||||
u1Byte lna_h:1;
|
||||
u1Byte rsvd_9:1;
|
||||
u1Byte bb_power:6;
|
||||
#endif
|
||||
u1Byte rsvd_5;
|
||||
|
||||
/* DW4 */
|
||||
u4Byte rsvd_6;
|
||||
|
||||
/* DW5 */
|
||||
u4Byte rsvd_7;
|
||||
|
||||
/* DW6 */
|
||||
u4Byte rsvd_8;
|
||||
} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0;
|
||||
|
||||
typedef struct _Phy_Status_Rpt_Jaguar2_Type1 {
|
||||
/* DW0 and DW1 */
|
||||
u1Byte page_num;
|
||||
u1Byte pwdb[4];
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte l_rxsc: 4;
|
||||
u1Byte ht_rxsc: 4;
|
||||
#else
|
||||
u1Byte ht_rxsc: 4;
|
||||
u1Byte l_rxsc: 4;
|
||||
#endif
|
||||
u1Byte channel;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte band: 2;
|
||||
u1Byte rsvd_0: 1;
|
||||
u1Byte hw_antsw_occu: 1;
|
||||
u1Byte gnt_bt: 1;
|
||||
u1Byte ldpc: 1;
|
||||
u1Byte stbc: 1;
|
||||
u1Byte beamformed: 1;
|
||||
#else
|
||||
u1Byte beamformed: 1;
|
||||
u1Byte stbc: 1;
|
||||
u1Byte ldpc: 1;
|
||||
u1Byte gnt_bt: 1;
|
||||
u1Byte hw_antsw_occu: 1;
|
||||
u1Byte rsvd_0: 1;
|
||||
u1Byte band: 2;
|
||||
#endif
|
||||
|
||||
/* DW2 */
|
||||
u2Byte lsig_length;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte antidx_a: 3;
|
||||
u1Byte antidx_b: 3;
|
||||
u1Byte rsvd_1: 2;
|
||||
u1Byte antidx_c: 3;
|
||||
u1Byte antidx_d: 3;
|
||||
u1Byte rsvd_2: 2;
|
||||
#else
|
||||
u1Byte rsvd_1: 2;
|
||||
u1Byte antidx_b: 3;
|
||||
u1Byte antidx_a: 3;
|
||||
u1Byte rsvd_2: 2;
|
||||
u1Byte antidx_d: 3;
|
||||
u1Byte antidx_c: 3;
|
||||
#endif
|
||||
|
||||
/* DW3 */
|
||||
u1Byte paid;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte paid_msb: 1;
|
||||
u1Byte gid: 6;
|
||||
u1Byte rsvd_3: 1;
|
||||
#else
|
||||
u1Byte rsvd_3: 1;
|
||||
u1Byte gid: 6;
|
||||
u1Byte paid_msb: 1;
|
||||
#endif
|
||||
u1Byte intf_pos;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte intf_pos_msb: 1;
|
||||
u1Byte rsvd_4: 2;
|
||||
u1Byte nb_intf_flag: 1;
|
||||
u1Byte rf_mode: 2;
|
||||
u1Byte rsvd_5: 2;
|
||||
#else
|
||||
u1Byte rsvd_5: 2;
|
||||
u1Byte rf_mode: 2;
|
||||
u1Byte nb_intf_flag: 1;
|
||||
u1Byte rsvd_4: 2;
|
||||
u1Byte intf_pos_msb: 1;
|
||||
#endif
|
||||
|
||||
/* DW4 */
|
||||
s1Byte rxevm[4]; /* s(8,1) */
|
||||
|
||||
/* DW5 */
|
||||
s1Byte cfo_tail[4]; /* s(8,7) */
|
||||
|
||||
/* DW6 */
|
||||
s1Byte rxsnr[4]; /* s(8,1) */
|
||||
} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1;
|
||||
|
||||
typedef struct _Phy_Status_Rpt_Jaguar2_Type2 {
|
||||
/* DW0 ane DW1 */
|
||||
u1Byte page_num;
|
||||
u1Byte pwdb[4];
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte l_rxsc: 4;
|
||||
u1Byte ht_rxsc: 4;
|
||||
#else
|
||||
u1Byte ht_rxsc: 4;
|
||||
u1Byte l_rxsc: 4;
|
||||
#endif
|
||||
u1Byte channel;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte band: 2;
|
||||
u1Byte rsvd_0: 1;
|
||||
u1Byte hw_antsw_occu: 1;
|
||||
u1Byte gnt_bt: 1;
|
||||
u1Byte ldpc: 1;
|
||||
u1Byte stbc: 1;
|
||||
u1Byte beamformed: 1;
|
||||
#else
|
||||
u1Byte beamformed: 1;
|
||||
u1Byte stbc: 1;
|
||||
u1Byte ldpc: 1;
|
||||
u1Byte gnt_bt: 1;
|
||||
u1Byte hw_antsw_occu: 1;
|
||||
u1Byte rsvd_0: 1;
|
||||
u1Byte band: 2;
|
||||
#endif
|
||||
|
||||
/* DW2 */
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte shift_l_map: 6;
|
||||
u1Byte rsvd_1: 2;
|
||||
#else
|
||||
u1Byte rsvd_1: 2;
|
||||
u1Byte shift_l_map: 6;
|
||||
#endif
|
||||
u1Byte cnt_pw2cca;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte agc_table_a: 4;
|
||||
u1Byte agc_table_b: 4;
|
||||
u1Byte agc_table_c: 4;
|
||||
u1Byte agc_table_d: 4;
|
||||
#else
|
||||
u1Byte agc_table_b: 4;
|
||||
u1Byte agc_table_a: 4;
|
||||
u1Byte agc_table_d: 4;
|
||||
u1Byte agc_table_c: 4;
|
||||
#endif
|
||||
|
||||
/* DW3 ~ DW6*/
|
||||
u1Byte cnt_cca2agc_rdy;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte gain_a: 6;
|
||||
u1Byte rsvd_2: 1;
|
||||
u1Byte trsw_a: 1;
|
||||
u1Byte gain_b: 6;
|
||||
u1Byte rsvd_3: 1;
|
||||
u1Byte trsw_b: 1;
|
||||
u1Byte gain_c: 6;
|
||||
u1Byte rsvd_4: 1;
|
||||
u1Byte trsw_c: 1;
|
||||
u1Byte gain_d: 6;
|
||||
u1Byte rsvd_5: 1;
|
||||
u1Byte trsw_d: 1;
|
||||
u1Byte aagc_step_a: 2;
|
||||
u1Byte aagc_step_b: 2;
|
||||
u1Byte aagc_step_c: 2;
|
||||
u1Byte aagc_step_d: 2;
|
||||
#else
|
||||
u1Byte trsw_a: 1;
|
||||
u1Byte rsvd_2: 1;
|
||||
u1Byte gain_a: 6;
|
||||
u1Byte trsw_b: 1;
|
||||
u1Byte rsvd_3: 1;
|
||||
u1Byte gain_b: 6;
|
||||
u1Byte trsw_c: 1;
|
||||
u1Byte rsvd_4: 1;
|
||||
u1Byte gain_c: 6;
|
||||
u1Byte trsw_d: 1;
|
||||
u1Byte rsvd_5: 1;
|
||||
u1Byte gain_d: 6;
|
||||
u1Byte aagc_step_d: 2;
|
||||
u1Byte aagc_step_c: 2;
|
||||
u1Byte aagc_step_b: 2;
|
||||
u1Byte aagc_step_a: 2;
|
||||
#endif
|
||||
u1Byte ht_aagc_gain[4];
|
||||
u1Byte dagc_gain[4];
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u1Byte counter: 6;
|
||||
u1Byte rsvd_6: 2;
|
||||
u1Byte syn_count: 5;
|
||||
u1Byte rsvd_7:3;
|
||||
#else
|
||||
u1Byte rsvd_6: 2;
|
||||
u1Byte counter: 6;
|
||||
u1Byte rsvd_7:3;
|
||||
u1Byte syn_count: 5;
|
||||
#endif
|
||||
} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2;
|
||||
/*==============================================*/
|
||||
#endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/
|
||||
|
||||
u4Byte
|
||||
query_phydm_trx_capability(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
u4Byte
|
||||
query_phydm_stbc_capability(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
u4Byte
|
||||
query_phydm_ldpc_capability(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
u4Byte
|
||||
query_phydm_txbf_parameters(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
u4Byte
|
||||
query_phydm_txbf_capability(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
#endif /*#ifndef __HALHWOUTSRC_H__*/
|
||||
|
||||
@@ -0,0 +1,958 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
//
|
||||
// ODM IO Relative API.
|
||||
//
|
||||
|
||||
u1Byte
|
||||
ODM_Read1Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
return RTL_R8(RegAddr);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
return rtw_read8(Adapter,RegAddr);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
return PlatformEFIORead1Byte(Adapter, RegAddr);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
u2Byte
|
||||
ODM_Read2Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
return RTL_R16(RegAddr);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
return rtw_read16(Adapter,RegAddr);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
return PlatformEFIORead2Byte(Adapter, RegAddr);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
u4Byte
|
||||
ODM_Read4Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
return RTL_R32(RegAddr);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
return rtw_read32(Adapter,RegAddr);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
return PlatformEFIORead4Byte(Adapter, RegAddr);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_Write1Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u1Byte Data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
RTL_W8(RegAddr, Data);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
rtw_write8(Adapter,RegAddr, Data);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformEFIOWrite1Byte(Adapter, RegAddr, Data);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_Write2Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u2Byte Data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
RTL_W16(RegAddr, Data);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
rtw_write16(Adapter,RegAddr, Data);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformEFIOWrite2Byte(Adapter, RegAddr, Data);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_Write4Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte Data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
RTL_W32(RegAddr, Data);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
rtw_write32(Adapter,RegAddr, Data);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformEFIOWrite4Byte(Adapter, RegAddr, Data);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_SetMACReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask,
|
||||
IN u4Byte Data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
u4Byte
|
||||
ODM_GetMACReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
return PHY_QueryMacReg(pDM_Odm->Adapter, RegAddr, BitMask);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_SetBBReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask,
|
||||
IN u4Byte Data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
u4Byte
|
||||
ODM_GetBBReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_SetRFReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN ODM_RF_RADIO_PATH_E eRFPath,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask,
|
||||
IN u4Byte Data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
|
||||
ODM_delay_us(2);
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PHY_SetRFReg(pDM_Odm->Adapter, eRFPath, RegAddr, BitMask, Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
u4Byte
|
||||
ODM_GetRFReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN ODM_RF_RADIO_PATH_E eRFPath,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ODM Memory relative API.
|
||||
//
|
||||
VOID
|
||||
ODM_AllocateMemory(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT PVOID *pPtr,
|
||||
IN u4Byte length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
*pPtr = kmalloc(length, GFP_ATOMIC);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
|
||||
*pPtr = rtw_zvmalloc(length);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformAllocateMemory(Adapter, pPtr, length);
|
||||
#endif
|
||||
}
|
||||
|
||||
// length could be ignored, used to detect memory leakage.
|
||||
VOID
|
||||
ODM_FreeMemory(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT PVOID pPtr,
|
||||
IN u4Byte length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
kfree(pPtr);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
|
||||
rtw_vmfree(pPtr, length);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
//PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformFreeMemory(pPtr, length);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_MoveMemory(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT PVOID pDest,
|
||||
IN PVOID pSrc,
|
||||
IN u4Byte Length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
memcpy(pDest, pSrc, Length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
|
||||
_rtw_memcpy(pDest, pSrc, Length);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformMoveMemory(pDest, pSrc, Length);
|
||||
#endif
|
||||
}
|
||||
|
||||
void ODM_Memory_Set(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PVOID pbuf,
|
||||
IN s1Byte value,
|
||||
IN u4Byte length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
memset(pbuf, value, length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
|
||||
_rtw_memset(pbuf,value, length);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformFillMemory(pbuf,length,value);
|
||||
#endif
|
||||
}
|
||||
s4Byte ODM_CompareMemory(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PVOID pBuf1,
|
||||
IN PVOID pBuf2,
|
||||
IN u4Byte length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return memcmp(pBuf1,pBuf2,length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
|
||||
return _rtw_memcmp(pBuf1,pBuf2,length);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
return PlatformCompareMemory(pBuf1,pBuf2,length);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ODM MISC relative API.
|
||||
//
|
||||
VOID
|
||||
ODM_AcquireSpinLock(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN RT_SPINLOCK_TYPE type
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
rtw_odm_acquirespinlock(Adapter, type);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformAcquireSpinLock(Adapter, type);
|
||||
#endif
|
||||
}
|
||||
VOID
|
||||
ODM_ReleaseSpinLock(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN RT_SPINLOCK_TYPE type
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
rtw_odm_releasespinlock(Adapter, type);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformReleaseSpinLock(Adapter, type);
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Work item relative API. FOr MP driver only~!
|
||||
//
|
||||
VOID
|
||||
ODM_InitializeWorkItem(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_WORK_ITEM pRtWorkItem,
|
||||
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
|
||||
IN PVOID pContext,
|
||||
IN const char* szID
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_StartWorkItem(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformStartWorkItem(pRtWorkItem);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_StopWorkItem(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformStopWorkItem(pRtWorkItem);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_FreeWorkItem(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformFreeWorkItem(pRtWorkItem);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_ScheduleWorkItem(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformScheduleWorkItem(pRtWorkItem);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_IsWorkItemScheduled(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformIsWorkItemScheduled(pRtWorkItem);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ODM Timer relative API.
|
||||
//
|
||||
VOID
|
||||
ODM_StallExecution(
|
||||
IN u4Byte usDelay
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_udelay_os(usDelay);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformStallExecution(usDelay);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_delay_ms(IN u4Byte ms)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
delay_ms(ms);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_mdelay_os(ms);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
delay_ms(ms);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_delay_us(IN u4Byte us)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
delay_us(us);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_udelay_os(us);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformStallExecution(us);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_sleep_ms(IN u4Byte ms)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_msleep_os(ms);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_sleep_us(IN u4Byte us)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_usleep_os(us);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_SetTimer(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_TIMER pTimer,
|
||||
IN u4Byte msDelay
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
mod_timer(pTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(msDelay));
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
_set_timer(pTimer,msDelay ); //ms
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformSetTimer(Adapter, pTimer, msDelay);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
ODM_InitializeTimer(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_TIMER pTimer,
|
||||
IN RT_TIMER_CALL_BACK CallBackFunc,
|
||||
IN PVOID pContext,
|
||||
IN const char* szID
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
init_timer(pTimer);
|
||||
pTimer->function = CallBackFunc;
|
||||
pTimer->data = (unsigned long)pDM_Odm;
|
||||
/*mod_timer(pTimer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
_init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_CancelTimer(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_TIMER pTimer
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
del_timer(pTimer);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
_cancel_timer_ex(pTimer);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
PlatformCancelTimer(Adapter, pTimer);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_ReleaseTimer(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_TIMER pTimer
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
|
||||
// <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm.
|
||||
// Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail.
|
||||
if (pTimer == 0)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
PlatformReleaseTimer(Adapter, pTimer);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
u1Byte
|
||||
phydm_trans_h2c_id(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u1Byte phydm_h2c_id
|
||||
)
|
||||
{
|
||||
u1Byte platform_h2c_id = phydm_h2c_id;
|
||||
|
||||
switch (phydm_h2c_id)
|
||||
{
|
||||
//1 [0]
|
||||
case ODM_H2C_RSSI_REPORT:
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if(pDM_Odm->SupportICType == ODM_RTL8188E)
|
||||
platform_h2c_id = H2C_88E_RSSI_REPORT;
|
||||
else if(pDM_Odm->SupportICType == ODM_RTL8814A)
|
||||
platform_h2c_id =H2C_8814A_RSSI_REPORT;
|
||||
else
|
||||
platform_h2c_id = H2C_RSSI_REPORT;
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
platform_h2c_id = H2C_RSSI_SETTING;
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES)
|
||||
platform_h2c_id = H2C_88XX_RSSI_REPORT;
|
||||
else
|
||||
#endif
|
||||
#if (RTL8812A_SUPPORT == 1)
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8812)
|
||||
platform_h2c_id = H2C_8812_RSSI_REPORT;
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
|
||||
break;
|
||||
|
||||
//1 [3]
|
||||
case ODM_H2C_WIFI_CALIBRATION:
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
platform_h2c_id =H2C_WIFI_CALIBRATION;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#if (RTL8723B_SUPPORT == 1)
|
||||
platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION;
|
||||
#endif
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#endif
|
||||
break;
|
||||
|
||||
|
||||
//1 [4]
|
||||
case ODM_H2C_IQ_CALIBRATION:
|
||||
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
platform_h2c_id =H2C_IQ_CALIBRATION;
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1))
|
||||
platform_h2c_id = H2C_8812_IQ_CALIBRATION;
|
||||
#endif
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#endif
|
||||
|
||||
break;
|
||||
//1 [5]
|
||||
case ODM_H2C_RA_PARA_ADJUST:
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B))
|
||||
platform_h2c_id =H2C_8814A_RA_PARA_ADJUST;
|
||||
else
|
||||
platform_h2c_id = H2C_RA_PARA_ADJUST;
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1))
|
||||
platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
|
||||
#elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
|
||||
platform_h2c_id = H2C_RA_PARA_ADJUST;
|
||||
#elif(RTL8192E_SUPPORT==1)
|
||||
platform_h2c_id =H2C_8192E_RA_PARA_ADJUST;
|
||||
#elif(RTL8723B_SUPPORT==1)
|
||||
platform_h2c_id =H2C_8723B_RA_PARA_ADJUST;
|
||||
#endif
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES)
|
||||
platform_h2c_id = H2C_88XX_RA_PARA_ADJUST;
|
||||
else
|
||||
#endif
|
||||
#if(RTL8812A_SUPPORT==1)
|
||||
if(pDM_Odm->SupportICType == ODM_RTL8812)
|
||||
platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
|
||||
break;
|
||||
|
||||
|
||||
//1 [6]
|
||||
case PHYDM_H2C_DYNAMIC_TX_PATH:
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if(pDM_Odm->SupportICType == ODM_RTL8814A)
|
||||
{
|
||||
platform_h2c_id =H2C_8814A_DYNAMIC_TX_PATH;
|
||||
}
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8814A)
|
||||
platform_h2c_id = H2C_DYNAMIC_TX_PATH;
|
||||
#endif
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if(RTL8814A_SUPPORT==1)
|
||||
if( pDM_Odm->SupportICType == ODM_RTL8814A)
|
||||
{
|
||||
platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
break;
|
||||
|
||||
/* [7]*/
|
||||
case PHYDM_H2C_FW_TRACE_EN:
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B))
|
||||
platform_h2c_id = H2C_8814A_FW_TRACE_EN;
|
||||
else
|
||||
platform_h2c_id = H2C_FW_TRACE_EN;
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
platform_h2c_id = 0x49;
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES)
|
||||
platform_h2c_id = H2C_88XX_FW_TRACE_EN;
|
||||
else
|
||||
#endif
|
||||
#if (RTL8812A_SUPPORT == 1)
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8812)
|
||||
platform_h2c_id = H2C_8812_FW_TRACE_EN;
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
|
||||
#endif
|
||||
|
||||
break;
|
||||
|
||||
case PHYDM_H2C_TXBF:
|
||||
#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
|
||||
platform_h2c_id = 0x41; /*H2C_TxBF*/
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PHYDM_H2C_MU:
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
platform_h2c_id = 0x4a; /*H2C_MU*/
|
||||
#endif
|
||||
break;
|
||||
|
||||
default:
|
||||
platform_h2c_id = phydm_h2c_id;
|
||||
break;
|
||||
}
|
||||
|
||||
return platform_h2c_id;
|
||||
|
||||
}
|
||||
|
||||
/*ODM FW relative API.*/
|
||||
|
||||
VOID
|
||||
ODM_FillH2CCmd(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u1Byte phydm_h2c_id,
|
||||
IN u4Byte CmdLen,
|
||||
IN pu1Byte pCmdBuffer
|
||||
)
|
||||
{
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
u1Byte platform_h2c_id;
|
||||
|
||||
platform_h2c_id=phydm_trans_h2c_id(pDM_Odm, phydm_h2c_id);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E) {
|
||||
if (!pDM_Odm->RaSupport88E)
|
||||
FillH2CCmd88E(Adapter, platform_h2c_id, CmdLen, pCmdBuffer);
|
||||
} else if (pDM_Odm->SupportICType == ODM_RTL8814A)
|
||||
FillH2CCmd8814A(Adapter, platform_h2c_id, CmdLen, pCmdBuffer);
|
||||
else if (pDM_Odm->SupportICType == ODM_RTL8822B)
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
FillH2CCmd8822B(Adapter, platform_h2c_id, CmdLen, pCmdBuffer);
|
||||
#endif
|
||||
else
|
||||
FillH2CCmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer);
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_hal_fill_h2c_cmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer);
|
||||
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES)
|
||||
GET_HAL_INTERFACE(pDM_Odm->priv)->FillH2CCmdHandler(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer);
|
||||
else
|
||||
#endif
|
||||
#if (RTL8812A_SUPPORT == 1)
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8812)
|
||||
FillH2CCmd8812(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer);
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
}
|
||||
|
||||
u1Byte
|
||||
phydm_c2H_content_parsing(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte c2hCmdId,
|
||||
IN u1Byte c2hCmdLen,
|
||||
IN pu1Byte tmpBuf
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
#endif
|
||||
u1Byte Extend_c2hSubID = 0;
|
||||
u1Byte find_c2h_cmd = TRUE;
|
||||
|
||||
switch (c2hCmdId) {
|
||||
case PHYDM_C2H_DBG:
|
||||
phydm_fw_trace_handler(pDM_Odm, tmpBuf, c2hCmdLen);
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_RA_RPT:
|
||||
phydm_c2h_ra_report_handler(pDM_Odm, tmpBuf, c2hCmdLen);
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_RA_PARA_RPT:
|
||||
ODM_C2HRaParaReportHandler(pDM_Odm, tmpBuf, c2hCmdLen);
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_DYNAMIC_TX_PATH_RPT:
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8814A))
|
||||
phydm_c2h_dtp_handler(pDM_Odm, tmpBuf, c2hCmdLen);
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_IQK_FINISH:
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) {
|
||||
|
||||
RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n"));
|
||||
PlatformAcquireSpinLock(Adapter, RT_IQK_SPINLOCK);
|
||||
pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE;
|
||||
PlatformReleaseSpinLock(Adapter, RT_IQK_SPINLOCK);
|
||||
pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = 0;
|
||||
pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime);
|
||||
}
|
||||
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_DBG_CODE:
|
||||
phydm_fw_trace_handler_code(pDM_Odm, tmpBuf, c2hCmdLen);
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_EXTEND:
|
||||
Extend_c2hSubID= tmpBuf[0];
|
||||
if (Extend_c2hSubID == PHYDM_EXTEND_C2H_DBG_PRINT)
|
||||
phydm_fw_trace_handler_8051(pDM_Odm, tmpBuf, c2hCmdLen);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
find_c2h_cmd = FALSE;
|
||||
break;
|
||||
}
|
||||
|
||||
return find_c2h_cmd;
|
||||
|
||||
}
|
||||
|
||||
u8Byte
|
||||
ODM_GetCurrentTime(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return 0;
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
return (u8Byte)rtw_get_current_time();
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
return PlatformGetCurrentTime();
|
||||
#endif
|
||||
}
|
||||
|
||||
u8Byte
|
||||
ODM_GetProgressingTime(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u8Byte Start_Time
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return 0;
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
return rtw_get_passing_time_ms((u4Byte)Start_Time);
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
return ((PlatformGetCurrentTime() - Start_Time)>>10);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,426 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __ODM_INTERFACE_H__
|
||||
#define __ODM_INTERFACE_H__
|
||||
|
||||
#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/
|
||||
|
||||
//
|
||||
// =========== Constant/Structure/Enum/... Define
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
// =========== Macro Define
|
||||
//
|
||||
|
||||
#define _reg_all(_name) ODM_##_name
|
||||
#define _reg_ic(_name, _ic) ODM_##_name##_ic
|
||||
#define _bit_all(_name) BIT_##_name
|
||||
#define _bit_ic(_name, _ic) BIT_##_name##_ic
|
||||
|
||||
// _cat: implemented by Token-Pasting Operator.
|
||||
#if 0
|
||||
#define _cat(_name, _ic_type, _func) \
|
||||
( \
|
||||
_func##_all(_name) \
|
||||
)
|
||||
#endif
|
||||
|
||||
/*===================================
|
||||
|
||||
#define ODM_REG_DIG_11N 0xC50
|
||||
#define ODM_REG_DIG_11AC 0xDDD
|
||||
|
||||
ODM_REG(DIG,_pDM_Odm)
|
||||
=====================================*/
|
||||
|
||||
#define _reg_11N(_name) ODM_REG_##_name##_11N
|
||||
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
|
||||
#define _bit_11N(_name) ODM_BIT_##_name##_11N
|
||||
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
|
||||
|
||||
#ifdef __ECOS
|
||||
#define _rtk_cat(_name, _ic_type, _func) \
|
||||
( \
|
||||
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
|
||||
_func##_11AC(_name) \
|
||||
)
|
||||
#else
|
||||
|
||||
#define _cat(_name, _ic_type, _func) \
|
||||
( \
|
||||
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
|
||||
_func##_11AC(_name) \
|
||||
)
|
||||
#endif
|
||||
/*
|
||||
// only sample code
|
||||
//#define _cat(_name, _ic_type, _func) \
|
||||
// ( \
|
||||
// ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \
|
||||
// _func##_ic(_name, _8195) \
|
||||
// )
|
||||
*/
|
||||
|
||||
// _name: name of register or bit.
|
||||
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
|
||||
// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
|
||||
#ifdef __ECOS
|
||||
#define ODM_REG(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _reg)
|
||||
#define ODM_BIT(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _bit)
|
||||
#else
|
||||
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
|
||||
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
|
||||
#endif
|
||||
typedef enum _PHYDM_H2C_CMD {
|
||||
PHYDM_H2C_TXBF = 0x41,
|
||||
ODM_H2C_RSSI_REPORT = 0x42,
|
||||
ODM_H2C_IQ_CALIBRATION = 0x45,
|
||||
ODM_H2C_RA_PARA_ADJUST = 0x47,
|
||||
PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
|
||||
PHYDM_H2C_FW_TRACE_EN = 0x49,
|
||||
ODM_H2C_WIFI_CALIBRATION = 0x6d,
|
||||
PHYDM_H2C_MU = 0x4a,
|
||||
ODM_MAX_H2CCMD
|
||||
}PHYDM_H2C_CMD;
|
||||
|
||||
typedef enum _PHYDM_C2H_EVT {
|
||||
PHYDM_C2H_DBG = 0,
|
||||
PHYDM_C2H_LB = 1,
|
||||
PHYDM_C2H_XBF = 2,
|
||||
PHYDM_C2H_TX_REPORT = 3,
|
||||
PHYDM_C2H_INFO = 9,
|
||||
PHYDM_C2H_BT_MP = 11,
|
||||
PHYDM_C2H_RA_RPT = 12,
|
||||
PHYDM_C2H_RA_PARA_RPT=14,
|
||||
PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
|
||||
PHYDM_C2H_IQK_FINISH = 17, /*0x11*/
|
||||
PHYDM_C2H_DBG_CODE = 0xFE,
|
||||
PHYDM_C2H_EXTEND = 0xFF,
|
||||
}PHYDM_C2H_EVT;
|
||||
|
||||
typedef enum _PHYDM_EXTEND_C2H_EVT {
|
||||
PHYDM_EXTEND_C2H_DBG_PRINT = 0
|
||||
|
||||
}PHYDM_EXTEND_C2H_EVT;
|
||||
|
||||
|
||||
//
|
||||
// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
|
||||
// Suggest HW team to use thread instead of workitem. Windows also support the feature.
|
||||
//
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
||||
typedef void *PRT_WORK_ITEM ;
|
||||
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
|
||||
typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
|
||||
|
||||
#if 0
|
||||
typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE;
|
||||
|
||||
typedef struct _RT_WORK_ITEM
|
||||
{
|
||||
|
||||
RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object.
|
||||
PVOID Adapter; // Pointer to Adapter object.
|
||||
PVOID pContext; // Parameter to passed to CallBackFunc().
|
||||
RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem.
|
||||
u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled.
|
||||
PVOID pPlatformExt; // Pointer to platform-dependent extension.
|
||||
BOOLEAN bFree;
|
||||
char szID[36]; // An identity string of this workitem.
|
||||
}RT_WORK_ITEM, *PRT_WORK_ITEM;
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// =========== Extern Variable ??? It should be forbidden.
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// =========== EXtern Function Prototype
|
||||
//
|
||||
|
||||
|
||||
u1Byte
|
||||
ODM_Read1Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr
|
||||
);
|
||||
|
||||
u2Byte
|
||||
ODM_Read2Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr
|
||||
);
|
||||
|
||||
u4Byte
|
||||
ODM_Read4Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_Write1Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u1Byte Data
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_Write2Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u2Byte Data
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_Write4Byte(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte Data
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_SetMACReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask,
|
||||
IN u4Byte Data
|
||||
);
|
||||
|
||||
u4Byte
|
||||
ODM_GetMACReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_SetBBReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask,
|
||||
IN u4Byte Data
|
||||
);
|
||||
|
||||
u4Byte
|
||||
ODM_GetBBReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_SetRFReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN ODM_RF_RADIO_PATH_E eRFPath,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask,
|
||||
IN u4Byte Data
|
||||
);
|
||||
|
||||
u4Byte
|
||||
ODM_GetRFReg(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN ODM_RF_RADIO_PATH_E eRFPath,
|
||||
IN u4Byte RegAddr,
|
||||
IN u4Byte BitMask
|
||||
);
|
||||
|
||||
|
||||
//
|
||||
// Memory Relative Function.
|
||||
//
|
||||
VOID
|
||||
ODM_AllocateMemory(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT PVOID *pPtr,
|
||||
IN u4Byte length
|
||||
);
|
||||
VOID
|
||||
ODM_FreeMemory(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT PVOID pPtr,
|
||||
IN u4Byte length
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_MoveMemory(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT PVOID pDest,
|
||||
IN PVOID pSrc,
|
||||
IN u4Byte Length
|
||||
);
|
||||
|
||||
s4Byte ODM_CompareMemory(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PVOID pBuf1,
|
||||
IN PVOID pBuf2,
|
||||
IN u4Byte length
|
||||
);
|
||||
|
||||
void ODM_Memory_Set
|
||||
(IN PDM_ODM_T pDM_Odm,
|
||||
IN PVOID pbuf,
|
||||
IN s1Byte value,
|
||||
IN u4Byte length);
|
||||
|
||||
//
|
||||
// ODM MISC-spin lock relative API.
|
||||
//
|
||||
VOID
|
||||
ODM_AcquireSpinLock(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN RT_SPINLOCK_TYPE type
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_ReleaseSpinLock(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN RT_SPINLOCK_TYPE type
|
||||
);
|
||||
|
||||
|
||||
//
|
||||
// ODM MISC-workitem relative API.
|
||||
//
|
||||
VOID
|
||||
ODM_InitializeWorkItem(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_WORK_ITEM pRtWorkItem,
|
||||
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
|
||||
IN PVOID pContext,
|
||||
IN const char* szID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_StartWorkItem(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_StopWorkItem(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_FreeWorkItem(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_ScheduleWorkItem(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_IsWorkItemScheduled(
|
||||
IN PRT_WORK_ITEM pRtWorkItem
|
||||
);
|
||||
|
||||
//
|
||||
// ODM Timer relative API.
|
||||
//
|
||||
VOID
|
||||
ODM_StallExecution(
|
||||
IN u4Byte usDelay
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_delay_ms(IN u4Byte ms);
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
ODM_delay_us(IN u4Byte us);
|
||||
|
||||
VOID
|
||||
ODM_sleep_ms(IN u4Byte ms);
|
||||
|
||||
VOID
|
||||
ODM_sleep_us(IN u4Byte us);
|
||||
|
||||
VOID
|
||||
ODM_SetTimer(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_TIMER pTimer,
|
||||
IN u4Byte msDelay
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_InitializeTimer(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_TIMER pTimer,
|
||||
IN RT_TIMER_CALL_BACK CallBackFunc,
|
||||
IN PVOID pContext,
|
||||
IN const char* szID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_CancelTimer(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_TIMER pTimer
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_ReleaseTimer(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PRT_TIMER pTimer
|
||||
);
|
||||
|
||||
//
|
||||
// ODM FW relative API.
|
||||
//
|
||||
VOID
|
||||
ODM_FillH2CCmd(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u1Byte ElementID,
|
||||
IN u4Byte CmdLen,
|
||||
IN pu1Byte pCmdBuffer
|
||||
);
|
||||
|
||||
u1Byte
|
||||
phydm_c2H_content_parsing(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte c2hCmdId,
|
||||
IN u1Byte c2hCmdLen,
|
||||
IN pu1Byte tmpBuf
|
||||
);
|
||||
|
||||
u8Byte
|
||||
ODM_GetCurrentTime(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u8Byte
|
||||
ODM_GetProgressingTime(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u8Byte Start_Time
|
||||
);
|
||||
|
||||
#endif // __ODM_INTERFACE_H__
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMIQK_H__
|
||||
#define __PHYDMIQK_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOK_delay 1
|
||||
#define WBIQK_delay 10
|
||||
#define TX_IQK 0
|
||||
#define RX_IQK 1
|
||||
#define TXIQK 0
|
||||
#define RXIQK1 1
|
||||
#define RXIQK2 2
|
||||
|
||||
#define NUM 4
|
||||
/*---------------------------End Define Parameters-------------------------------*/
|
||||
|
||||
typedef struct _IQK_INFORMATION {
|
||||
BOOLEAN LOK_fail[NUM];
|
||||
BOOLEAN IQK_fail[2][NUM];
|
||||
u4Byte IQC_Matrix[2][NUM];
|
||||
u1Byte IQKtimes;
|
||||
u4Byte RFReg18;
|
||||
u4Byte lna_idx;
|
||||
u1Byte rxiqk_step;
|
||||
u1Byte tmp1bcc;
|
||||
|
||||
u4Byte IQK_Channel[2];
|
||||
BOOLEAN IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1)*/
|
||||
u4Byte IQK_CFIR_real[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
|
||||
u4Byte IQK_CFIR_imag[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
|
||||
u1Byte retry_count[2][4][3]; /*channel / path / (TXK:0, RXK1:1, RXK2:2)*/
|
||||
u1Byte gs_retry_count[2][4][2]; /*channel / path / (GSRXK1:0, GSRXK2:1)*/
|
||||
u1Byte RXIQK_fail_code[2][4]; /*channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail*/
|
||||
u4Byte LOK_IDAC[2][4]; /*channel / path*/
|
||||
u4Byte RXIQK_AGC[2][4]; /*channel / path*/
|
||||
u4Byte bypassIQK[2][4]; /*channel / 0xc94/0xe94*/
|
||||
u4Byte tmp_GNTWL;
|
||||
BOOLEAN is_BTG;
|
||||
|
||||
} IQK_INFO, *PIQK_INFO;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,191 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*============================================================*/
|
||||
/*include files*/
|
||||
/*============================================================*/
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
|
||||
/*<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
|
||||
/*This is a phydm API*/
|
||||
|
||||
VOID
|
||||
phydm_SetKfreeToRF_8814A(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte eRFPath,
|
||||
IN u1Byte Data
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
|
||||
BOOLEAN bOdd;
|
||||
|
||||
if ((Data%2) != 0) { /*odd -> positive*/
|
||||
Data = Data - 1;
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 1);
|
||||
bOdd = TRUE;
|
||||
} else { /*even -> negative*/
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 0);
|
||||
bOdd = FALSE;
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", bOdd));
|
||||
switch (Data) {
|
||||
case 0:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 0;
|
||||
break;
|
||||
case 2:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 0;
|
||||
break;
|
||||
case 4:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 1;
|
||||
break;
|
||||
case 6:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 1;
|
||||
break;
|
||||
case 8:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 2;
|
||||
break;
|
||||
case 10:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 2;
|
||||
break;
|
||||
case 12:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 3;
|
||||
break;
|
||||
case 14:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 3;
|
||||
break;
|
||||
case 16:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 4;
|
||||
break;
|
||||
case 18:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 4;
|
||||
break;
|
||||
case 20:
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
|
||||
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 5);
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = 5;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (bOdd == FALSE) {
|
||||
/*that means Kfree offset is negative, we need to record it.*/
|
||||
pRFCalibrateInfo->KfreeOffset[eRFPath] = (-1)*pRFCalibrateInfo->KfreeOffset[eRFPath];
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath]));
|
||||
} else
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath]));
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
phydm_SetKfreeToRF(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte eRFPath,
|
||||
IN u1Byte Data
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
phydm_SetKfreeToRF_8814A(pDM_Odm, eRFPath, Data);
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_ConfigKFree(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte channelToSW,
|
||||
IN pu1Byte kfreeTable
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
|
||||
u1Byte rfpath = 0, maxRFpath = 0;
|
||||
u1Byte channelIdx = 0;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
maxRFpath = 4; /*0~3*/
|
||||
else if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B))
|
||||
maxRFpath = 2; /*0~1*/
|
||||
else
|
||||
maxRFpath = 1;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>phy_ConfigKFree8814A()\n"));
|
||||
|
||||
if (pRFCalibrateInfo->RegRfKFreeEnable == 2) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == 2, Disable\n"));
|
||||
return;
|
||||
} else if (pRFCalibrateInfo->RegRfKFreeEnable == 1 || pRFCalibrateInfo->RegRfKFreeEnable == 0) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == TRUE\n"));
|
||||
/*Make sure the targetval is defined*/
|
||||
if (((pRFCalibrateInfo->RegRfKFreeEnable == 1) && (kfreeTable[0] != 0xFF)) || (pRFCalibrateInfo->RfKFreeEnable == TRUE)) {
|
||||
/*if kfreeTable[0] == 0xff, means no Kfree*/
|
||||
if (*pDM_Odm->pBandType == ODM_BAND_2_4G) {
|
||||
if (channelToSW <= 14 && channelToSW >= 1)
|
||||
channelIdx = PHYDM_2G;
|
||||
} else if (*pDM_Odm->pBandType == ODM_BAND_5G) {
|
||||
if (channelToSW >= 36 && channelToSW <= 48)
|
||||
channelIdx = PHYDM_5GLB1;
|
||||
if (channelToSW >= 52 && channelToSW <= 64)
|
||||
channelIdx = PHYDM_5GLB2;
|
||||
if (channelToSW >= 100 && channelToSW <= 120)
|
||||
channelIdx = PHYDM_5GMB1;
|
||||
if (channelToSW >= 124 && channelToSW <= 144)
|
||||
channelIdx = PHYDM_5GMB2;
|
||||
if (channelToSW >= 149 && channelToSW <= 177)
|
||||
channelIdx = PHYDM_5GHB;
|
||||
}
|
||||
|
||||
for (rfpath = ODM_RF_PATH_A; rfpath < maxRFpath; rfpath++) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phydm_kfree(): PATH_%d: %#x\n", rfpath, kfreeTable[channelIdx*maxRFpath + rfpath]));
|
||||
phydm_SetKfreeToRF(pDM_Odm, rfpath, kfreeTable[channelIdx*maxRFpath + rfpath]);
|
||||
}
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): targetval not defined, Don't execute KFree Process.\n"));
|
||||
return;
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===phy_ConfigKFree8814A()\n"));
|
||||
}
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMKFREE_H__
|
||||
#define __PHYDKFREE_H__
|
||||
|
||||
#define KFREE_VERSION "1.0"
|
||||
|
||||
typedef enum tag_phydm_kfree_channeltosw {
|
||||
PHYDM_2G = 0,
|
||||
PHYDM_5GLB1 = 1,
|
||||
PHYDM_5GLB2 = 2,
|
||||
PHYDM_5GMB1 = 3,
|
||||
PHYDM_5GMB2 = 4,
|
||||
PHYDM_5GHB = 5,
|
||||
} PHYDM_KFREE_CHANNELTOSW;
|
||||
|
||||
|
||||
VOID
|
||||
phydm_ConfigKFree(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte channelToSW,
|
||||
IN pu1Byte kfreeTable
|
||||
);
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,305 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
#include "phydm_noisemonitor.h"
|
||||
|
||||
//=================================================
|
||||
// This function is for inband noise test utility only
|
||||
// To obtain the inband noise level(dbm), do the following.
|
||||
// 1. disable DIG and Power Saving
|
||||
// 2. Set initial gain = 0x1a
|
||||
// 3. Stop updating idle time pwer report (for driver read)
|
||||
// - 0x80c[25]
|
||||
//
|
||||
//=================================================
|
||||
|
||||
#define Valid_Min -35
|
||||
#define Valid_Max 10
|
||||
#define ValidCnt 5
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
|
||||
|
||||
s2Byte odm_InbandNoise_Monitor_NSeries(PDM_ODM_T pDM_Odm,u8 bPauseDIG,u8 IGIValue,u32 max_time)
|
||||
{
|
||||
u4Byte tmp4b;
|
||||
u1Byte max_rf_path=0,rf_path;
|
||||
u1Byte reg_c50, reg_c58,valid_done=0;
|
||||
struct noise_level noise_data;
|
||||
u8Byte start = 0, func_start = 0, func_end = 0;
|
||||
|
||||
func_start = ODM_GetCurrentTime(pDM_Odm);
|
||||
pDM_Odm->noise_level.noise_all = 0;
|
||||
|
||||
if((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R))
|
||||
max_rf_path = 2;
|
||||
else
|
||||
max_rf_path = 1;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() ==> \n"));
|
||||
|
||||
ODM_Memory_Set(pDM_Odm,&noise_data,0,sizeof(struct noise_level));
|
||||
|
||||
//
|
||||
// Step 1. Disable DIG && Set initial gain.
|
||||
//
|
||||
|
||||
if(bPauseDIG)
|
||||
{
|
||||
odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue);
|
||||
}
|
||||
//
|
||||
// Step 2. Disable all power save for read registers
|
||||
//
|
||||
//dcmd_DebugControlPowerSave(pAdapter, PSDisable);
|
||||
|
||||
//
|
||||
// Step 3. Get noise power level
|
||||
//
|
||||
start = ODM_GetCurrentTime(pDM_Odm);
|
||||
while(1)
|
||||
{
|
||||
|
||||
//Stop updating idle time pwer report (for driver read)
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 1);
|
||||
|
||||
//Read Noise Floor Report
|
||||
tmp4b = ODM_GetBBReg(pDM_Odm, 0x8f8,bMaskDWord );
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));
|
||||
|
||||
//ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain);
|
||||
//if(max_rf_path == 2)
|
||||
// ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain);
|
||||
|
||||
//update idle time pwer report per 5us
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 0);
|
||||
|
||||
noise_data.value[ODM_RF_PATH_A] = (u1Byte)(tmp4b&0xff);
|
||||
noise_data.value[ODM_RF_PATH_B] = (u1Byte)((tmp4b&0xff00)>>8);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
|
||||
noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));
|
||||
|
||||
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
|
||||
{
|
||||
noise_data.sval[rf_path] = (s1Byte)noise_data.value[rf_path];
|
||||
noise_data.sval[rf_path] /= 2;
|
||||
}
|
||||
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("sval_a = %d, sval_b = %d\n",
|
||||
noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));
|
||||
//ODM_delay_ms(10);
|
||||
//ODM_sleep_ms(10);
|
||||
|
||||
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
|
||||
{
|
||||
if( (noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min))
|
||||
{
|
||||
noise_data.valid_cnt[rf_path]++;
|
||||
noise_data.sum[rf_path] += noise_data.sval[rf_path];
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("RF_Path:%d Valid sval = %d\n", rf_path,noise_data.sval[rf_path]));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Sum of sval = %d, \n", noise_data.sum[rf_path]));
|
||||
if(noise_data.valid_cnt[rf_path] == ValidCnt)
|
||||
{
|
||||
valid_done++;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("After divided, RF_Path:%d ,sum = %d \n", rf_path,noise_data.sum[rf_path]));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//printk("####### valid_done:%d #############\n",valid_done);
|
||||
if ((valid_done==max_rf_path) || (ODM_GetProgressingTime(pDM_Odm,start) > max_time))
|
||||
{
|
||||
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
|
||||
{
|
||||
//printk("%s PATH_%d - sum = %d, valid_cnt = %d \n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]);
|
||||
if(noise_data.valid_cnt[rf_path])
|
||||
noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path];
|
||||
else
|
||||
noise_data.sum[rf_path] = 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
reg_c50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
|
||||
reg_c50 &= ~BIT7;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50));
|
||||
pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = (u1Byte)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]);
|
||||
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A];
|
||||
|
||||
if(max_rf_path == 2){
|
||||
reg_c58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);
|
||||
reg_c58 &= ~BIT7;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58));
|
||||
pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = (u1Byte)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]);
|
||||
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B];
|
||||
}
|
||||
pDM_Odm->noise_level.noise_all /= max_rf_path;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("noise_a = %d, noise_b = %d\n",
|
||||
pDM_Odm->noise_level.noise[ODM_RF_PATH_A],
|
||||
pDM_Odm->noise_level.noise[ODM_RF_PATH_B]));
|
||||
|
||||
//
|
||||
// Step 4. Recover the Dig
|
||||
//
|
||||
if(bPauseDIG)
|
||||
{
|
||||
odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue);
|
||||
}
|
||||
func_end = ODM_GetProgressingTime(pDM_Odm,func_start) ;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n"));
|
||||
return pDM_Odm->noise_level.noise_all;
|
||||
|
||||
}
|
||||
|
||||
s2Byte
|
||||
odm_InbandNoise_Monitor_ACSeries(PDM_ODM_T pDM_Odm, u8 bPauseDIG, u8 IGIValue, u32 max_time
|
||||
)
|
||||
{
|
||||
s4Byte rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
|
||||
s4Byte value32, pwdb_A = 0, sval, noise, sum;
|
||||
BOOLEAN pd_flag;
|
||||
u1Byte i, valid_cnt;
|
||||
u8Byte start = 0, func_start = 0, func_end = 0;
|
||||
|
||||
|
||||
if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
|
||||
return 0;
|
||||
|
||||
func_start = ODM_GetCurrentTime(pDM_Odm);
|
||||
pDM_Odm->noise_level.noise_all = 0;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() ==>\n"));
|
||||
|
||||
/* Step 1. Disable DIG && Set initial gain. */
|
||||
if (bPauseDIG)
|
||||
odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue);
|
||||
|
||||
/* Step 2. Disable all power save for read registers */
|
||||
/*dcmd_DebugControlPowerSave(pAdapter, PSDisable); */
|
||||
|
||||
/* Step 3. Get noise power level */
|
||||
start = ODM_GetCurrentTime(pDM_Odm);
|
||||
|
||||
/* reset counters */
|
||||
sum = 0;
|
||||
valid_cnt = 0;
|
||||
|
||||
/* Step 3. Get noise power level */
|
||||
while (1) {
|
||||
/*Set IGI=0x1C */
|
||||
ODM_Write_DIG(pDM_Odm, 0x1C);
|
||||
/*stop CK320&CK88 */
|
||||
ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 1);
|
||||
/*Read Path-A */
|
||||
ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, 0x200); /*set debug port*/
|
||||
value32 = ODM_GetBBReg(pDM_Odm, 0xFA0, bMaskDWord); /*read debug port*/
|
||||
|
||||
rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/
|
||||
rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
|
||||
|
||||
pd_flag = (BOOLEAN) ((value32 & BIT31) >> 31);
|
||||
|
||||
/*Not in packet detection period or Tx state */
|
||||
if ((!pd_flag) || (rxi_buf_anta != 0x200)) {
|
||||
/*sign conversion*/
|
||||
rxi_buf_anta = ODM_SignConversion(rxi_buf_anta, 10);
|
||||
rxq_buf_anta = ODM_SignConversion(rxq_buf_anta, 10);
|
||||
|
||||
pwdb_A = ODM_PWdB_Conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF));
|
||||
}
|
||||
/*Start CK320&CK88*/
|
||||
ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 0);
|
||||
/*BB Reset*/
|
||||
ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) & (~BIT0));
|
||||
ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) | BIT0);
|
||||
/*PMAC Reset*/
|
||||
ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) & (~BIT0));
|
||||
ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) | BIT0);
|
||||
/*CCK Reset*/
|
||||
if (ODM_Read1Byte(pDM_Odm, 0x80B) & BIT4) {
|
||||
ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) & (~BIT4));
|
||||
ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) | BIT4);
|
||||
}
|
||||
|
||||
sval = pwdb_A;
|
||||
|
||||
if (sval < 0 && sval >= -27) {
|
||||
if (valid_cnt < ValidCnt) {
|
||||
valid_cnt++;
|
||||
sum += sval;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum));
|
||||
if ((valid_cnt >= ValidCnt) || (ODM_GetProgressingTime(pDM_Odm, start) > max_time)) {
|
||||
sum /= valid_cnt;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*ADC backoff is 12dB,*/
|
||||
/*Ptarget=0x1C-110=-82dBm*/
|
||||
noise = sum + 12 + 0x1C - 110;
|
||||
|
||||
/*Offset*/
|
||||
noise = noise - 3;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise));
|
||||
pDM_Odm->noise_level.noise_all = (s2Byte)noise;
|
||||
|
||||
/* Step 4. Recover the Dig*/
|
||||
if (bPauseDIG)
|
||||
odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue);
|
||||
|
||||
func_end = ODM_GetProgressingTime(pDM_Odm, func_start);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() <==\n"));
|
||||
|
||||
return pDM_Odm->noise_level.noise_all;
|
||||
}
|
||||
|
||||
|
||||
|
||||
s2Byte
|
||||
ODM_InbandNoise_Monitor(PVOID pDM_VOID, u8 bPauseDIG, u8 IGIValue, u32 max_time)
|
||||
{
|
||||
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
|
||||
return odm_InbandNoise_Monitor_ACSeries(pDM_Odm, bPauseDIG, IGIValue, max_time);
|
||||
else
|
||||
return odm_InbandNoise_Monitor_NSeries(pDM_Odm, bPauseDIG, IGIValue, max_time);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,49 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __ODMNOISEMONITOR_H__
|
||||
#define __ODMNOISEMONITOR_H__
|
||||
|
||||
#define ODM_MAX_CHANNEL_NUM 38//14+24
|
||||
struct noise_level
|
||||
{
|
||||
//u1Byte value_a, value_b;
|
||||
u1Byte value[MAX_RF_PATH];
|
||||
//s1Byte sval_a, sval_b;
|
||||
s1Byte sval[MAX_RF_PATH];
|
||||
|
||||
//s4Byte noise_a=0, noise_b=0,sum_a=0, sum_b=0;
|
||||
//s4Byte noise[ODM_RF_PATH_MAX];
|
||||
s4Byte sum[MAX_RF_PATH];
|
||||
//u1Byte valid_cnt_a=0, valid_cnt_b=0,
|
||||
u1Byte valid[MAX_RF_PATH];
|
||||
u1Byte valid_cnt[MAX_RF_PATH];
|
||||
|
||||
};
|
||||
|
||||
|
||||
typedef struct _ODM_NOISE_MONITOR_
|
||||
{
|
||||
s1Byte noise[MAX_RF_PATH];
|
||||
s2Byte noise_all;
|
||||
}ODM_NOISE_MONITOR;
|
||||
|
||||
s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,810 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if(defined(CONFIG_PATH_DIVERSITY))
|
||||
#if RTL8814A_SUPPORT
|
||||
|
||||
VOID
|
||||
phydm_dtp_fix_tx_path(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte path
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv;
|
||||
u1Byte i,num_enable_path=0;
|
||||
|
||||
if(path==pDM_PathDiv->pre_tx_path)
|
||||
{
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_PathDiv->pre_tx_path=path;
|
||||
}
|
||||
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT18|BIT19, 3);
|
||||
|
||||
for(i=0; i<4; i++)
|
||||
{
|
||||
if(path&BIT(i))
|
||||
num_enable_path++;
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Number of trun-on path : (( %d ))\n", num_enable_path));
|
||||
|
||||
if(num_enable_path == 1)
|
||||
{
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path);
|
||||
|
||||
if(path==PHYDM_A)//1-1
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n"));
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
|
||||
}
|
||||
else if(path==PHYDM_B)//1-2
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n"));
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0);
|
||||
}
|
||||
else if(path==PHYDM_C)//1-3
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n"));
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0);
|
||||
|
||||
}
|
||||
else if(path==PHYDM_D)//1-4
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n"));
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 0);
|
||||
}
|
||||
|
||||
}
|
||||
else if(num_enable_path == 2)
|
||||
{
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path);
|
||||
|
||||
if(path==PHYDM_AB)//2-1
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1);
|
||||
}
|
||||
else if(path==PHYDM_AC)//2-2
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1);
|
||||
}
|
||||
else if(path==PHYDM_AD)//2-3
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1);
|
||||
}
|
||||
else if(path==PHYDM_BC)//2-4
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1);
|
||||
}
|
||||
else if(path==PHYDM_BD)//2-5
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1);
|
||||
}
|
||||
else if(path==PHYDM_CD)//2-6
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1);
|
||||
}
|
||||
|
||||
}
|
||||
else if(num_enable_path == 3)
|
||||
{
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, 0xf0000, path);
|
||||
|
||||
if(path==PHYDM_ABC)//3-1
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 2);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 2);
|
||||
//set for 3ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 2);
|
||||
}
|
||||
else if(path==PHYDM_ABD)//3-2
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2);
|
||||
//set for 3ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2);
|
||||
|
||||
}
|
||||
else if(path==PHYDM_ACD)//3-3
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2);
|
||||
//set for 3ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2);
|
||||
}
|
||||
else if(path==PHYDM_BCD)//3-4
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n"));
|
||||
//set for 1ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2);
|
||||
//set for 2ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2);
|
||||
//set for 3ss
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 0);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1);
|
||||
ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2);
|
||||
}
|
||||
}
|
||||
else if(num_enable_path == 4)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n"));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_find_default_path(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv;
|
||||
u4Byte rssi_avg_a=0, rssi_avg_b=0, rssi_avg_c=0, rssi_avg_d=0, rssi_avg_bcd=0;
|
||||
u4Byte rssi_total_a=0, rssi_total_b=0, rssi_total_c=0, rssi_total_d=0;
|
||||
|
||||
//2 Default Path Selection By RSSI
|
||||
|
||||
rssi_avg_a = (pDM_PathDiv->path_a_cnt_all > 0)? (pDM_PathDiv->path_a_sum_all / pDM_PathDiv->path_a_cnt_all) :0 ;
|
||||
rssi_avg_b = (pDM_PathDiv->path_b_cnt_all > 0)? (pDM_PathDiv->path_b_sum_all / pDM_PathDiv->path_b_cnt_all) :0 ;
|
||||
rssi_avg_c = (pDM_PathDiv->path_c_cnt_all > 0)? (pDM_PathDiv->path_c_sum_all / pDM_PathDiv->path_c_cnt_all) :0 ;
|
||||
rssi_avg_d = (pDM_PathDiv->path_d_cnt_all > 0)? (pDM_PathDiv->path_d_sum_all / pDM_PathDiv->path_d_cnt_all) :0 ;
|
||||
|
||||
|
||||
pDM_PathDiv->path_a_sum_all = 0;
|
||||
pDM_PathDiv->path_a_cnt_all = 0;
|
||||
pDM_PathDiv->path_b_sum_all = 0;
|
||||
pDM_PathDiv->path_b_cnt_all = 0;
|
||||
pDM_PathDiv->path_c_sum_all = 0;
|
||||
pDM_PathDiv->path_c_cnt_all = 0;
|
||||
pDM_PathDiv->path_d_sum_all = 0;
|
||||
pDM_PathDiv->path_d_cnt_all = 0;
|
||||
|
||||
if(pDM_PathDiv->use_path_a_as_default_ant == 1)
|
||||
{
|
||||
rssi_avg_bcd=(rssi_avg_b+rssi_avg_c+rssi_avg_d)/3;
|
||||
|
||||
if( (rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd )
|
||||
{
|
||||
pDM_PathDiv->is_pathA_exist=TRUE;
|
||||
pDM_PathDiv->default_path=PATH_A;
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_PathDiv->is_pathA_exist=FALSE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if( (rssi_avg_a >=rssi_avg_b) && (rssi_avg_a >=rssi_avg_c)&&(rssi_avg_a >=rssi_avg_d))
|
||||
pDM_PathDiv->default_path=PATH_A;
|
||||
else if( (rssi_avg_b >=rssi_avg_c)&&(rssi_avg_b >=rssi_avg_d))
|
||||
pDM_PathDiv->default_path=PATH_B;
|
||||
else if( rssi_avg_c >=rssi_avg_d)
|
||||
pDM_PathDiv->default_path=PATH_C;
|
||||
else
|
||||
pDM_PathDiv->default_path=PATH_D;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
phydm_candidate_dtp_update(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv;
|
||||
|
||||
pDM_PathDiv->num_candidate=3;
|
||||
|
||||
if(pDM_PathDiv->use_path_a_as_default_ant == 1)
|
||||
{
|
||||
if(pDM_PathDiv->num_tx_path==3)
|
||||
{
|
||||
if(pDM_PathDiv->is_pathA_exist)
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_ABC;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_ABD;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_ACD;
|
||||
}
|
||||
else // use path BCD
|
||||
{
|
||||
pDM_PathDiv->num_candidate=1;
|
||||
phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD);
|
||||
return;
|
||||
}
|
||||
}
|
||||
else if(pDM_PathDiv->num_tx_path==2)
|
||||
{
|
||||
if(pDM_PathDiv->is_pathA_exist)
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_AB;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_AC;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_AD;
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_BC;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_BD;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_CD;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
//2 3 TX Mode
|
||||
if(pDM_PathDiv->num_tx_path==3)//choose 3 ant form 4
|
||||
{
|
||||
if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_ABC;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_ABD;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_ACD;
|
||||
}
|
||||
else if(pDM_PathDiv->default_path==PATH_B)
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_ABC;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_ABD;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_BCD;
|
||||
}
|
||||
else if(pDM_PathDiv->default_path == PATH_C)
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_ABC;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_ACD;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_BCD;
|
||||
}
|
||||
else if(pDM_PathDiv->default_path == PATH_D)
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_ABD;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_ACD;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_BCD;
|
||||
}
|
||||
}
|
||||
|
||||
//2 2 TX Mode
|
||||
else if(pDM_PathDiv->num_tx_path==2)//choose 2 ant form 4
|
||||
{
|
||||
if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_AB;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_AC;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_AD;
|
||||
}
|
||||
else if(pDM_PathDiv->default_path==PATH_B)
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_AB;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_BC;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_BD;
|
||||
}
|
||||
else if(pDM_PathDiv->default_path == PATH_C)
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1 = PHYDM_AC;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_BC;
|
||||
pDM_PathDiv->ant_candidate_3 = PHYDM_CD;
|
||||
}
|
||||
else if(pDM_PathDiv->default_path == PATH_D)
|
||||
{
|
||||
pDM_PathDiv->ant_candidate_1= PHYDM_AD;
|
||||
pDM_PathDiv->ant_candidate_2 = PHYDM_BD;
|
||||
pDM_PathDiv->ant_candidate_3= PHYDM_CD;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
phydm_dynamic_tx_path(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv;
|
||||
|
||||
PSTA_INFO_T pEntry;
|
||||
u4Byte i;
|
||||
u1Byte num_client=0;
|
||||
u1Byte H2C_Parameter[6] ={0};
|
||||
|
||||
|
||||
if(!pDM_Odm->bLinked) //bLinked==False
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n"));
|
||||
|
||||
if(pDM_PathDiv->bBecomeLinked == TRUE)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n"));
|
||||
pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked;
|
||||
}
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(pDM_PathDiv->bBecomeLinked ==FALSE)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n"));
|
||||
pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked;
|
||||
}
|
||||
}
|
||||
|
||||
//2 [Period CTRL]
|
||||
if(pDM_PathDiv->dtp_period >=2)
|
||||
{
|
||||
pDM_PathDiv->dtp_period=0;
|
||||
}
|
||||
else
|
||||
{
|
||||
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",pDM_PathDiv->dtp_period));
|
||||
pDM_PathDiv->dtp_period++;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
//2 [Fix Path]
|
||||
if (pDM_Odm->path_select != PHYDM_AUTO_PATH)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
//2 [Check Bfer]
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
{
|
||||
BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap);
|
||||
|
||||
if( BeamformCap & BEAMFORMER_CAP ) // BFmer On && Div On -> Div Off
|
||||
{
|
||||
if( pDM_PathDiv->fix_path_bfer == 0)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : OFF ] BFmer ==1 \n"));
|
||||
pDM_PathDiv->fix_path_bfer = 1 ;
|
||||
}
|
||||
return;
|
||||
}
|
||||
else // BFmer Off && Div Off -> Div On
|
||||
{
|
||||
if( pDM_PathDiv->fix_path_bfer == 1 )
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : ON ] BFmer ==0 \n"));
|
||||
pDM_PathDiv->fix_path_bfer = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if(pDM_PathDiv->use_path_a_as_default_ant ==1)
|
||||
{
|
||||
phydm_find_default_path(pDM_Odm);
|
||||
phydm_candidate_dtp_update(pDM_Odm);
|
||||
}
|
||||
else
|
||||
{
|
||||
if( pDM_PathDiv->dtp_state == PHYDM_DTP_INIT)
|
||||
{
|
||||
phydm_find_default_path(pDM_Odm);
|
||||
phydm_candidate_dtp_update(pDM_Odm);
|
||||
pDM_PathDiv->dtp_state = PHYDM_DTP_RUNNING_1;
|
||||
}
|
||||
|
||||
else if( pDM_PathDiv->dtp_state == PHYDM_DTP_RUNNING_1)
|
||||
{
|
||||
pDM_PathDiv->dtp_check_patha_counter++;
|
||||
|
||||
if(pDM_PathDiv->dtp_check_patha_counter>=NUM_RESET_DTP_PERIOD)
|
||||
{
|
||||
pDM_PathDiv->dtp_check_patha_counter=0;
|
||||
pDM_PathDiv->dtp_state = PHYDM_DTP_INIT;
|
||||
}
|
||||
//2 Search space update
|
||||
else
|
||||
{
|
||||
// 1. find the worst candidate
|
||||
|
||||
|
||||
// 2. repalce the worst candidate
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//2 Dynamic Path Selection H2C
|
||||
|
||||
if(pDM_PathDiv->num_candidate == 1)
|
||||
{
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
H2C_Parameter[0] = pDM_PathDiv->num_candidate;
|
||||
H2C_Parameter[1] = pDM_PathDiv->num_tx_path;
|
||||
H2C_Parameter[2] = pDM_PathDiv->ant_candidate_1;
|
||||
H2C_Parameter[3] = pDM_PathDiv->ant_candidate_2;
|
||||
H2C_Parameter[4] = pDM_PathDiv->ant_candidate_3;
|
||||
|
||||
ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, H2C_Parameter);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
phydm_dynamic_tx_path_init(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv);
|
||||
PADAPTER pAdapter = pDM_Odm->Adapter;
|
||||
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
|
||||
USB_MODE_MECH *pUsbModeMech = &pAdapter->UsbModeMechanism;
|
||||
#endif
|
||||
u1Byte search_space_2[NUM_CHOOSE2_FROM4]= {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD };
|
||||
u1Byte search_space_3[NUM_CHOOSE3_FROM4]= {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC};
|
||||
|
||||
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
|
||||
pDM_PathDiv->is_u3_mode = (pUsbModeMech->CurUsbMode==USB_MODE_U3)? 1 : 0 ;
|
||||
#else
|
||||
pDM_PathDiv->is_u3_mode = 1;
|
||||
#endif
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX Path Init 8814\n"));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("is_u3_mode = (( %d ))\n", pDM_PathDiv->is_u3_mode));
|
||||
|
||||
memcpy(&(pDM_PathDiv->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4);
|
||||
memcpy(&(pDM_PathDiv->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4);
|
||||
|
||||
pDM_PathDiv->use_path_a_as_default_ant= 1;
|
||||
pDM_PathDiv->dtp_state = PHYDM_DTP_INIT;
|
||||
pDM_Odm->path_select = PHYDM_AUTO_PATH;
|
||||
pDM_PathDiv->path_div_type = PHYDM_4R_PATH_DIV;
|
||||
|
||||
|
||||
if(pDM_PathDiv->is_u3_mode )
|
||||
{
|
||||
pDM_PathDiv->num_tx_path=3;
|
||||
phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD);/* 3TX Set Init TX Path*/
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_PathDiv->num_tx_path=2;
|
||||
phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BC);/* 2TX // Set Init TX Path*/
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
phydm_process_rssi_for_path_div(
|
||||
IN OUT PVOID pDM_VOID,
|
||||
IN PVOID p_phy_info_void,
|
||||
IN PVOID p_pkt_info_void
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void;
|
||||
PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void;
|
||||
pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv);
|
||||
|
||||
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID)
|
||||
{
|
||||
if(pPktinfo->DataRate > ODM_RATE11M)
|
||||
{
|
||||
if(pDM_PathDiv->path_div_type == PHYDM_4R_PATH_DIV)
|
||||
{
|
||||
#if RTL8814A_SUPPORT
|
||||
if(pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
{
|
||||
pDM_PathDiv->path_a_sum_all+=pPhyInfo->RxMIMOSignalStrength[0];
|
||||
pDM_PathDiv->path_a_cnt_all++;
|
||||
|
||||
pDM_PathDiv->path_b_sum_all+=pPhyInfo->RxMIMOSignalStrength[1];
|
||||
pDM_PathDiv->path_b_cnt_all++;
|
||||
|
||||
pDM_PathDiv->path_c_sum_all+=pPhyInfo->RxMIMOSignalStrength[2];
|
||||
pDM_PathDiv->path_c_cnt_all++;
|
||||
|
||||
pDM_PathDiv->path_d_sum_all+=pPhyInfo->RxMIMOSignalStrength[3];
|
||||
pDM_PathDiv->path_d_cnt_all++;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
pDM_PathDiv->PathA_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[0];
|
||||
pDM_PathDiv->PathA_Cnt[pPktinfo->StationID]++;
|
||||
|
||||
pDM_PathDiv->PathB_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[1];
|
||||
pDM_PathDiv->PathB_Cnt[pPktinfo->StationID]++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
#endif //#if RTL8814A_SUPPORT
|
||||
|
||||
VOID
|
||||
odm_pathdiv_debug(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *const dm_value,
|
||||
IN u4Byte *_used,
|
||||
OUT char *output,
|
||||
IN u4Byte *_out_len
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv);
|
||||
u4Byte used = *_used;
|
||||
u4Byte out_len = *_out_len;
|
||||
|
||||
pDM_Odm->path_select = (dm_value[0] & 0xf);
|
||||
PHYDM_SNPRINTF((output+used, out_len-used,"Path_select = (( 0x%x ))\n",pDM_Odm->path_select ));
|
||||
|
||||
//2 [Fix Path]
|
||||
if (pDM_Odm->path_select != PHYDM_AUTO_PATH)
|
||||
{
|
||||
PHYDM_SNPRINTF((output+used, out_len-used,"Trun on path [%s%s%s%s]\n",
|
||||
((pDM_Odm->path_select) & 0x1)?"A":"",
|
||||
((pDM_Odm->path_select) & 0x2)?"B":"",
|
||||
((pDM_Odm->path_select) & 0x4)?"C":"",
|
||||
((pDM_Odm->path_select) & 0x8)?"D":"" ));
|
||||
|
||||
phydm_dtp_fix_tx_path( pDM_Odm, pDM_Odm->path_select );
|
||||
}
|
||||
else
|
||||
{
|
||||
PHYDM_SNPRINTF((output+used, out_len-used,"%s\n","Auto Path"));
|
||||
}
|
||||
}
|
||||
|
||||
#endif // #if(defined(CONFIG_PATH_DIVERSITY))
|
||||
|
||||
VOID
|
||||
phydm_c2h_dtp_handler(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte CmdBuf,
|
||||
IN u1Byte CmdLen
|
||||
)
|
||||
{
|
||||
#if(defined(CONFIG_PATH_DIVERSITY))
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv);
|
||||
|
||||
u1Byte macid = CmdBuf[0];
|
||||
u1Byte target = CmdBuf[1];
|
||||
u1Byte nsc_1 = CmdBuf[2];
|
||||
u1Byte nsc_2 = CmdBuf[3];
|
||||
u1Byte nsc_3 = CmdBuf[4];
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Target_candidate = (( %d ))\n", target));
|
||||
/*
|
||||
if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3))
|
||||
{
|
||||
phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_1);
|
||||
}
|
||||
else if( nsc_2 >= nsc_3)
|
||||
{
|
||||
phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_2);
|
||||
}
|
||||
else
|
||||
{
|
||||
phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_3);
|
||||
}
|
||||
*/
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_PathDiversity(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
#if(defined(CONFIG_PATH_DIVERSITY))
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
#if RTL8812A_SUPPORT
|
||||
|
||||
if(pDM_Odm->SupportICType & ODM_RTL8812)
|
||||
ODM_PathDiversity_8812A(pDM_Odm);
|
||||
else
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if(pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
phydm_dynamic_tx_path(pDM_Odm);
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_PathDiversityInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
#if(defined(CONFIG_PATH_DIVERSITY))
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
/*pDM_Odm->SupportAbility |= ODM_BB_PATH_DIV;*/
|
||||
|
||||
if(pDM_Odm->mp_mode == TRUE)
|
||||
return;
|
||||
|
||||
if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
#if RTL8812A_SUPPORT
|
||||
if(pDM_Odm->SupportICType & ODM_RTL8812)
|
||||
ODM_PathDiversityInit_8812A(pDM_Odm);
|
||||
else
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if(pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
phydm_dynamic_tx_path_init(pDM_Odm);
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
//
|
||||
// 2011/12/02 MH Copy from MP oursrc for temporarily test.
|
||||
//
|
||||
|
||||
VOID
|
||||
odm_PathDivChkAntSwitchCallback(
|
||||
PRT_TIMER pTimer
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_PathDivChkAntSwitchWorkitemCallback(
|
||||
IN PVOID pContext
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_CCKTXPathDiversityCallback(
|
||||
PRT_TIMER pTimer
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_CCKTXPathDiversityWorkItemCallback(
|
||||
IN PVOID pContext
|
||||
)
|
||||
{
|
||||
}
|
||||
u1Byte
|
||||
odm_SwAntDivSelectScanChnl(
|
||||
IN PADAPTER Adapter
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
VOID
|
||||
odm_SwAntDivConstructScanChnl(
|
||||
IN PADAPTER Adapter,
|
||||
IN u1Byte ScanChnl
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
@@ -0,0 +1,324 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMPATHDIV_H__
|
||||
#define __PHYDMPATHDIV_H__
|
||||
/*#define PATHDIV_VERSION "2.0" //2014.11.04*/
|
||||
#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/
|
||||
|
||||
#if(defined(CONFIG_PATH_DIVERSITY))
|
||||
#define USE_PATH_A_AS_DEFAULT_ANT //for 8814 dynamic TX path selection
|
||||
|
||||
#define NUM_RESET_DTP_PERIOD 5
|
||||
#define ANT_DECT_RSSI_TH 3
|
||||
|
||||
#define PATH_A 1
|
||||
#define PATH_B 2
|
||||
#define PATH_C 3
|
||||
#define PATH_D 4
|
||||
|
||||
#define PHYDM_AUTO_PATH 0
|
||||
#define PHYDM_FIX_PATH 1
|
||||
|
||||
#define NUM_CHOOSE2_FROM4 6
|
||||
#define NUM_CHOOSE3_FROM4 4
|
||||
|
||||
|
||||
#define PHYDM_A BIT0
|
||||
#define PHYDM_B BIT1
|
||||
#define PHYDM_C BIT2
|
||||
#define PHYDM_D BIT3
|
||||
#define PHYDM_AB (BIT0 | BIT1) // 0
|
||||
#define PHYDM_AC (BIT0 | BIT2) // 1
|
||||
#define PHYDM_AD (BIT0 | BIT3) // 2
|
||||
#define PHYDM_BC (BIT1 | BIT2) // 3
|
||||
#define PHYDM_BD (BIT1 | BIT3) // 4
|
||||
#define PHYDM_CD (BIT2 | BIT3) // 5
|
||||
|
||||
#define PHYDM_ABC (BIT0 | BIT1 | BIT2) /* 0*/
|
||||
#define PHYDM_ABD (BIT0 | BIT1 | BIT3) /* 1*/
|
||||
#define PHYDM_ACD (BIT0 | BIT2 | BIT3) /* 2*/
|
||||
#define PHYDM_BCD (BIT1 | BIT2 | BIT3) /* 3*/
|
||||
|
||||
#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3)
|
||||
|
||||
|
||||
typedef enum dtp_state
|
||||
{
|
||||
PHYDM_DTP_INIT=1,
|
||||
PHYDM_DTP_RUNNING_1
|
||||
|
||||
}PHYDM_DTP_STATE;
|
||||
|
||||
typedef enum path_div_type
|
||||
{
|
||||
PHYDM_2R_PATH_DIV = 1,
|
||||
PHYDM_4R_PATH_DIV = 2
|
||||
}PHYDM_PATH_DIV_TYPE;
|
||||
|
||||
VOID
|
||||
phydm_process_rssi_for_path_div(
|
||||
IN OUT PVOID pDM_VOID,
|
||||
IN PVOID p_phy_info_void,
|
||||
IN PVOID p_pkt_info_void
|
||||
);
|
||||
|
||||
typedef struct _ODM_PATH_DIVERSITY_
|
||||
{
|
||||
u1Byte RespTxPath;
|
||||
u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u2Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u1Byte path_div_type;
|
||||
#if RTL8814A_SUPPORT
|
||||
|
||||
u4Byte path_a_sum_all;
|
||||
u4Byte path_b_sum_all;
|
||||
u4Byte path_c_sum_all;
|
||||
u4Byte path_d_sum_all;
|
||||
|
||||
u4Byte path_a_cnt_all;
|
||||
u4Byte path_b_cnt_all;
|
||||
u4Byte path_c_cnt_all;
|
||||
u4Byte path_d_cnt_all;
|
||||
|
||||
u1Byte dtp_period;
|
||||
BOOLEAN bBecomeLinked;
|
||||
BOOLEAN is_u3_mode;
|
||||
u1Byte num_tx_path;
|
||||
u1Byte default_path;
|
||||
u1Byte num_candidate;
|
||||
u1Byte ant_candidate_1;
|
||||
u1Byte ant_candidate_2;
|
||||
u1Byte ant_candidate_3;
|
||||
u1Byte dtp_state;
|
||||
u1Byte dtp_check_patha_counter;
|
||||
BOOLEAN fix_path_bfer;
|
||||
u1Byte search_space_2[NUM_CHOOSE2_FROM4];
|
||||
u1Byte search_space_3[NUM_CHOOSE3_FROM4];
|
||||
|
||||
u1Byte pre_tx_path;
|
||||
u1Byte use_path_a_as_default_ant;
|
||||
BOOLEAN is_pathA_exist;
|
||||
|
||||
#endif
|
||||
}PATHDIV_T, *pPATHDIV_T;
|
||||
|
||||
|
||||
#endif //#if(defined(CONFIG_PATH_DIVERSITY))
|
||||
|
||||
VOID
|
||||
phydm_c2h_dtp_handler(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte CmdBuf,
|
||||
IN u1Byte CmdLen
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_PathDiversityInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_PathDiversity(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_pathdiv_debug(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *const dm_value,
|
||||
IN u4Byte *_used,
|
||||
OUT char *output,
|
||||
IN u4Byte *_out_len
|
||||
);
|
||||
|
||||
|
||||
|
||||
//1 [OLD IC]--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
//#define PATHDIV_ENABLE 1
|
||||
#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi
|
||||
#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C
|
||||
|
||||
|
||||
|
||||
|
||||
typedef struct _PathDiv_Parameter_define_
|
||||
{
|
||||
u4Byte org_5g_RegE30;
|
||||
u4Byte org_5g_RegC14;
|
||||
u4Byte org_5g_RegCA0;
|
||||
u4Byte swt_5g_RegE30;
|
||||
u4Byte swt_5g_RegC14;
|
||||
u4Byte swt_5g_RegCA0;
|
||||
//for 2G IQK information
|
||||
u4Byte org_2g_RegC80;
|
||||
u4Byte org_2g_RegC4C;
|
||||
u4Byte org_2g_RegC94;
|
||||
u4Byte org_2g_RegC14;
|
||||
u4Byte org_2g_RegCA0;
|
||||
|
||||
u4Byte swt_2g_RegC80;
|
||||
u4Byte swt_2g_RegC4C;
|
||||
u4Byte swt_2g_RegC94;
|
||||
u4Byte swt_2g_RegC14;
|
||||
u4Byte swt_2g_RegCA0;
|
||||
}PATHDIV_PARA,*pPATHDIV_PARA;
|
||||
|
||||
VOID
|
||||
odm_PathDiversityInit_92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_2TPathDiversityInit_92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_1TPathDiversityInit_92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
odm_IsConnected_92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
ODM_PathDiversityBeforeLink92C(
|
||||
//IN PADAPTER Adapter
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_PathDiversityAfterLink_92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_SetRespPath_92C(
|
||||
IN PADAPTER Adapter,
|
||||
IN u1Byte DefaultRespPath
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_OFDMTXPathDiversity_92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_CCKTXPathDiversity_92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_ResetPathDiversity_92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_CCKTXPathDiversityCallback(
|
||||
PRT_TIMER pTimer
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_CCKTXPathDiversityWorkItemCallback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_PathDivChkAntSwitchCallback(
|
||||
PRT_TIMER pTimer
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_PathDivChkAntSwitchWorkitemCallback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
odm_PathDivChkAntSwitch(
|
||||
PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_CCKPathDiversityChkPerPktRssi(
|
||||
PADAPTER Adapter,
|
||||
BOOLEAN bIsDefPort,
|
||||
BOOLEAN bMatchBSSID,
|
||||
PRT_WLAN_STA pEntry,
|
||||
PRT_RFD pRfd,
|
||||
pu1Byte pDesc
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_PathDivChkPerPktRssi(
|
||||
PADAPTER Adapter,
|
||||
BOOLEAN bIsDefPort,
|
||||
BOOLEAN bMatchBSSID,
|
||||
PRT_WLAN_STA pEntry,
|
||||
PRT_RFD pRfd
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_PathDivRestAfterLink(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_FillTXPathInTXDESC(
|
||||
IN PADAPTER Adapter,
|
||||
IN PRT_TCB pTcb,
|
||||
IN pu1Byte pDesc
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_PathDivInit_92D(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
u1Byte
|
||||
odm_SwAntDivSelectScanChnl(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_SwAntDivConstructScanChnl(
|
||||
IN PADAPTER Adapter,
|
||||
IN u1Byte ScanChnl
|
||||
);
|
||||
|
||||
#endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
|
||||
#endif //#ifndef __ODMPATHDIV_H__
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,351 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMPOWERTRACKING_H__
|
||||
#define __PHYDMPOWERTRACKING_H__
|
||||
|
||||
#define POWRTRACKING_VERSION "1.1"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#ifdef RTK_AC_SUPPORT
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#else
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 0
|
||||
#endif
|
||||
#else
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#endif
|
||||
|
||||
#define DPK_DELTA_MAPPING_NUM 13
|
||||
#define index_mapping_HP_NUM 15
|
||||
#define DELTA_SWINGIDX_SIZE 30
|
||||
#define DELTA_SWINTSSI_SIZE 61
|
||||
#define BAND_NUM 3
|
||||
#define MAX_RF_PATH 4
|
||||
#define TXSCALE_TABLE_SIZE 37
|
||||
#define CCK_TABLE_SIZE_8723D 41
|
||||
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_BB_REG_NUM_MAX 10
|
||||
|
||||
#define IQK_BB_REG_NUM 9
|
||||
|
||||
#define HP_THERMAL_NUM 8
|
||||
|
||||
#define AVG_THERMAL_NUM 8
|
||||
#define IQK_Matrix_REG_NUM 8
|
||||
//#define IQK_Matrix_Settings_NUM 1+24+21
|
||||
#define IQK_Matrix_Settings_NUM (14+24+21) // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
|
||||
|
||||
#if !defined(_OUTSRC_COEXIST)
|
||||
#define OFDM_TABLE_SIZE_92D 43
|
||||
#define OFDM_TABLE_SIZE 37
|
||||
#define CCK_TABLE_SIZE 33
|
||||
#define CCK_TABLE_SIZE_88F 21
|
||||
|
||||
|
||||
|
||||
//#define OFDM_TABLE_SIZE_92E 54
|
||||
//#define CCK_TABLE_SIZE_92E 54
|
||||
extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
|
||||
extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
|
||||
|
||||
|
||||
extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
|
||||
extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16];
|
||||
extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16];
|
||||
|
||||
#endif
|
||||
|
||||
#define ODM_OFDM_TABLE_SIZE 37
|
||||
#define ODM_CCK_TABLE_SIZE 33
|
||||
// <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table.
|
||||
extern u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE];
|
||||
extern u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE];
|
||||
|
||||
static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
|
||||
static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
|
||||
|
||||
//extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E];
|
||||
//extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8];
|
||||
//extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8];
|
||||
|
||||
#ifdef CONFIG_WLAN_HAL_8192EE
|
||||
#define OFDM_TABLE_SIZE_92E 54
|
||||
#define CCK_TABLE_SIZE_92E 54
|
||||
extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8];
|
||||
extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8];
|
||||
#endif
|
||||
|
||||
#define OFDM_TABLE_SIZE_8812 43
|
||||
#define AVG_THERMAL_NUM_8812 4
|
||||
|
||||
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
|
||||
extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
|
||||
#elif(ODM_IC_11AC_SERIES_SUPPORT)
|
||||
extern unsigned int OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812];
|
||||
#endif
|
||||
|
||||
extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D];
|
||||
|
||||
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
|
||||
|
||||
typedef struct _IQK_MATRIX_REGS_SETTING{
|
||||
BOOLEAN bIQKDone;
|
||||
s4Byte Value[1][IQK_Matrix_REG_NUM];
|
||||
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
|
||||
|
||||
typedef struct ODM_RF_Calibration_Structure
|
||||
{
|
||||
//for tx power tracking
|
||||
|
||||
u4Byte RegA24; // for TempCCK
|
||||
s4Byte RegE94;
|
||||
s4Byte RegE9C;
|
||||
s4Byte RegEB4;
|
||||
s4Byte RegEBC;
|
||||
|
||||
//u1Byte bTXPowerTracking;
|
||||
u1Byte TXPowercount;
|
||||
BOOLEAN bTXPowerTrackingInit;
|
||||
BOOLEAN bTXPowerTracking;
|
||||
u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
|
||||
u1Byte TM_Trigger;
|
||||
u1Byte InternalPA5G[2]; //pathA / pathB
|
||||
|
||||
u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
|
||||
u1Byte ThermalValue;
|
||||
u1Byte ThermalValue_LCK;
|
||||
u1Byte ThermalValue_IQK;
|
||||
u1Byte ThermalValue_DPK;
|
||||
u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
|
||||
u1Byte ThermalValue_AVG_index;
|
||||
u1Byte ThermalValue_RxGain;
|
||||
u1Byte ThermalValue_Crystal;
|
||||
u1Byte ThermalValue_DPKstore;
|
||||
u1Byte ThermalValue_DPKtrack;
|
||||
BOOLEAN TxPowerTrackingInProgress;
|
||||
BOOLEAN bDPKenable;
|
||||
|
||||
BOOLEAN bReloadtxpowerindex;
|
||||
u1Byte bRfPiEnable;
|
||||
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
|
||||
|
||||
u1Byte bCCKinCH14;
|
||||
u1Byte CCK_index;
|
||||
u1Byte OFDM_index[MAX_RF_PATH];
|
||||
s1Byte PowerIndexOffset;
|
||||
s1Byte DeltaPowerIndex;
|
||||
s1Byte DeltaPowerIndexLast;
|
||||
BOOLEAN bTxPowerChanged;
|
||||
|
||||
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
|
||||
u1Byte ThermalValue_HP_index;
|
||||
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
|
||||
u1Byte Delta_LCK;
|
||||
u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
|
||||
|
||||
u1Byte BbSwingIdxOfdm[MAX_RF_PATH];
|
||||
u1Byte BbSwingIdxOfdmCurrent;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH];
|
||||
#else
|
||||
u1Byte BbSwingIdxOfdmBase;
|
||||
#endif
|
||||
BOOLEAN BbSwingFlagOfdm;
|
||||
u1Byte BbSwingIdxCck;
|
||||
u1Byte BbSwingIdxCckCurrent;
|
||||
u1Byte BbSwingIdxCckBase;
|
||||
u1Byte DefaultOfdmIndex;
|
||||
u1Byte DefaultCckIndex;
|
||||
BOOLEAN BbSwingFlagCck;
|
||||
|
||||
s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH];
|
||||
s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH];
|
||||
s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH];
|
||||
s1Byte Remnant_CCKSwingIdx;
|
||||
s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */
|
||||
BOOLEAN Modify_TxAGC_Flag_PathA;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathB;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathC;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathD;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathA_CCK;
|
||||
|
||||
s1Byte KfreeOffset[MAX_RF_PATH];
|
||||
|
||||
//--------------------------------------------------------------------//
|
||||
|
||||
//for IQK
|
||||
u4Byte RegC04;
|
||||
u4Byte Reg874;
|
||||
u4Byte RegC08;
|
||||
u4Byte RegB68;
|
||||
u4Byte RegB6C;
|
||||
u4Byte Reg870;
|
||||
u4Byte Reg860;
|
||||
u4Byte Reg864;
|
||||
|
||||
BOOLEAN bIQKInitialized;
|
||||
BOOLEAN bLCKInProgress;
|
||||
BOOLEAN bAntennaDetected;
|
||||
BOOLEAN bNeedIQK;
|
||||
BOOLEAN bIQKInProgress;
|
||||
BOOLEAN bIQKPAoff;
|
||||
u1Byte Delta_IQK;
|
||||
u4Byte ADDA_backup[IQK_ADDA_REG_NUM];
|
||||
u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM];
|
||||
u4Byte IQK_BB_backup_recover[9];
|
||||
u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
|
||||
u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
|
||||
u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
|
||||
u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
|
||||
u8Byte IQK_StartTime;
|
||||
u8Byte IQK_TotalProgressingTime;
|
||||
u8Byte IQK_ProgressingTime;
|
||||
u4Byte LOK_Result;
|
||||
u1Byte IQKstep;
|
||||
u1Byte Kcount;
|
||||
u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
|
||||
BOOLEAN isMPmode;
|
||||
|
||||
//for APK
|
||||
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
|
||||
u1Byte bAPKdone;
|
||||
u1Byte bAPKThermalMeterIgnore;
|
||||
u1Byte bDPdone;
|
||||
u1Byte bDPPathAOK;
|
||||
u1Byte bDPPathBOK;
|
||||
|
||||
/*Add by Yuchen for Kfree Phydm*/
|
||||
u1Byte RegRfKFreeEnable; /*for registry*/
|
||||
u1Byte RfKFreeEnable; /*for efuse enable check*/
|
||||
u4Byte TxLOK[2];
|
||||
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckAP(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_TXPowerTrackingCheck(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckMP(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckCE(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCallbackThermalMeter92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCallbackRXGainThermalMeter92D(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCallbackThermalMeter92D(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingDirectCall92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterCheck(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,756 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*============================================================ */
|
||||
/* include files */
|
||||
/*============================================================ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
//============================================================
|
||||
// Global var
|
||||
//============================================================
|
||||
|
||||
u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = {
|
||||
0x7f8001fe, /* 0, +6.0dB */
|
||||
0x788001e2, /* 1, +5.5dB */
|
||||
0x71c001c7, /* 2, +5.0dB*/
|
||||
0x6b8001ae, /* 3, +4.5dB*/
|
||||
0x65400195, /* 4, +4.0dB*/
|
||||
0x5fc0017f, /* 5, +3.5dB*/
|
||||
0x5a400169, /* 6, +3.0dB*/
|
||||
0x55400155, /* 7, +2.5dB*/
|
||||
0x50800142, /* 8, +2.0dB*/
|
||||
0x4c000130, /* 9, +1.5dB*/
|
||||
0x47c0011f, /* 10, +1.0dB*/
|
||||
0x43c0010f, /* 11, +0.5dB*/
|
||||
0x40000100, /* 12, +0dB*/
|
||||
0x3c8000f2, /* 13, -0.5dB*/
|
||||
0x390000e4, /* 14, -1.0dB*/
|
||||
0x35c000d7, /* 15, -1.5dB*/
|
||||
0x32c000cb, /* 16, -2.0dB*/
|
||||
0x300000c0, /* 17, -2.5dB*/
|
||||
0x2d4000b5, /* 18, -3.0dB*/
|
||||
0x2ac000ab, /* 19, -3.5dB*/
|
||||
0x288000a2, /* 20, -4.0dB*/
|
||||
0x26000098, /* 21, -4.5dB*/
|
||||
0x24000090, /* 22, -5.0dB*/
|
||||
0x22000088, /* 23, -5.5dB*/
|
||||
0x20000080, /* 24, -6.0dB*/
|
||||
0x1e400079, /* 25, -6.5dB*/
|
||||
0x1c800072, /* 26, -7.0dB*/
|
||||
0x1b00006c, /* 27. -7.5dB*/
|
||||
0x19800066, /* 28, -8.0dB*/
|
||||
0x18000060, /* 29, -8.5dB*/
|
||||
0x16c0005b, /* 30, -9.0dB*/
|
||||
0x15800056, /* 31, -9.5dB*/
|
||||
0x14400051, /* 32, -10.0dB*/
|
||||
0x1300004c, /* 33, -10.5dB*/
|
||||
0x12000048, /* 34, -11.0dB*/
|
||||
0x11000044, /* 35, -11.5dB*/
|
||||
0x10000040, /* 36, -12.0dB*/
|
||||
};
|
||||
|
||||
u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
|
||||
};
|
||||
|
||||
|
||||
u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = {
|
||||
0x0b40002d, /* 0, -15.0dB */
|
||||
0x0c000030, /* 1, -14.5dB*/
|
||||
0x0cc00033, /* 2, -14.0dB*/
|
||||
0x0d800036, /* 3, -13.5dB*/
|
||||
0x0e400039, /* 4, -13.0dB */
|
||||
0x0f00003c, /* 5, -12.5dB*/
|
||||
0x10000040, /* 6, -12.0dB*/
|
||||
0x11000044, /* 7, -11.5dB*/
|
||||
0x12000048, /* 8, -11.0dB*/
|
||||
0x1300004c, /* 9, -10.5dB*/
|
||||
0x14400051, /* 10, -10.0dB*/
|
||||
0x15800056, /* 11, -9.5dB*/
|
||||
0x16c0005b, /* 12, -9.0dB*/
|
||||
0x18000060, /* 13, -8.5dB*/
|
||||
0x19800066, /* 14, -8.0dB*/
|
||||
0x1b00006c, /* 15, -7.5dB*/
|
||||
0x1c800072, /* 16, -7.0dB*/
|
||||
0x1e400079, /* 17, -6.5dB*/
|
||||
0x20000080, /* 18, -6.0dB*/
|
||||
0x22000088, /* 19, -5.5dB*/
|
||||
0x24000090, /* 20, -5.0dB*/
|
||||
0x26000098, /* 21, -4.5dB*/
|
||||
0x288000a2, /* 22, -4.0dB*/
|
||||
0x2ac000ab, /* 23, -3.5dB*/
|
||||
0x2d4000b5, /* 24, -3.0dB*/
|
||||
0x300000c0, /* 25, -2.5dB*/
|
||||
0x32c000cb, /* 26, -2.0dB*/
|
||||
0x35c000d7, /* 27, -1.5dB*/
|
||||
0x390000e4, /* 28, -1.0dB*/
|
||||
0x3c8000f2, /* 29, -0.5dB*/
|
||||
0x40000100, /* 30, +0dB*/
|
||||
0x43c0010f, /* 31, +0.5dB*/
|
||||
0x47c0011f, /* 32, +1.0dB*/
|
||||
0x4c000130, /* 33, +1.5dB*/
|
||||
0x50800142, /* 34, +2.0dB*/
|
||||
0x55400155, /* 35, +2.5dB*/
|
||||
0x5a400169, /* 36, +3.0dB*/
|
||||
0x5fc0017f, /* 37, +3.5dB*/
|
||||
0x65400195, /* 38, +4.0dB*/
|
||||
0x6b8001ae, /* 39, +4.5dB*/
|
||||
0x71c001c7, /* 40, +5.0dB*/
|
||||
0x788001e2, /* 41, +5.5dB*/
|
||||
0x7f8001fe /* 42, +6.0dB*/
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = {
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= {
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
|
||||
};
|
||||
u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = {
|
||||
0x0CD, /*0 , -20dB*/
|
||||
0x0D9,
|
||||
0x0E6,
|
||||
0x0F3,
|
||||
0x102,
|
||||
0x111,
|
||||
0x121,
|
||||
0x132,
|
||||
0x144,
|
||||
0x158,
|
||||
0x16C,
|
||||
0x182,
|
||||
0x198,
|
||||
0x1B1,
|
||||
0x1CA,
|
||||
0x1E5,
|
||||
0x202,
|
||||
0x221,
|
||||
0x241,
|
||||
0x263,
|
||||
0x287,
|
||||
0x2AE,
|
||||
0x2D6,
|
||||
0x301,
|
||||
0x32F,
|
||||
0x35F,
|
||||
0x392,
|
||||
0x3C9,
|
||||
0x402,
|
||||
0x43F,
|
||||
0x47F,
|
||||
0x4C3,
|
||||
0x50C,
|
||||
0x558,
|
||||
0x5A9,
|
||||
0x5FF,
|
||||
0x65A,
|
||||
0x6BA,
|
||||
0x720,
|
||||
0x78C,
|
||||
0x7FF,
|
||||
};
|
||||
|
||||
|
||||
u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] =
|
||||
{
|
||||
0x081, /* 0, -12.0dB*/
|
||||
0x088, /* 1, -11.5dB*/
|
||||
0x090, /* 2, -11.0dB*/
|
||||
0x099, /* 3, -10.5dB*/
|
||||
0x0A2, /* 4, -10.0dB*/
|
||||
0x0AC, /* 5, -9.5dB*/
|
||||
0x0B6, /* 6, -9.0dB*/
|
||||
0x0C0, /*7, -8.5dB*/
|
||||
0x0CC, /* 8, -8.0dB*/
|
||||
0x0D8, /* 9, -7.5dB*/
|
||||
0x0E5, /* 10, -7.0dB*/
|
||||
0x0F2, /* 11, -6.5dB*/
|
||||
0x101, /* 12, -6.0dB*/
|
||||
0x110, /* 13, -5.5dB*/
|
||||
0x120, /* 14, -5.0dB*/
|
||||
0x131, /* 15, -4.5dB*/
|
||||
0x143, /* 16, -4.0dB*/
|
||||
0x156, /* 17, -3.5dB*/
|
||||
0x16A, /* 18, -3.0dB*/
|
||||
0x180, /* 19, -2.5dB*/
|
||||
0x197, /* 20, -2.0dB*/
|
||||
0x1AF, /* 21, -1.5dB*/
|
||||
0x1C8, /* 22, -1.0dB*/
|
||||
0x1E3, /* 23, -0.5dB*/
|
||||
0x200, /* 24, +0 dB*/
|
||||
0x21E, /* 25, +0.5dB*/
|
||||
0x23E, /* 26, +1.0dB*/
|
||||
0x261, /* 27, +1.5dB*/
|
||||
0x285,/* 28, +2.0dB*/
|
||||
0x2AB, /* 29, +2.5dB*/
|
||||
0x2D3, /*30, +3.0dB*/
|
||||
0x2FE, /* 31, +3.5dB*/
|
||||
0x32B, /* 32, +4.0dB*/
|
||||
0x35C, /* 33, +4.5dB*/
|
||||
0x38E, /* 34, +5.0dB*/
|
||||
0x3C4, /* 35, +5.5dB*/
|
||||
0x3FE /* 36, +6.0dB */
|
||||
};
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
|
||||
unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = {
|
||||
/* +6.0dB */ 0x7f8001fe,
|
||||
/* +5.5dB */ 0x788001e2,
|
||||
/* +5.0dB */ 0x71c001c7,
|
||||
/* +4.5dB */ 0x6b8001ae,
|
||||
/* +4.0dB */ 0x65400195,
|
||||
/* +3.5dB */ 0x5fc0017f,
|
||||
/* +3.0dB */ 0x5a400169,
|
||||
/* +2.5dB */ 0x55400155,
|
||||
/* +2.0dB */ 0x50800142,
|
||||
/* +1.5dB */ 0x4c000130,
|
||||
/* +1.0dB */ 0x47c0011f,
|
||||
/* +0.5dB */ 0x43c0010f,
|
||||
/* 0.0dB */ 0x40000100,
|
||||
/* -0.5dB */ 0x3c8000f2,
|
||||
/* -1.0dB */ 0x390000e4,
|
||||
/* -1.5dB */ 0x35c000d7,
|
||||
/* -2.0dB */ 0x32c000cb,
|
||||
/* -2.5dB */ 0x300000c0,
|
||||
/* -3.0dB */ 0x2d4000b5,
|
||||
/* -3.5dB */ 0x2ac000ab,
|
||||
/* -4.0dB */ 0x288000a2,
|
||||
/* -4.5dB */ 0x26000098,
|
||||
/* -5.0dB */ 0x24000090,
|
||||
/* -5.5dB */ 0x22000088,
|
||||
/* -6.0dB */ 0x20000080,
|
||||
/* -6.5dB */ 0x1a00006c,
|
||||
/* -7.0dB */ 0x1c800072,
|
||||
/* -7.5dB */ 0x18000060,
|
||||
/* -8.0dB */ 0x19800066,
|
||||
/* -8.5dB */ 0x15800056,
|
||||
/* -9.0dB */ 0x26c0005b,
|
||||
/* -9.5dB */ 0x14400051,
|
||||
/* -10.0dB */ 0x24400051,
|
||||
/* -10.5dB */ 0x1300004c,
|
||||
/* -11.0dB */ 0x12000048,
|
||||
/* -11.5dB */ 0x11000044,
|
||||
/* -12.0dB */ 0x10000040
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
if (!(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
|
||||
return;
|
||||
#endif
|
||||
|
||||
odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
|
||||
}
|
||||
|
||||
u1Byte
|
||||
getSwingIndex(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
u1Byte i = 0;
|
||||
u4Byte bbSwing;
|
||||
u4Byte swingTableSize;
|
||||
pu4Byte pSwingTable;
|
||||
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B
|
||||
|| pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B
|
||||
) {
|
||||
bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000);
|
||||
|
||||
pSwingTable = OFDMSwingTable_New;
|
||||
swingTableSize = OFDM_TABLE_SIZE;
|
||||
} else {
|
||||
#if ((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821)
|
||||
{
|
||||
bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A);
|
||||
pSwingTable = TxScalingTable_Jaguar;
|
||||
swingTableSize = TXSCALE_TABLE_SIZE;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
bbSwing = 0;
|
||||
pSwingTable = OFDMSwingTable;
|
||||
swingTableSize = OFDM_TABLE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < swingTableSize; ++i) {
|
||||
u4Byte tableValue = pSwingTable[i];
|
||||
|
||||
if (tableValue >= 0x100000 )
|
||||
tableValue >>= 22;
|
||||
if (bbSwing == tableValue)
|
||||
break;
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm);
|
||||
u1Byte p = 0;
|
||||
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
if(pDM_Odm->mp_mode == FALSE)
|
||||
pHalData->TxPowerTrackControl = TRUE;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
pRFCalibrateInfo->bTXPowerTracking = _TRUE;
|
||||
pRFCalibrateInfo->TXPowercount = 0;
|
||||
pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE;
|
||||
|
||||
if(pDM_Odm->mp_mode == FALSE)
|
||||
pRFCalibrateInfo->TxPowerTrackControl = _TRUE;
|
||||
else
|
||||
pRFCalibrateInfo->TxPowerTrackControl = _FALSE;
|
||||
|
||||
if(pDM_Odm->mp_mode == FALSE)
|
||||
pRFCalibrateInfo->TxPowerTrackControl = _TRUE;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl));
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#ifdef RTL8188E_SUPPORT
|
||||
{
|
||||
pRFCalibrateInfo->bTXPowerTracking = _TRUE;
|
||||
pRFCalibrateInfo->TXPowercount = 0;
|
||||
pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE;
|
||||
pRFCalibrateInfo->TxPowerTrackControl = _TRUE;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE;
|
||||
pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter;
|
||||
pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter;
|
||||
pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter;
|
||||
|
||||
if (pRFCalibrateInfo->DefaultBbSwingIndexFlag != TRUE) {
|
||||
/*The index of "0 dB" in SwingTable.*/
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) {
|
||||
pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex;
|
||||
pRFCalibrateInfo->DefaultCckIndex = 20;
|
||||
} else if (pDM_Odm->SupportICType == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
|
||||
pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/
|
||||
pRFCalibrateInfo->DefaultCckIndex = 20; /*CCK:-6dB*/
|
||||
} else if (pDM_Odm->SupportICType == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
|
||||
pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/
|
||||
pRFCalibrateInfo->DefaultCckIndex = 28; /*CCK: -6dB*/
|
||||
} else {
|
||||
pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex;
|
||||
pRFCalibrateInfo->DefaultCckIndex = 24;
|
||||
}
|
||||
pRFCalibrateInfo->DefaultBbSwingIndexFlag = TRUE;
|
||||
}
|
||||
|
||||
pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex;
|
||||
pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
|
||||
{
|
||||
pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = 0;
|
||||
pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0;
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = 0;
|
||||
}
|
||||
pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = 0;
|
||||
pRFCalibrateInfo->Modify_TxAGC_Value_CCK = 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_TXPowerTrackingCheck(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
|
||||
at the same time. In the stage2/3, we need to prive universal interface and merge all
|
||||
HW dynamic mechanism. */
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
switch (pDM_Odm->SupportPlatform)
|
||||
{
|
||||
case ODM_WIN:
|
||||
odm_TXPowerTrackingCheckMP(pDM_Odm);
|
||||
break;
|
||||
|
||||
case ODM_CE:
|
||||
odm_TXPowerTrackingCheckCE(pDM_Odm);
|
||||
break;
|
||||
|
||||
case ODM_AP:
|
||||
odm_TXPowerTrackingCheckAP(pDM_Odm);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckCE(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
|
||||
if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
|
||||
return;
|
||||
|
||||
if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) {
|
||||
|
||||
if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter)
|
||||
|| IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)
|
||||
|| IS_HARDWARE_TYPE_8703B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)
|
||||
|| IS_HARDWARE_TYPE_8821C(Adapter)
|
||||
) {
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03);
|
||||
} else {
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_OLD, bRFRegOffsetMask, 0x60);
|
||||
}
|
||||
|
||||
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
ODM_TXPowerTrackingCallback_ThermalMeter(Adapter);
|
||||
pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckMP(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
|
||||
if (ODM_CheckPowerStatus(Adapter) == FALSE)
|
||||
{
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
odm_TXPowerTrackingThermalMeterCheck(Adapter);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckAP(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
prtl8192cd_priv priv = pDM_Odm->priv;
|
||||
|
||||
return;
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterCheck(
|
||||
IN PADAPTER Adapter
|
||||
)
|
||||
{
|
||||
#ifndef AP_BUILD_WORKAROUND
|
||||
static u1Byte TM_Trigger = 0;
|
||||
|
||||
if (!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK)) {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
|
||||
("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (!TM_Trigger) {
|
||||
if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) ||
|
||||
IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter)
|
||||
|| IS_HARDWARE_TYPE_8703B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter))
|
||||
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
|
||||
else
|
||||
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
|
||||
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n"));
|
||||
|
||||
TM_Trigger = 1;
|
||||
return;
|
||||
} else {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n"));
|
||||
odm_TXPowerTrackingDirectCall(Adapter);
|
||||
TM_Trigger = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,334 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMPOWERTRACKING_H__
|
||||
#define __PHYDMPOWERTRACKING_H__
|
||||
|
||||
#define POWRTRACKING_VERSION "1.1"
|
||||
|
||||
#define DPK_DELTA_MAPPING_NUM 13
|
||||
#define index_mapping_HP_NUM 15
|
||||
#define OFDM_TABLE_SIZE 43
|
||||
#define CCK_TABLE_SIZE 33
|
||||
#define CCK_TABLE_SIZE_88F 21
|
||||
#define TXSCALE_TABLE_SIZE 37
|
||||
#define CCK_TABLE_SIZE_8723D 41
|
||||
|
||||
#define TXPWR_TRACK_TABLE_SIZE 30
|
||||
#define DELTA_SWINGIDX_SIZE 30
|
||||
#define DELTA_SWINTSSI_SIZE 61
|
||||
#define BAND_NUM 4
|
||||
|
||||
#define AVG_THERMAL_NUM 8
|
||||
#define HP_THERMAL_NUM 8
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_BB_REG_NUM_MAX 10
|
||||
|
||||
#define IQK_BB_REG_NUM 9
|
||||
|
||||
|
||||
|
||||
#define IQK_Matrix_REG_NUM 8
|
||||
#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
|
||||
|
||||
extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
|
||||
extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
|
||||
|
||||
extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
|
||||
extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16];
|
||||
extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16];
|
||||
extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D];
|
||||
|
||||
extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
|
||||
|
||||
// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table.
|
||||
static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
|
||||
static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
|
||||
|
||||
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
|
||||
|
||||
typedef struct _IQK_MATRIX_REGS_SETTING{
|
||||
BOOLEAN bIQKDone;
|
||||
s4Byte Value[3][IQK_Matrix_REG_NUM];
|
||||
BOOLEAN bBWIqkResultSaved[3];
|
||||
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
|
||||
|
||||
typedef struct ODM_RF_Calibration_Structure
|
||||
{
|
||||
//for tx power tracking
|
||||
|
||||
u4Byte RegA24; // for TempCCK
|
||||
s4Byte RegE94;
|
||||
s4Byte RegE9C;
|
||||
s4Byte RegEB4;
|
||||
s4Byte RegEBC;
|
||||
|
||||
u1Byte TXPowercount;
|
||||
BOOLEAN bTXPowerTrackingInit;
|
||||
BOOLEAN bTXPowerTracking;
|
||||
u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
|
||||
u1Byte TM_Trigger;
|
||||
u1Byte InternalPA5G[2]; //pathA / pathB
|
||||
|
||||
u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
|
||||
u1Byte ThermalValue;
|
||||
u1Byte ThermalValue_LCK;
|
||||
u1Byte ThermalValue_IQK;
|
||||
u1Byte ThermalValue_DPK;
|
||||
u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
|
||||
u1Byte ThermalValue_AVG_index;
|
||||
u1Byte ThermalValue_RxGain;
|
||||
u1Byte ThermalValue_Crystal;
|
||||
u1Byte ThermalValue_DPKstore;
|
||||
u1Byte ThermalValue_DPKtrack;
|
||||
BOOLEAN TxPowerTrackingInProgress;
|
||||
|
||||
BOOLEAN bReloadtxpowerindex;
|
||||
u1Byte bRfPiEnable;
|
||||
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
|
||||
|
||||
|
||||
//------------------------- Tx power Tracking -------------------------//
|
||||
u1Byte bCCKinCH14;
|
||||
u1Byte CCK_index;
|
||||
u1Byte OFDM_index[MAX_RF_PATH];
|
||||
s1Byte PowerIndexOffset[MAX_RF_PATH];
|
||||
s1Byte DeltaPowerIndex[MAX_RF_PATH];
|
||||
s1Byte DeltaPowerIndexLast[MAX_RF_PATH];
|
||||
BOOLEAN bTxPowerChanged;
|
||||
s1Byte XtalOffset;
|
||||
s1Byte XtalOffsetLast;
|
||||
|
||||
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
|
||||
u1Byte ThermalValue_HP_index;
|
||||
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
|
||||
u1Byte Delta_LCK;
|
||||
s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB
|
||||
u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE];
|
||||
s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
|
||||
|
||||
u1Byte BbSwingIdxOfdm[MAX_RF_PATH];
|
||||
u1Byte BbSwingIdxOfdmCurrent;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH];
|
||||
#else
|
||||
u1Byte BbSwingIdxOfdmBase;
|
||||
#endif
|
||||
BOOLEAN DefaultBbSwingIndexFlag;
|
||||
BOOLEAN BbSwingFlagOfdm;
|
||||
u1Byte BbSwingIdxCck;
|
||||
u1Byte BbSwingIdxCckCurrent;
|
||||
u1Byte BbSwingIdxCckBase;
|
||||
u1Byte DefaultOfdmIndex;
|
||||
u1Byte DefaultCckIndex;
|
||||
BOOLEAN BbSwingFlagCck;
|
||||
|
||||
s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH];
|
||||
s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH];
|
||||
s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH];
|
||||
s1Byte Remnant_CCKSwingIdx;
|
||||
s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */
|
||||
BOOLEAN Modify_TxAGC_Flag_PathA;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathB;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathC;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathD;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathA_CCK;
|
||||
|
||||
s1Byte KfreeOffset[MAX_RF_PATH];
|
||||
|
||||
//--------------------------------------------------------------------//
|
||||
|
||||
//for IQK
|
||||
u4Byte RegC04;
|
||||
u4Byte Reg874;
|
||||
u4Byte RegC08;
|
||||
u4Byte RegB68;
|
||||
u4Byte RegB6C;
|
||||
u4Byte Reg870;
|
||||
u4Byte Reg860;
|
||||
u4Byte Reg864;
|
||||
|
||||
BOOLEAN bIQKInitialized;
|
||||
BOOLEAN bLCKInProgress;
|
||||
BOOLEAN bAntennaDetected;
|
||||
BOOLEAN bNeedIQK;
|
||||
BOOLEAN bIQKInProgress;
|
||||
BOOLEAN bIQKPAoff;
|
||||
u1Byte Delta_IQK;
|
||||
u4Byte ADDA_backup[IQK_ADDA_REG_NUM];
|
||||
u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM];
|
||||
u4Byte IQK_BB_backup_recover[9];
|
||||
u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
|
||||
u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}
|
||||
u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}
|
||||
u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
u4Byte TxIQC_8723D[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u4Byte RxIQC_8723D[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
|
||||
u1Byte IQKstep;
|
||||
u1Byte Kcount;
|
||||
u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
|
||||
BOOLEAN isMPmode;
|
||||
|
||||
|
||||
|
||||
// <James> IQK time measurement
|
||||
u8Byte IQK_StartTime;
|
||||
u8Byte IQK_ProgressingTime;
|
||||
u8Byte IQK_TotalProgressingTime;
|
||||
|
||||
u4Byte LOK_Result;
|
||||
|
||||
//for APK
|
||||
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
|
||||
u1Byte bAPKdone;
|
||||
u1Byte bAPKThermalMeterIgnore;
|
||||
|
||||
// DPK
|
||||
BOOLEAN bDPKFail;
|
||||
u1Byte bDPdone;
|
||||
u1Byte bDPPathAOK;
|
||||
u1Byte bDPPathBOK;
|
||||
|
||||
u4Byte TxLOK[2];
|
||||
u4Byte DpkTxAGC;
|
||||
s4Byte DpkGain;
|
||||
u4Byte DpkThermal[4];
|
||||
s1Byte Modify_TxAGC_Value_OFDM;
|
||||
s1Byte Modify_TxAGC_Value_CCK;
|
||||
|
||||
/*Add by Yuchen for Kfree Phydm*/
|
||||
u1Byte RegRfKFreeEnable; /*for registry*/
|
||||
u1Byte RfKFreeEnable; /*for efuse enable check*/
|
||||
|
||||
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
|
||||
|
||||
|
||||
VOID
|
||||
ODM_TXPowerTrackingCheck(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckAP(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckMP(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckCE(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCallbackThermalMeter92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCallbackRXGainThermalMeter92D(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCallbackThermalMeter92D(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingDirectCall92C(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterCheck(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,784 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
//============================================================
|
||||
// Global var
|
||||
//============================================================
|
||||
|
||||
u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = {
|
||||
0x7f8001fe, // 0, +6.0dB
|
||||
0x788001e2, // 1, +5.5dB
|
||||
0x71c001c7, // 2, +5.0dB
|
||||
0x6b8001ae, // 3, +4.5dB
|
||||
0x65400195, // 4, +4.0dB
|
||||
0x5fc0017f, // 5, +3.5dB
|
||||
0x5a400169, // 6, +3.0dB
|
||||
0x55400155, // 7, +2.5dB
|
||||
0x50800142, // 8, +2.0dB
|
||||
0x4c000130, // 9, +1.5dB
|
||||
0x47c0011f, // 10, +1.0dB
|
||||
0x43c0010f, // 11, +0.5dB
|
||||
0x40000100, // 12, +0dB
|
||||
0x3c8000f2, // 13, -0.5dB
|
||||
0x390000e4, // 14, -1.0dB
|
||||
0x35c000d7, // 15, -1.5dB
|
||||
0x32c000cb, // 16, -2.0dB
|
||||
0x300000c0, // 17, -2.5dB
|
||||
0x2d4000b5, // 18, -3.0dB
|
||||
0x2ac000ab, // 19, -3.5dB
|
||||
0x288000a2, // 20, -4.0dB
|
||||
0x26000098, // 21, -4.5dB
|
||||
0x24000090, // 22, -5.0dB
|
||||
0x22000088, // 23, -5.5dB
|
||||
0x20000080, // 24, -6.0dB
|
||||
0x1e400079, // 25, -6.5dB
|
||||
0x1c800072, // 26, -7.0dB
|
||||
0x1b00006c, // 27. -7.5dB
|
||||
0x19800066, // 28, -8.0dB
|
||||
0x18000060, // 29, -8.5dB
|
||||
0x16c0005b, // 30, -9.0dB
|
||||
0x15800056, // 31, -9.5dB
|
||||
0x14400051, // 32, -10.0dB
|
||||
0x1300004c, // 33, -10.5dB
|
||||
0x12000048, // 34, -11.0dB
|
||||
0x11000044, // 35, -11.5dB
|
||||
0x10000040, // 36, -12.0dB
|
||||
};
|
||||
|
||||
u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB <== default
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB <== default
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB
|
||||
};
|
||||
|
||||
|
||||
u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = {
|
||||
0x0b40002d, // 0, -15.0dB
|
||||
0x0c000030, // 1, -14.5dB
|
||||
0x0cc00033, // 2, -14.0dB
|
||||
0x0d800036, // 3, -13.5dB
|
||||
0x0e400039, // 4, -13.0dB
|
||||
0x0f00003c, // 5, -12.5dB
|
||||
0x10000040, // 6, -12.0dB
|
||||
0x11000044, // 7, -11.5dB
|
||||
0x12000048, // 8, -11.0dB
|
||||
0x1300004c, // 9, -10.5dB
|
||||
0x14400051, // 10, -10.0dB
|
||||
0x15800056, // 11, -9.5dB
|
||||
0x16c0005b, // 12, -9.0dB
|
||||
0x18000060, // 13, -8.5dB
|
||||
0x19800066, // 14, -8.0dB
|
||||
0x1b00006c, // 15, -7.5dB
|
||||
0x1c800072, // 16, -7.0dB
|
||||
0x1e400079, // 17, -6.5dB
|
||||
0x20000080, // 18, -6.0dB
|
||||
0x22000088, // 19, -5.5dB
|
||||
0x24000090, // 20, -5.0dB
|
||||
0x26000098, // 21, -4.5dB
|
||||
0x288000a2, // 22, -4.0dB
|
||||
0x2ac000ab, // 23, -3.5dB
|
||||
0x2d4000b5, // 24, -3.0dB
|
||||
0x300000c0, // 25, -2.5dB
|
||||
0x32c000cb, // 26, -2.0dB
|
||||
0x35c000d7, // 27, -1.5dB
|
||||
0x390000e4, // 28, -1.0dB
|
||||
0x3c8000f2, // 29, -0.5dB
|
||||
0x40000100, // 30, +0dB
|
||||
0x43c0010f, // 31, +0.5dB
|
||||
0x47c0011f, // 32, +1.0dB
|
||||
0x4c000130, // 33, +1.5dB
|
||||
0x50800142, // 34, +2.0dB
|
||||
0x55400155, // 35, +2.5dB
|
||||
0x5a400169, // 36, +3.0dB
|
||||
0x5fc0017f, // 37, +3.5dB
|
||||
0x65400195, // 38, +4.0dB
|
||||
0x6b8001ae, // 39, +4.5dB
|
||||
0x71c001c7, // 40, +5.0dB
|
||||
0x788001e2, // 41, +5.5dB
|
||||
0x7f8001fe // 42, +6.0dB
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = {
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 20, -6.0dB
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB
|
||||
};
|
||||
|
||||
|
||||
u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= {
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB
|
||||
};
|
||||
u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = {
|
||||
0x0CD,
|
||||
0x0D9,
|
||||
0x0E6,
|
||||
0x0F3,
|
||||
0x102,
|
||||
0x111,
|
||||
0x121,
|
||||
0x132,
|
||||
0x144,
|
||||
0x158,
|
||||
0x16C,
|
||||
0x182,
|
||||
0x198,
|
||||
0x1B1,
|
||||
0x1CA,
|
||||
0x1E5,
|
||||
0x202,
|
||||
0x221,
|
||||
0x241,
|
||||
0x263,
|
||||
0x287,
|
||||
0x2AE,
|
||||
0x2D6,
|
||||
0x301,
|
||||
0x32F,
|
||||
0x35F,
|
||||
0x392,
|
||||
0x3C9,
|
||||
0x402,
|
||||
0x43F,
|
||||
0x47F,
|
||||
0x4C3,
|
||||
0x50C,
|
||||
0x558,
|
||||
0x5A9,
|
||||
0x5FF,
|
||||
0x65A,
|
||||
0x6BA,
|
||||
0x720,
|
||||
0x78C,
|
||||
0x7FF,
|
||||
};
|
||||
|
||||
|
||||
u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] =
|
||||
{
|
||||
0x081, // 0, -12.0dB
|
||||
0x088, // 1, -11.5dB
|
||||
0x090, // 2, -11.0dB
|
||||
0x099, // 3, -10.5dB
|
||||
0x0A2, // 4, -10.0dB
|
||||
0x0AC, // 5, -9.5dB
|
||||
0x0B6, // 6, -9.0dB
|
||||
0x0C0, // 7, -8.5dB
|
||||
0x0CC, // 8, -8.0dB
|
||||
0x0D8, // 9, -7.5dB
|
||||
0x0E5, // 10, -7.0dB
|
||||
0x0F2, // 11, -6.5dB
|
||||
0x101, // 12, -6.0dB
|
||||
0x110, // 13, -5.5dB
|
||||
0x120, // 14, -5.0dB
|
||||
0x131, // 15, -4.5dB
|
||||
0x143, // 16, -4.0dB
|
||||
0x156, // 17, -3.5dB
|
||||
0x16A, // 18, -3.0dB
|
||||
0x180, // 19, -2.5dB
|
||||
0x197, // 20, -2.0dB
|
||||
0x1AF, // 21, -1.5dB
|
||||
0x1C8, // 22, -1.0dB
|
||||
0x1E3, // 23, -0.5dB
|
||||
0x200, // 24, +0 dB
|
||||
0x21E, // 25, +0.5dB
|
||||
0x23E, // 26, +1.0dB
|
||||
0x261, // 27, +1.5dB
|
||||
0x285, // 28, +2.0dB
|
||||
0x2AB, // 29, +2.5dB
|
||||
0x2D3, // 30, +3.0dB
|
||||
0x2FE, // 31, +3.5dB
|
||||
0x32B, // 32, +4.0dB
|
||||
0x35C, // 33, +4.5dB
|
||||
0x38E, // 34, +5.0dB
|
||||
0x3C4, // 35, +5.5dB
|
||||
0x3FE // 36, +6.0dB
|
||||
};
|
||||
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
|
||||
unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = {
|
||||
/* +6.0dB */ 0x7f8001fe,
|
||||
/* +5.5dB */ 0x788001e2,
|
||||
/* +5.0dB */ 0x71c001c7,
|
||||
/* +4.5dB */ 0x6b8001ae,
|
||||
/* +4.0dB */ 0x65400195,
|
||||
/* +3.5dB */ 0x5fc0017f,
|
||||
/* +3.0dB */ 0x5a400169,
|
||||
/* +2.5dB */ 0x55400155,
|
||||
/* +2.0dB */ 0x50800142,
|
||||
/* +1.5dB */ 0x4c000130,
|
||||
/* +1.0dB */ 0x47c0011f,
|
||||
/* +0.5dB */ 0x43c0010f,
|
||||
/* 0.0dB */ 0x40000100,
|
||||
/* -0.5dB */ 0x3c8000f2,
|
||||
/* -1.0dB */ 0x390000e4,
|
||||
/* -1.5dB */ 0x35c000d7,
|
||||
/* -2.0dB */ 0x32c000cb,
|
||||
/* -2.5dB */ 0x300000c0,
|
||||
/* -3.0dB */ 0x2d4000b5,
|
||||
/* -3.5dB */ 0x2ac000ab,
|
||||
/* -4.0dB */ 0x288000a2,
|
||||
/* -4.5dB */ 0x26000098,
|
||||
/* -5.0dB */ 0x24000090,
|
||||
/* -5.5dB */ 0x22000088,
|
||||
/* -6.0dB */ 0x20000080,
|
||||
/* -6.5dB */ 0x1a00006c,
|
||||
/* -7.0dB */ 0x1c800072,
|
||||
/* -7.5dB */ 0x18000060,
|
||||
/* -8.0dB */ 0x19800066,
|
||||
/* -8.5dB */ 0x15800056,
|
||||
/* -9.0dB */ 0x26c0005b,
|
||||
/* -9.5dB */ 0x14400051,
|
||||
/* -10.0dB */ 0x24400051,
|
||||
/* -10.5dB */ 0x1300004c,
|
||||
/* -11.0dB */ 0x12000048,
|
||||
/* -11.5dB */ 0x11000044,
|
||||
/* -12.0dB */ 0x10000040
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
if (!(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
|
||||
return;
|
||||
#endif
|
||||
|
||||
odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
|
||||
}
|
||||
|
||||
u1Byte
|
||||
getSwingIndex(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
u1Byte i = 0;
|
||||
u4Byte bbSwing;
|
||||
u4Byte swingTableSize;
|
||||
pu4Byte pSwingTable;
|
||||
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B)
|
||||
{
|
||||
bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000);
|
||||
|
||||
pSwingTable = OFDMSwingTable_New;
|
||||
swingTableSize = OFDM_TABLE_SIZE;
|
||||
} else {
|
||||
bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A);
|
||||
pSwingTable = TxScalingTable_Jaguar;
|
||||
swingTableSize = TXSCALE_TABLE_SIZE;
|
||||
}
|
||||
|
||||
for (i = 0; i < swingTableSize; ++i) {
|
||||
u4Byte tableValue = pSwingTable[i];
|
||||
|
||||
if (tableValue >= 0x100000 )
|
||||
tableValue >>= 22;
|
||||
if (bbSwing == tableValue)
|
||||
break;
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm);
|
||||
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
u1Byte p = 0;
|
||||
|
||||
if(pDM_Odm->mp_mode == FALSE)
|
||||
pRFCalibrateInfo->TxPowerTrackControl = TRUE;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#ifdef CONFIG_RTL8188E
|
||||
{
|
||||
pRFCalibrateInfo->bTXPowerTracking = _TRUE;
|
||||
pRFCalibrateInfo->TXPowercount = 0;
|
||||
pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE;
|
||||
|
||||
if(pDM_Odm->mp_mode == FALSE)
|
||||
pRFCalibrateInfo->TxPowerTrackControl = _TRUE;
|
||||
|
||||
MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl);
|
||||
}
|
||||
#else
|
||||
{
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
|
||||
pdmpriv->bTXPowerTracking = _TRUE;
|
||||
pdmpriv->TXPowercount = 0;
|
||||
pdmpriv->bTXPowerTrackingInit = _FALSE;
|
||||
|
||||
if(pDM_Odm->mp_mode == FALSE)
|
||||
pdmpriv->TxPowerTrackControl = _TRUE;
|
||||
|
||||
MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
|
||||
|
||||
}
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#ifdef RTL8188E_SUPPORT
|
||||
{
|
||||
pRFCalibrateInfo->bTXPowerTracking = _TRUE;
|
||||
pRFCalibrateInfo->TXPowercount = 0;
|
||||
pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE;
|
||||
pRFCalibrateInfo->TxPowerTrackControl = _TRUE;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
pRFCalibrateInfo->TxPowerTrackControl = FALSE;
|
||||
#else
|
||||
pRFCalibrateInfo->TxPowerTrackControl = TRUE;
|
||||
#endif
|
||||
#else
|
||||
pRFCalibrateInfo->TxPowerTrackControl = TRUE;
|
||||
#endif
|
||||
|
||||
pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter;
|
||||
pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter;
|
||||
pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter;
|
||||
|
||||
if (pRFCalibrateInfo->DefaultBbSwingIndexFlag != TRUE) {
|
||||
/*The index of "0 dB" in SwingTable.*/
|
||||
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B ||
|
||||
pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) {
|
||||
pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex;
|
||||
pRFCalibrateInfo->DefaultCckIndex = 20;
|
||||
} else if (pDM_Odm->SupportICType == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
|
||||
pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/
|
||||
pRFCalibrateInfo->DefaultCckIndex = 20; /*CCK:-6dB*/
|
||||
} else if (pDM_Odm->SupportICType == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
|
||||
pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/
|
||||
pRFCalibrateInfo->DefaultCckIndex = 28; /*CCK: -6dB*/
|
||||
} else {
|
||||
pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex;
|
||||
pRFCalibrateInfo->DefaultCckIndex = 24;
|
||||
}
|
||||
pRFCalibrateInfo->DefaultBbSwingIndexFlag = TRUE;
|
||||
}
|
||||
|
||||
pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex;
|
||||
pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
|
||||
{
|
||||
pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex;
|
||||
pRFCalibrateInfo->DeltaPowerIndex[p] = 0;
|
||||
pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0;
|
||||
pRFCalibrateInfo->PowerIndexOffset[p] = 0;
|
||||
pRFCalibrateInfo->KfreeOffset[p] = 0;
|
||||
}
|
||||
pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = 0;
|
||||
pRFCalibrateInfo->Modify_TxAGC_Value_CCK = 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ODM_TXPowerTrackingCheck(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
|
||||
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
|
||||
// at the same time. In the stage2/3, we need to prive universal interface and merge all
|
||||
// HW dynamic mechanism.*/
|
||||
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
switch (pDM_Odm->SupportPlatform)
|
||||
{
|
||||
case ODM_WIN:
|
||||
odm_TXPowerTrackingCheckMP(pDM_Odm);
|
||||
break;
|
||||
|
||||
case ODM_CE:
|
||||
odm_TXPowerTrackingCheckCE(pDM_Odm);
|
||||
break;
|
||||
|
||||
case ODM_AP:
|
||||
odm_TXPowerTrackingCheckAP(pDM_Odm);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckCE(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
#if ((RTL8188F_SUPPORT == 1))
|
||||
rtl8192c_odm_CheckTXPowerTracking(Adapter);
|
||||
#endif
|
||||
|
||||
#if(RTL8188E_SUPPORT==1)
|
||||
|
||||
if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (!pRFCalibrateInfo->TM_Trigger) {
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
|
||||
/*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/
|
||||
|
||||
pRFCalibrateInfo->TM_Trigger = 1;
|
||||
return;
|
||||
|
||||
} else {
|
||||
/*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/
|
||||
odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter);
|
||||
pRFCalibrateInfo->TM_Trigger = 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckMP(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
|
||||
if (*pDM_Odm->pIsFcsModeEnable)
|
||||
return;
|
||||
|
||||
if (ODM_CheckPowerStatus(Adapter) == FALSE)
|
||||
{
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (IS_HARDWARE_TYPE_8821B(Adapter)) /* TODO: Don't Do PowerTracking*/
|
||||
return;
|
||||
|
||||
odm_TXPowerTrackingThermalMeterCheck(Adapter);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckAP(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingDirectCall(
|
||||
IN PADAPTER Adapter
|
||||
)
|
||||
{
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
|
||||
ODM_TXPowerTrackingCallback_ThermalMeter(Adapter);
|
||||
}
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterCheck(
|
||||
IN PADAPTER Adapter
|
||||
)
|
||||
{
|
||||
#ifndef AP_BUILD_WORKAROUND
|
||||
static u1Byte TM_Trigger = 0;
|
||||
|
||||
if (!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK))
|
||||
{
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
|
||||
("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (!TM_Trigger)
|
||||
{
|
||||
if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) ||
|
||||
IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8703B(Adapter)
|
||||
|| IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter))
|
||||
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
|
||||
else
|
||||
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
|
||||
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n"));
|
||||
|
||||
TM_Trigger = 1;
|
||||
return;
|
||||
} else {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n"));
|
||||
odm_TXPowerTrackingDirectCall(Adapter);
|
||||
TM_Trigger = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,299 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMPOWERTRACKING_H__
|
||||
#define __PHYDMPOWERTRACKING_H__
|
||||
|
||||
#define POWRTRACKING_VERSION "1.1"
|
||||
|
||||
#define DPK_DELTA_MAPPING_NUM 13
|
||||
#define index_mapping_HP_NUM 15
|
||||
#define TXSCALE_TABLE_SIZE 37
|
||||
#define CCK_TABLE_SIZE_8723D 41
|
||||
#define TXPWR_TRACK_TABLE_SIZE 30
|
||||
#define DELTA_SWINGIDX_SIZE 30
|
||||
#define DELTA_SWINTSSI_SIZE 61
|
||||
#define BAND_NUM 3
|
||||
#define MAX_RF_PATH 4
|
||||
#define CCK_TABLE_SIZE_88F 21
|
||||
|
||||
|
||||
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
|
||||
|
||||
#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
|
||||
#define AVG_THERMAL_NUM 8
|
||||
#define HP_THERMAL_NUM 8
|
||||
#define IQK_Matrix_REG_NUM 8
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
|
||||
#define IQK_BB_REG_NUM 9
|
||||
|
||||
|
||||
extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
|
||||
extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
|
||||
|
||||
extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
|
||||
extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16];
|
||||
extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16];
|
||||
extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16];
|
||||
extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D];
|
||||
|
||||
extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
|
||||
|
||||
// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table.
|
||||
static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
|
||||
static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
|
||||
|
||||
VOID
|
||||
ODM_TXPowerTrackingCheck(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckAP(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckMP(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingCheckCE(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
|
||||
VOID
|
||||
odm_TXPowerTrackingThermalMeterCheck(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
typedef struct _IQK_MATRIX_REGS_SETTING{
|
||||
BOOLEAN bIQKDone;
|
||||
s4Byte Value[3][IQK_Matrix_REG_NUM];
|
||||
BOOLEAN bBWIqkResultSaved[3];
|
||||
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
|
||||
|
||||
typedef struct ODM_RF_Calibration_Structure
|
||||
{
|
||||
//for tx power tracking
|
||||
|
||||
u4Byte RegA24; // for TempCCK
|
||||
s4Byte RegE94;
|
||||
s4Byte RegE9C;
|
||||
s4Byte RegEB4;
|
||||
s4Byte RegEBC;
|
||||
//u1Byte bTXPowerTracking;
|
||||
u1Byte TXPowercount;
|
||||
BOOLEAN bTXPowerTrackingInit;
|
||||
BOOLEAN bTXPowerTracking;
|
||||
u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
|
||||
u1Byte TM_Trigger;
|
||||
u1Byte InternalPA5G[2]; //pathA / pathB
|
||||
|
||||
u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
|
||||
u1Byte ThermalValue;
|
||||
u1Byte ThermalValue_LCK;
|
||||
u1Byte ThermalValue_IQK;
|
||||
u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
|
||||
u1Byte ThermalValue_AVG_index;
|
||||
u1Byte ThermalValue_RxGain;
|
||||
|
||||
BOOLEAN bReloadtxpowerindex;
|
||||
u1Byte bRfPiEnable;
|
||||
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
|
||||
|
||||
|
||||
//------------------------- Tx power Tracking -------------------------//
|
||||
u1Byte bCCKinCH14;
|
||||
u1Byte CCK_index;
|
||||
u1Byte OFDM_index[MAX_RF_PATH];
|
||||
s1Byte PowerIndexOffset[MAX_RF_PATH];
|
||||
s1Byte DeltaPowerIndex[MAX_RF_PATH];
|
||||
s1Byte DeltaPowerIndexLast[MAX_RF_PATH];
|
||||
BOOLEAN bTxPowerChanged;
|
||||
s1Byte XtalOffset;
|
||||
s1Byte XtalOffsetLast;
|
||||
|
||||
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
|
||||
u1Byte ThermalValue_HP_index;
|
||||
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
|
||||
u1Byte Delta_LCK;
|
||||
s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB
|
||||
u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE];
|
||||
s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
|
||||
u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
|
||||
|
||||
u1Byte BbSwingIdxOfdm[MAX_RF_PATH];
|
||||
u1Byte BbSwingIdxOfdmCurrent;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH];
|
||||
#else
|
||||
u1Byte BbSwingIdxOfdmBase;
|
||||
#endif
|
||||
BOOLEAN DefaultBbSwingIndexFlag;
|
||||
BOOLEAN BbSwingFlagOfdm;
|
||||
u1Byte BbSwingIdxCck;
|
||||
u1Byte BbSwingIdxCckCurrent;
|
||||
u1Byte BbSwingIdxCckBase;
|
||||
u1Byte DefaultOfdmIndex;
|
||||
u1Byte DefaultCckIndex;
|
||||
BOOLEAN BbSwingFlagCck;
|
||||
|
||||
s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH];
|
||||
s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH];
|
||||
s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH];
|
||||
s1Byte Remnant_CCKSwingIdx;
|
||||
s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */
|
||||
BOOLEAN Modify_TxAGC_Flag_PathA;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathB;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathC;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathD;
|
||||
BOOLEAN Modify_TxAGC_Flag_PathA_CCK;
|
||||
|
||||
s1Byte KfreeOffset[MAX_RF_PATH];
|
||||
|
||||
//--------------------------------------------------------------------//
|
||||
|
||||
//for IQK
|
||||
u4Byte RegC04;
|
||||
u4Byte Reg874;
|
||||
u4Byte RegC08;
|
||||
u4Byte RegB68;
|
||||
u4Byte RegB6C;
|
||||
u4Byte Reg870;
|
||||
u4Byte Reg860;
|
||||
u4Byte Reg864;
|
||||
|
||||
BOOLEAN bIQKInitialized;
|
||||
BOOLEAN bLCKInProgress;
|
||||
BOOLEAN bAntennaDetected;
|
||||
BOOLEAN bNeedIQK;
|
||||
BOOLEAN bIQKInProgress;
|
||||
BOOLEAN bIQKPAoff;
|
||||
u1Byte Delta_IQK;
|
||||
u4Byte ADDA_backup[IQK_ADDA_REG_NUM];
|
||||
u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM];
|
||||
u4Byte IQK_BB_backup_recover[9];
|
||||
u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
|
||||
u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
|
||||
u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
|
||||
u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
u4Byte TxIQC_8723D[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u4Byte RxIQC_8723D[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
|
||||
u8Byte IQK_StartTime;
|
||||
u8Byte IQK_TotalProgressingTime;
|
||||
u8Byte IQK_ProgressingTime;
|
||||
u4Byte LOK_Result;
|
||||
u1Byte IQKstep;
|
||||
u1Byte Kcount;
|
||||
u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
|
||||
BOOLEAN isMPmode;
|
||||
|
||||
//for APK
|
||||
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
|
||||
u1Byte bAPKdone;
|
||||
u1Byte bAPKThermalMeterIgnore;
|
||||
|
||||
// DPK
|
||||
BOOLEAN bDPKFail;
|
||||
u1Byte bDPdone;
|
||||
u1Byte bDPPathAOK;
|
||||
u1Byte bDPPathBOK;
|
||||
|
||||
u4Byte TxLOK[2];
|
||||
u4Byte DpkTxAGC;
|
||||
s4Byte DpkGain;
|
||||
u4Byte DpkThermal[4];
|
||||
|
||||
s1Byte Modify_TxAGC_Value_OFDM;
|
||||
s1Byte Modify_TxAGC_Value_CCK;
|
||||
|
||||
/*Add by Yuchen for Kfree Phydm*/
|
||||
u1Byte RegRfKFreeEnable; /*for registry*/
|
||||
u1Byte RfKFreeEnable; /*for efuse enable check*/
|
||||
|
||||
HALMAC_PWR_TRACKING_OPTION HALMAC_PWR_TRACKING_INFO;
|
||||
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,697 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __PHYDMPREDEFINE_H__
|
||||
#define __PHYDMPREDEFINE_H__
|
||||
|
||||
//1 ============================================================
|
||||
//1 Definition
|
||||
//1 ============================================================
|
||||
|
||||
#define PHYDM_CODE_BASE "PHYDM_010"
|
||||
#define PHYDM_RELEASE_DATE "00000000"
|
||||
|
||||
//Max path of IC
|
||||
#define MAX_PATH_NUM_8188E 1
|
||||
#define MAX_PATH_NUM_8192E 2
|
||||
#define MAX_PATH_NUM_8723B 1
|
||||
#define MAX_PATH_NUM_8812A 2
|
||||
#define MAX_PATH_NUM_8821A 1
|
||||
#define MAX_PATH_NUM_8814A 4
|
||||
#define MAX_PATH_NUM_8822B 2
|
||||
#define MAX_PATH_NUM_8821B 2
|
||||
#define MAX_PATH_NUM_8703B 1
|
||||
#define MAX_PATH_NUM_8188F 1
|
||||
#define MAX_PATH_NUM_8723D 1
|
||||
#define MAX_PATH_NUM_8197F 2
|
||||
#define MAX_PATH_NUM_8821C 1
|
||||
|
||||
//Max RF path
|
||||
#define ODM_RF_PATH_MAX 2
|
||||
#define ODM_RF_PATH_MAX_JAGUAR 4
|
||||
|
||||
/*Bit define path*/
|
||||
#define PHYDM_A BIT0
|
||||
#define PHYDM_B BIT1
|
||||
#define PHYDM_C BIT2
|
||||
#define PHYDM_D BIT3
|
||||
#define PHYDM_AB (BIT0 | BIT1)
|
||||
#define PHYDM_AC (BIT0 | BIT2)
|
||||
#define PHYDM_AD (BIT0 | BIT3)
|
||||
#define PHYDM_BC (BIT1 | BIT2)
|
||||
#define PHYDM_BD (BIT1 | BIT3)
|
||||
#define PHYDM_CD (BIT2 | BIT3)
|
||||
#define PHYDM_ABC (BIT0 | BIT1 | BIT2)
|
||||
#define PHYDM_ABD (BIT0 | BIT1 | BIT3)
|
||||
#define PHYDM_ACD (BIT0 | BIT2 | BIT3)
|
||||
#define PHYDM_BCD (BIT1 | BIT2 | BIT3)
|
||||
#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3)
|
||||
|
||||
//number of entry
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
#define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of AsocEntry[].*/
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
|
||||
#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#define ASSOCIATE_ENTRY_NUM NUM_STAT
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1)
|
||||
#else
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1)
|
||||
#endif
|
||||
|
||||
/* -----MGN rate--------------------------------- */
|
||||
|
||||
enum ODM_MGN_RATE {
|
||||
ODM_MGN_1M = 0x02,
|
||||
ODM_MGN_2M = 0x04,
|
||||
ODM_MGN_5_5M = 0x0B,
|
||||
ODM_MGN_6M = 0x0C,
|
||||
ODM_MGN_9M = 0x12,
|
||||
ODM_MGN_11M = 0x16,
|
||||
ODM_MGN_12M = 0x18,
|
||||
ODM_MGN_18M = 0x24,
|
||||
ODM_MGN_24M = 0x30,
|
||||
ODM_MGN_36M = 0x48,
|
||||
ODM_MGN_48M = 0x60,
|
||||
ODM_MGN_54M = 0x6C,
|
||||
ODM_MGN_MCS32 = 0x7F,
|
||||
ODM_MGN_MCS0,
|
||||
ODM_MGN_MCS1,
|
||||
ODM_MGN_MCS2,
|
||||
ODM_MGN_MCS3,
|
||||
ODM_MGN_MCS4,
|
||||
ODM_MGN_MCS5,
|
||||
ODM_MGN_MCS6,
|
||||
ODM_MGN_MCS7,
|
||||
ODM_MGN_MCS8,
|
||||
ODM_MGN_MCS9,
|
||||
ODM_MGN_MCS10,
|
||||
ODM_MGN_MCS11,
|
||||
ODM_MGN_MCS12,
|
||||
ODM_MGN_MCS13,
|
||||
ODM_MGN_MCS14,
|
||||
ODM_MGN_MCS15,
|
||||
ODM_MGN_MCS16,
|
||||
ODM_MGN_MCS17,
|
||||
ODM_MGN_MCS18,
|
||||
ODM_MGN_MCS19,
|
||||
ODM_MGN_MCS20,
|
||||
ODM_MGN_MCS21,
|
||||
ODM_MGN_MCS22,
|
||||
ODM_MGN_MCS23,
|
||||
ODM_MGN_MCS24,
|
||||
ODM_MGN_MCS25,
|
||||
ODM_MGN_MCS26,
|
||||
ODM_MGN_MCS27,
|
||||
ODM_MGN_MCS28,
|
||||
ODM_MGN_MCS29,
|
||||
ODM_MGN_MCS30,
|
||||
ODM_MGN_MCS31,
|
||||
ODM_MGN_VHT1SS_MCS0,
|
||||
ODM_MGN_VHT1SS_MCS1,
|
||||
ODM_MGN_VHT1SS_MCS2,
|
||||
ODM_MGN_VHT1SS_MCS3,
|
||||
ODM_MGN_VHT1SS_MCS4,
|
||||
ODM_MGN_VHT1SS_MCS5,
|
||||
ODM_MGN_VHT1SS_MCS6,
|
||||
ODM_MGN_VHT1SS_MCS7,
|
||||
ODM_MGN_VHT1SS_MCS8,
|
||||
ODM_MGN_VHT1SS_MCS9,
|
||||
ODM_MGN_VHT2SS_MCS0,
|
||||
ODM_MGN_VHT2SS_MCS1,
|
||||
ODM_MGN_VHT2SS_MCS2,
|
||||
ODM_MGN_VHT2SS_MCS3,
|
||||
ODM_MGN_VHT2SS_MCS4,
|
||||
ODM_MGN_VHT2SS_MCS5,
|
||||
ODM_MGN_VHT2SS_MCS6,
|
||||
ODM_MGN_VHT2SS_MCS7,
|
||||
ODM_MGN_VHT2SS_MCS8,
|
||||
ODM_MGN_VHT2SS_MCS9,
|
||||
ODM_MGN_VHT3SS_MCS0,
|
||||
ODM_MGN_VHT3SS_MCS1,
|
||||
ODM_MGN_VHT3SS_MCS2,
|
||||
ODM_MGN_VHT3SS_MCS3,
|
||||
ODM_MGN_VHT3SS_MCS4,
|
||||
ODM_MGN_VHT3SS_MCS5,
|
||||
ODM_MGN_VHT3SS_MCS6,
|
||||
ODM_MGN_VHT3SS_MCS7,
|
||||
ODM_MGN_VHT3SS_MCS8,
|
||||
ODM_MGN_VHT3SS_MCS9,
|
||||
ODM_MGN_VHT4SS_MCS0,
|
||||
ODM_MGN_VHT4SS_MCS1,
|
||||
ODM_MGN_VHT4SS_MCS2,
|
||||
ODM_MGN_VHT4SS_MCS3,
|
||||
ODM_MGN_VHT4SS_MCS4,
|
||||
ODM_MGN_VHT4SS_MCS5,
|
||||
ODM_MGN_VHT4SS_MCS6,
|
||||
ODM_MGN_VHT4SS_MCS7,
|
||||
ODM_MGN_VHT4SS_MCS8,
|
||||
ODM_MGN_VHT4SS_MCS9,
|
||||
ODM_MGN_UNKNOWN
|
||||
};
|
||||
|
||||
#define ODM_MGN_MCS0_SG 0xc0
|
||||
#define ODM_MGN_MCS1_SG 0xc1
|
||||
#define ODM_MGN_MCS2_SG 0xc2
|
||||
#define ODM_MGN_MCS3_SG 0xc3
|
||||
#define ODM_MGN_MCS4_SG 0xc4
|
||||
#define ODM_MGN_MCS5_SG 0xc5
|
||||
#define ODM_MGN_MCS6_SG 0xc6
|
||||
#define ODM_MGN_MCS7_SG 0xc7
|
||||
#define ODM_MGN_MCS8_SG 0xc8
|
||||
#define ODM_MGN_MCS9_SG 0xc9
|
||||
#define ODM_MGN_MCS10_SG 0xca
|
||||
#define ODM_MGN_MCS11_SG 0xcb
|
||||
#define ODM_MGN_MCS12_SG 0xcc
|
||||
#define ODM_MGN_MCS13_SG 0xcd
|
||||
#define ODM_MGN_MCS14_SG 0xce
|
||||
#define ODM_MGN_MCS15_SG 0xcf
|
||||
|
||||
/* -----DESC rate--------------------------------- */
|
||||
|
||||
#define ODM_RATEMCS15_SG 0x1c
|
||||
#define ODM_RATEMCS32 0x20
|
||||
|
||||
|
||||
// CCK Rates, TxHT = 0
|
||||
#define ODM_RATE1M 0x00
|
||||
#define ODM_RATE2M 0x01
|
||||
#define ODM_RATE5_5M 0x02
|
||||
#define ODM_RATE11M 0x03
|
||||
// OFDM Rates, TxHT = 0
|
||||
#define ODM_RATE6M 0x04
|
||||
#define ODM_RATE9M 0x05
|
||||
#define ODM_RATE12M 0x06
|
||||
#define ODM_RATE18M 0x07
|
||||
#define ODM_RATE24M 0x08
|
||||
#define ODM_RATE36M 0x09
|
||||
#define ODM_RATE48M 0x0A
|
||||
#define ODM_RATE54M 0x0B
|
||||
// MCS Rates, TxHT = 1
|
||||
#define ODM_RATEMCS0 0x0C
|
||||
#define ODM_RATEMCS1 0x0D
|
||||
#define ODM_RATEMCS2 0x0E
|
||||
#define ODM_RATEMCS3 0x0F
|
||||
#define ODM_RATEMCS4 0x10
|
||||
#define ODM_RATEMCS5 0x11
|
||||
#define ODM_RATEMCS6 0x12
|
||||
#define ODM_RATEMCS7 0x13
|
||||
#define ODM_RATEMCS8 0x14
|
||||
#define ODM_RATEMCS9 0x15
|
||||
#define ODM_RATEMCS10 0x16
|
||||
#define ODM_RATEMCS11 0x17
|
||||
#define ODM_RATEMCS12 0x18
|
||||
#define ODM_RATEMCS13 0x19
|
||||
#define ODM_RATEMCS14 0x1A
|
||||
#define ODM_RATEMCS15 0x1B
|
||||
#define ODM_RATEMCS16 0x1C
|
||||
#define ODM_RATEMCS17 0x1D
|
||||
#define ODM_RATEMCS18 0x1E
|
||||
#define ODM_RATEMCS19 0x1F
|
||||
#define ODM_RATEMCS20 0x20
|
||||
#define ODM_RATEMCS21 0x21
|
||||
#define ODM_RATEMCS22 0x22
|
||||
#define ODM_RATEMCS23 0x23
|
||||
#define ODM_RATEMCS24 0x24
|
||||
#define ODM_RATEMCS25 0x25
|
||||
#define ODM_RATEMCS26 0x26
|
||||
#define ODM_RATEMCS27 0x27
|
||||
#define ODM_RATEMCS28 0x28
|
||||
#define ODM_RATEMCS29 0x29
|
||||
#define ODM_RATEMCS30 0x2A
|
||||
#define ODM_RATEMCS31 0x2B
|
||||
#define ODM_RATEVHTSS1MCS0 0x2C
|
||||
#define ODM_RATEVHTSS1MCS1 0x2D
|
||||
#define ODM_RATEVHTSS1MCS2 0x2E
|
||||
#define ODM_RATEVHTSS1MCS3 0x2F
|
||||
#define ODM_RATEVHTSS1MCS4 0x30
|
||||
#define ODM_RATEVHTSS1MCS5 0x31
|
||||
#define ODM_RATEVHTSS1MCS6 0x32
|
||||
#define ODM_RATEVHTSS1MCS7 0x33
|
||||
#define ODM_RATEVHTSS1MCS8 0x34
|
||||
#define ODM_RATEVHTSS1MCS9 0x35
|
||||
#define ODM_RATEVHTSS2MCS0 0x36
|
||||
#define ODM_RATEVHTSS2MCS1 0x37
|
||||
#define ODM_RATEVHTSS2MCS2 0x38
|
||||
#define ODM_RATEVHTSS2MCS3 0x39
|
||||
#define ODM_RATEVHTSS2MCS4 0x3A
|
||||
#define ODM_RATEVHTSS2MCS5 0x3B
|
||||
#define ODM_RATEVHTSS2MCS6 0x3C
|
||||
#define ODM_RATEVHTSS2MCS7 0x3D
|
||||
#define ODM_RATEVHTSS2MCS8 0x3E
|
||||
#define ODM_RATEVHTSS2MCS9 0x3F
|
||||
#define ODM_RATEVHTSS3MCS0 0x40
|
||||
#define ODM_RATEVHTSS3MCS1 0x41
|
||||
#define ODM_RATEVHTSS3MCS2 0x42
|
||||
#define ODM_RATEVHTSS3MCS3 0x43
|
||||
#define ODM_RATEVHTSS3MCS4 0x44
|
||||
#define ODM_RATEVHTSS3MCS5 0x45
|
||||
#define ODM_RATEVHTSS3MCS6 0x46
|
||||
#define ODM_RATEVHTSS3MCS7 0x47
|
||||
#define ODM_RATEVHTSS3MCS8 0x48
|
||||
#define ODM_RATEVHTSS3MCS9 0x49
|
||||
#define ODM_RATEVHTSS4MCS0 0x4A
|
||||
#define ODM_RATEVHTSS4MCS1 0x4B
|
||||
#define ODM_RATEVHTSS4MCS2 0x4C
|
||||
#define ODM_RATEVHTSS4MCS3 0x4D
|
||||
#define ODM_RATEVHTSS4MCS4 0x4E
|
||||
#define ODM_RATEVHTSS4MCS5 0x4F
|
||||
#define ODM_RATEVHTSS4MCS6 0x50
|
||||
#define ODM_RATEVHTSS4MCS7 0x51
|
||||
#define ODM_RATEVHTSS4MCS8 0x52
|
||||
#define ODM_RATEVHTSS4MCS9 0x53
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
|
||||
#else
|
||||
#if (RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1)
|
||||
#elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1)
|
||||
#elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1)
|
||||
#elif (RTL8812A_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1)
|
||||
#elif(RTL8814A_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1)
|
||||
#else
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define CONFIG_SFW_SUPPORTED
|
||||
#endif
|
||||
|
||||
//1 ============================================================
|
||||
//1 enumeration
|
||||
//1 ============================================================
|
||||
|
||||
|
||||
// ODM_CMNINFO_INTERFACE
|
||||
typedef enum tag_ODM_Support_Interface_Definition
|
||||
{
|
||||
ODM_ITRF_PCIE = 0x1,
|
||||
ODM_ITRF_USB = 0x2,
|
||||
ODM_ITRF_SDIO = 0x4,
|
||||
ODM_ITRF_ALL = 0x7,
|
||||
}ODM_INTERFACE_E;
|
||||
|
||||
// ODM_CMNINFO_IC_TYPE
|
||||
typedef enum tag_ODM_Support_IC_Type_Definition
|
||||
{
|
||||
ODM_RTL8188E = BIT0,
|
||||
ODM_RTL8812 = BIT1,
|
||||
ODM_RTL8821 = BIT2,
|
||||
ODM_RTL8192E = BIT3,
|
||||
ODM_RTL8723B = BIT4,
|
||||
ODM_RTL8814A = BIT5,
|
||||
ODM_RTL8881A = BIT6,
|
||||
ODM_RTL8822B = BIT7,
|
||||
ODM_RTL8703B = BIT8,
|
||||
ODM_RTL8195A = BIT9,
|
||||
ODM_RTL8188F = BIT10,
|
||||
ODM_RTL8723D = BIT11,
|
||||
ODM_RTL8197F = BIT12,
|
||||
ODM_RTL8821C = BIT13,
|
||||
ODM_RTL8814B = BIT14,
|
||||
ODM_RTL8198F = BIT15
|
||||
}ODM_IC_TYPE_E;
|
||||
|
||||
|
||||
#define ODM_IC_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195A)
|
||||
#define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B)
|
||||
#define ODM_IC_3SS (ODM_RTL8814A)
|
||||
#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F)
|
||||
|
||||
|
||||
#define ODM_IC_11N_SERIES (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F)
|
||||
#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B|ODM_RTL8821C)
|
||||
#define ODM_IC_11AC_1_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8881A)
|
||||
#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8821C)
|
||||
#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C)
|
||||
#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F)
|
||||
#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8821C)
|
||||
#define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F|ODM_RTL8822B|ODM_RTL8723D|ODM_RTL8821C)
|
||||
|
||||
#define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F)
|
||||
#define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C)
|
||||
|
||||
#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
#ifdef RTK_AC_SUPPORT
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#else
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_CONFIG_BT_COEXIST 0
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_CONFIG_BT_COEXIST 1
|
||||
|
||||
#else
|
||||
|
||||
#if ((RTL8188E_SUPPORT == 1) || \
|
||||
(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \
|
||||
(RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 0
|
||||
#else
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 0
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#define ODM_CONFIG_BT_COEXIST 1
|
||||
#else
|
||||
#define ODM_CONFIG_BT_COEXIST 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
#define PHYDM_LA_MODE_SUPPORT 1
|
||||
#else
|
||||
#define PHYDM_LA_MODE_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
|
||||
#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1
|
||||
#else
|
||||
#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0
|
||||
#endif
|
||||
|
||||
//ODM_CMNINFO_CUT_VER
|
||||
typedef enum tag_ODM_Cut_Version_Definition
|
||||
{
|
||||
ODM_CUT_A = 0,
|
||||
ODM_CUT_B = 1,
|
||||
ODM_CUT_C = 2,
|
||||
ODM_CUT_D = 3,
|
||||
ODM_CUT_E = 4,
|
||||
ODM_CUT_F = 5,
|
||||
|
||||
ODM_CUT_I = 8,
|
||||
ODM_CUT_J = 9,
|
||||
ODM_CUT_K = 10,
|
||||
ODM_CUT_TEST = 15,
|
||||
}ODM_CUT_VERSION_E;
|
||||
|
||||
// ODM_CMNINFO_FAB_VER
|
||||
typedef enum tag_ODM_Fab_Version_Definition
|
||||
{
|
||||
ODM_TSMC = 0,
|
||||
ODM_UMC = 1,
|
||||
}ODM_FAB_E;
|
||||
|
||||
// ODM_CMNINFO_RF_TYPE
|
||||
//
|
||||
// For example 1T2R (A+AB = BIT0|BIT4|BIT5)
|
||||
//
|
||||
typedef enum tag_ODM_RF_Path_Bit_Definition
|
||||
{
|
||||
ODM_RF_A = BIT0,
|
||||
ODM_RF_B = BIT1,
|
||||
ODM_RF_C = BIT2,
|
||||
ODM_RF_D = BIT3,
|
||||
}ODM_RF_PATH_E;
|
||||
|
||||
typedef enum tag_PHYDM_RF_TX_NUM {
|
||||
ODM_1T = 1,
|
||||
ODM_2T = 2,
|
||||
ODM_3T = 3,
|
||||
ODM_4T = 4,
|
||||
} ODM_RF_TX_NUM_E;
|
||||
|
||||
typedef enum tag_ODM_RF_Type_Definition {
|
||||
ODM_1T1R,
|
||||
ODM_1T2R,
|
||||
ODM_2T2R,
|
||||
ODM_2T2R_GREEN,
|
||||
ODM_2T3R,
|
||||
ODM_2T4R,
|
||||
ODM_3T3R,
|
||||
ODM_3T4R,
|
||||
ODM_4T4R,
|
||||
ODM_XTXR
|
||||
}ODM_RF_TYPE_E;
|
||||
|
||||
|
||||
typedef enum tag_ODM_MAC_PHY_Mode_Definition
|
||||
{
|
||||
ODM_SMSP = 0,
|
||||
ODM_DMSP = 1,
|
||||
ODM_DMDP = 2,
|
||||
}ODM_MAC_PHY_MODE_E;
|
||||
|
||||
|
||||
typedef enum tag_BT_Coexist_Definition
|
||||
{
|
||||
ODM_BT_BUSY = 1,
|
||||
ODM_BT_ON = 2,
|
||||
ODM_BT_OFF = 3,
|
||||
ODM_BT_NONE = 4,
|
||||
}ODM_BT_COEXIST_E;
|
||||
|
||||
// ODM_CMNINFO_OP_MODE
|
||||
typedef enum tag_Operation_Mode_Definition
|
||||
{
|
||||
ODM_NO_LINK = BIT0,
|
||||
ODM_LINK = BIT1,
|
||||
ODM_SCAN = BIT2,
|
||||
ODM_POWERSAVE = BIT3,
|
||||
ODM_AP_MODE = BIT4,
|
||||
ODM_CLIENT_MODE = BIT5,
|
||||
ODM_AD_HOC = BIT6,
|
||||
ODM_WIFI_DIRECT = BIT7,
|
||||
ODM_WIFI_DISPLAY = BIT8,
|
||||
}ODM_OPERATION_MODE_E;
|
||||
|
||||
// ODM_CMNINFO_WM_MODE
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
typedef enum tag_Wireless_Mode_Definition
|
||||
{
|
||||
ODM_WM_UNKNOW = 0x0,
|
||||
ODM_WM_B = BIT0,
|
||||
ODM_WM_G = BIT1,
|
||||
ODM_WM_A = BIT2,
|
||||
ODM_WM_N24G = BIT3,
|
||||
ODM_WM_N5G = BIT4,
|
||||
ODM_WM_AUTO = BIT5,
|
||||
ODM_WM_AC = BIT6,
|
||||
}ODM_WIRELESS_MODE_E;
|
||||
#else
|
||||
typedef enum tag_Wireless_Mode_Definition
|
||||
{
|
||||
ODM_WM_UNKNOWN = 0x00,/*0x0*/
|
||||
ODM_WM_A = BIT0, /* 0x1*/
|
||||
ODM_WM_B = BIT1, /* 0x2*/
|
||||
ODM_WM_G = BIT2,/* 0x4*/
|
||||
ODM_WM_AUTO = BIT3,/* 0x8*/
|
||||
ODM_WM_N24G = BIT4,/* 0x10*/
|
||||
ODM_WM_N5G = BIT5,/* 0x20*/
|
||||
ODM_WM_AC_5G = BIT6,/* 0x40*/
|
||||
ODM_WM_AC_24G = BIT7,/* 0x80*/
|
||||
ODM_WM_AC_ONLY = BIT8,/* 0x100*/
|
||||
ODM_WM_MAX = BIT11/* 0x800*/
|
||||
|
||||
}ODM_WIRELESS_MODE_E;
|
||||
#endif
|
||||
|
||||
// ODM_CMNINFO_BAND
|
||||
typedef enum tag_Band_Type_Definition
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
ODM_BAND_2_4G = BIT0,
|
||||
ODM_BAND_5G = BIT1,
|
||||
#else
|
||||
ODM_BAND_2_4G = 0,
|
||||
ODM_BAND_5G,
|
||||
ODM_BAND_ON_BOTH,
|
||||
ODM_BANDMAX
|
||||
#endif
|
||||
}ODM_BAND_TYPE_E;
|
||||
|
||||
|
||||
// ODM_CMNINFO_SEC_CHNL_OFFSET
|
||||
typedef enum tag_Secondary_Channel_Offset_Definition {
|
||||
|
||||
PHYDM_DONT_CARE = 0,
|
||||
PHYDM_BELOW = 1,
|
||||
PHYDM_ABOVE = 2
|
||||
} PHYDM_SEC_CHNL_OFFSET_E;
|
||||
|
||||
// ODM_CMNINFO_SEC_MODE
|
||||
typedef enum tag_Security_Definition
|
||||
{
|
||||
ODM_SEC_OPEN = 0,
|
||||
ODM_SEC_WEP40 = 1,
|
||||
ODM_SEC_TKIP = 2,
|
||||
ODM_SEC_RESERVE = 3,
|
||||
ODM_SEC_AESCCMP = 4,
|
||||
ODM_SEC_WEP104 = 5,
|
||||
ODM_WEP_WPA_MIXED = 6, // WEP + WPA
|
||||
ODM_SEC_SMS4 = 7,
|
||||
}ODM_SECURITY_E;
|
||||
|
||||
// ODM_CMNINFO_BW
|
||||
typedef enum tag_Bandwidth_Definition
|
||||
{
|
||||
ODM_BW20M = 0,
|
||||
ODM_BW40M = 1,
|
||||
ODM_BW80M = 2,
|
||||
ODM_BW160M = 3,
|
||||
ODM_BW5M = 4,
|
||||
ODM_BW10M = 5,
|
||||
ODM_BW_MAX = 6
|
||||
}ODM_BW_E;
|
||||
|
||||
// ODM_CMNINFO_CHNL
|
||||
|
||||
// ODM_CMNINFO_BOARD_TYPE
|
||||
typedef enum tag_Board_Definition
|
||||
{
|
||||
ODM_BOARD_DEFAULT = 0, // The DEFAULT case.
|
||||
ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card.
|
||||
ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card
|
||||
ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT
|
||||
ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA
|
||||
ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA
|
||||
ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW
|
||||
ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA
|
||||
ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA
|
||||
}ODM_BOARD_TYPE_E;
|
||||
|
||||
typedef enum tag_ODM_Package_Definition
|
||||
{
|
||||
ODM_PACKAGE_DEFAULT = 0,
|
||||
ODM_PACKAGE_QFN68 = BIT(0),
|
||||
ODM_PACKAGE_TFBGA90 = BIT(1),
|
||||
ODM_PACKAGE_TFBGA79 = BIT(2),
|
||||
}ODM_Package_TYPE_E;
|
||||
|
||||
typedef enum tag_ODM_TYPE_GPA_Definition {
|
||||
TYPE_GPA0 = 0x0000,
|
||||
TYPE_GPA1 = 0x0055,
|
||||
TYPE_GPA2 = 0x00AA,
|
||||
TYPE_GPA3 = 0x00FF,
|
||||
TYPE_GPA4 = 0x5500,
|
||||
TYPE_GPA5 = 0x5555,
|
||||
TYPE_GPA6 = 0x55AA,
|
||||
TYPE_GPA7 = 0x55FF,
|
||||
TYPE_GPA8 = 0xAA00,
|
||||
TYPE_GPA9 = 0xAA55,
|
||||
TYPE_GPA10 = 0xAAAA,
|
||||
TYPE_GPA11 = 0xAAFF,
|
||||
TYPE_GPA12 = 0xFF00,
|
||||
TYPE_GPA13 = 0xFF55,
|
||||
TYPE_GPA14 = 0xFFAA,
|
||||
TYPE_GPA15 = 0xFFFF,
|
||||
}ODM_TYPE_GPA_E;
|
||||
|
||||
typedef enum tag_ODM_TYPE_APA_Definition {
|
||||
TYPE_APA0 = 0x0000,
|
||||
TYPE_APA1 = 0x0055,
|
||||
TYPE_APA2 = 0x00AA,
|
||||
TYPE_APA3 = 0x00FF,
|
||||
TYPE_APA4 = 0x5500,
|
||||
TYPE_APA5 = 0x5555,
|
||||
TYPE_APA6 = 0x55AA,
|
||||
TYPE_APA7 = 0x55FF,
|
||||
TYPE_APA8 = 0xAA00,
|
||||
TYPE_APA9 = 0xAA55,
|
||||
TYPE_APA10 = 0xAAAA,
|
||||
TYPE_APA11 = 0xAAFF,
|
||||
TYPE_APA12 = 0xFF00,
|
||||
TYPE_APA13 = 0xFF55,
|
||||
TYPE_APA14 = 0xFFAA,
|
||||
TYPE_APA15 = 0xFFFF,
|
||||
}ODM_TYPE_APA_E;
|
||||
|
||||
typedef enum tag_ODM_TYPE_GLNA_Definition {
|
||||
TYPE_GLNA0 = 0x0000,
|
||||
TYPE_GLNA1 = 0x0055,
|
||||
TYPE_GLNA2 = 0x00AA,
|
||||
TYPE_GLNA3 = 0x00FF,
|
||||
TYPE_GLNA4 = 0x5500,
|
||||
TYPE_GLNA5 = 0x5555,
|
||||
TYPE_GLNA6 = 0x55AA,
|
||||
TYPE_GLNA7 = 0x55FF,
|
||||
TYPE_GLNA8 = 0xAA00,
|
||||
TYPE_GLNA9 = 0xAA55,
|
||||
TYPE_GLNA10 = 0xAAAA,
|
||||
TYPE_GLNA11 = 0xAAFF,
|
||||
TYPE_GLNA12 = 0xFF00,
|
||||
TYPE_GLNA13 = 0xFF55,
|
||||
TYPE_GLNA14 = 0xFFAA,
|
||||
TYPE_GLNA15 = 0xFFFF,
|
||||
}ODM_TYPE_GLNA_E;
|
||||
|
||||
typedef enum tag_ODM_TYPE_ALNA_Definition {
|
||||
TYPE_ALNA0 = 0x0000,
|
||||
TYPE_ALNA1 = 0x0055,
|
||||
TYPE_ALNA2 = 0x00AA,
|
||||
TYPE_ALNA3 = 0x00FF,
|
||||
TYPE_ALNA4 = 0x5500,
|
||||
TYPE_ALNA5 = 0x5555,
|
||||
TYPE_ALNA6 = 0x55AA,
|
||||
TYPE_ALNA7 = 0x55FF,
|
||||
TYPE_ALNA8 = 0xAA00,
|
||||
TYPE_ALNA9 = 0xAA55,
|
||||
TYPE_ALNA10 = 0xAAAA,
|
||||
TYPE_ALNA11 = 0xAAFF,
|
||||
TYPE_ALNA12 = 0xFF00,
|
||||
TYPE_ALNA13 = 0xFF55,
|
||||
TYPE_ALNA14 = 0xFFAA,
|
||||
TYPE_ALNA15 = 0xFFFF,
|
||||
}ODM_TYPE_ALNA_E;
|
||||
|
||||
|
||||
typedef enum _ODM_RF_RADIO_PATH {
|
||||
ODM_RF_PATH_A = 0, //Radio Path A
|
||||
ODM_RF_PATH_B = 1, //Radio Path B
|
||||
ODM_RF_PATH_C = 2, //Radio Path C
|
||||
ODM_RF_PATH_D = 3, //Radio Path D
|
||||
ODM_RF_PATH_AB,
|
||||
ODM_RF_PATH_AC,
|
||||
ODM_RF_PATH_AD,
|
||||
ODM_RF_PATH_BC,
|
||||
ODM_RF_PATH_BD,
|
||||
ODM_RF_PATH_CD,
|
||||
ODM_RF_PATH_ABC,
|
||||
ODM_RF_PATH_ACD,
|
||||
ODM_RF_PATH_BCD,
|
||||
ODM_RF_PATH_ABCD,
|
||||
// ODM_RF_PATH_MAX, //Max RF number 90 support
|
||||
} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
|
||||
|
||||
typedef enum _ODM_PARAMETER_INIT {
|
||||
ODM_PRE_SETTING = 0,
|
||||
ODM_POST_SETTING = 1,
|
||||
} ODM_PARAMETER_INIT_E;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,351 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODM_PRECOMP_H__
|
||||
#define __ODM_PRECOMP_H__
|
||||
|
||||
#include "phydm_types.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting.
|
||||
#else
|
||||
#define TEST_FALG___ 1
|
||||
#endif
|
||||
|
||||
//2 Config Flags and Structs - defined by each ODM Type
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "../8192cd_cfg.h"
|
||||
#include "../odm_inc.h"
|
||||
|
||||
#include "../8192cd.h"
|
||||
#include "../8192cd_util.h"
|
||||
#ifdef _BIG_ENDIAN_
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
|
||||
#else
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
|
||||
#endif
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
#include "../8192cd_headers.h"
|
||||
#include "../8192cd_debug.h"
|
||||
#endif
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
|
||||
#define __PACK
|
||||
#define __WLAN_ATTRIB_PACK__
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "mp_precomp.h"
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
|
||||
#define __PACK
|
||||
#define __WLAN_ATTRIB_PACK__
|
||||
#endif
|
||||
|
||||
//2 OutSrc Header Files
|
||||
|
||||
#include "phydm.h"
|
||||
#include "phydm_hwconfig.h"
|
||||
#include "phydm_debug.h"
|
||||
#include "phydm_regdefine11ac.h"
|
||||
#include "phydm_regdefine11n.h"
|
||||
#include "phydm_interface.h"
|
||||
#include "phydm_reg.h"
|
||||
|
||||
#include "phydm_adc_sampling.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
VOID
|
||||
PHY_SetTxPowerLimit(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u8 *Regulation,
|
||||
IN u8 *Band,
|
||||
IN u8 *Bandwidth,
|
||||
IN u8 *RateSection,
|
||||
IN u8 *RfPath,
|
||||
IN u8 *Channel,
|
||||
IN u8 *PowerLimit
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#define RTL8703B_SUPPORT 0
|
||||
#define RTL8188F_SUPPORT 0
|
||||
#define RTL8723D_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#if RTL8188E_SUPPORT == 1
|
||||
#define RTL8188E_T_SUPPORT 1
|
||||
#ifdef CONFIG_SFW_SUPPORTED
|
||||
#define RTL8188E_S_SUPPORT 1
|
||||
#else
|
||||
#define RTL8188E_S_SUPPORT 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8188E_SUPPORT==1)
|
||||
#include "rtl8188e/hal8188erateadaptive.h"//for RA,Power training
|
||||
#include "rtl8188e/halhwimg8188e_mac.h"
|
||||
#include "rtl8188e/halhwimg8188e_rf.h"
|
||||
#include "rtl8188e/halhwimg8188e_bb.h"
|
||||
#include "rtl8188e/halhwimg8188e_t_fw.h"
|
||||
#include "rtl8188e/halhwimg8188e_s_fw.h"
|
||||
#include "rtl8188e/phydm_regconfig8188e.h"
|
||||
#include "rtl8188e/phydm_rtl8188e.h"
|
||||
#include "rtl8188e/hal8188ereg.h"
|
||||
#include "rtl8188e/version_rtl8188e.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8188e_hal.h"
|
||||
#include "rtl8188e/halphyrf_8188e_ce.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8188e/halphyrf_8188e_win.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "rtl8188e/halphyrf_8188e_ap.h"
|
||||
#endif
|
||||
#endif //88E END
|
||||
|
||||
#if (RTL8192E_SUPPORT==1)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8192e/halphyrf_8192e_win.h" /*FOR_8192E_IQK*/
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "rtl8192e/halphyrf_8192e_ap.h" /*FOR_8192E_IQK*/
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8192e/halphyrf_8192e_ce.h" /*FOR_8192E_IQK*/
|
||||
#endif
|
||||
|
||||
#include "rtl8192e/phydm_rtl8192e.h" //FOR_8192E_IQK
|
||||
#include "rtl8192e/version_rtl8192e.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
#include "rtl8192e/halhwimg8192e_bb.h"
|
||||
#include "rtl8192e/halhwimg8192e_mac.h"
|
||||
#include "rtl8192e/halhwimg8192e_rf.h"
|
||||
#include "rtl8192e/phydm_regconfig8192e.h"
|
||||
#include "rtl8192e/halhwimg8192e_fw.h"
|
||||
#include "rtl8192e/hal8192ereg.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8192e_hal.h"
|
||||
#endif
|
||||
#endif //92E END
|
||||
|
||||
#if (RTL8812A_SUPPORT==1)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8812a/halphyrf_8812a_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "rtl8812a/halphyrf_8812a_ap.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8812a/halphyrf_8812a_ce.h"
|
||||
#endif
|
||||
|
||||
//#include "rtl8812a/HalPhyRf_8812A.h" //FOR_8812_IQK
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
#include "rtl8812a/halhwimg8812a_bb.h"
|
||||
#include "rtl8812a/halhwimg8812a_mac.h"
|
||||
#include "rtl8812a/halhwimg8812a_rf.h"
|
||||
#include "rtl8812a/phydm_regconfig8812a.h"
|
||||
#include "rtl8812a/halhwimg8812a_fw.h"
|
||||
#include "rtl8812a/phydm_rtl8812a.h"
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8812a_hal.h"
|
||||
#endif
|
||||
#include "rtl8812a/version_rtl8812a.h"
|
||||
|
||||
#endif //8812 END
|
||||
|
||||
#if (RTL8814A_SUPPORT==1)
|
||||
|
||||
#include "rtl8814a/halhwimg8814a_mac.h"
|
||||
#include "rtl8814a/halhwimg8814a_rf.h"
|
||||
#include "rtl8814a/halhwimg8814a_bb.h"
|
||||
#include "rtl8814a/version_rtl8814a.h"
|
||||
#include "rtl8814a/phydm_rtl8814a.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
#include "rtl8814a/halhwimg8814a_fw.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8814a/halphyrf_8814a_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8814a/halphyrf_8814a_ce.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "rtl8814a/halphyrf_8814a_ap.h"
|
||||
#endif
|
||||
#include "rtl8814a/phydm_regconfig8814a.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8814a_hal.h"
|
||||
#include "rtl8814a/phydm_iqk_8814a.h"
|
||||
#endif
|
||||
#endif //8814 END
|
||||
|
||||
#if (RTL8881A_SUPPORT==1)//FOR_8881_IQK
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8821a/phydm_iqk_8821a_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8821a/phydm_iqk_8821a_ce.h"
|
||||
#else
|
||||
#include "rtl8821a/phydm_iqk_8821a_ap.h"
|
||||
#endif
|
||||
//#include "rtl8881a/HalHWImg8881A_BB.h"
|
||||
//#include "rtl8881a/HalHWImg8881A_MAC.h"
|
||||
//#include "rtl8881a/HalHWImg8881A_RF.h"
|
||||
//#include "rtl8881a/odm_RegConfig8881A.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8723B_SUPPORT==1)
|
||||
#include "rtl8723b/halhwimg8723b_mac.h"
|
||||
#include "rtl8723b/halhwimg8723b_rf.h"
|
||||
#include "rtl8723b/halhwimg8723b_bb.h"
|
||||
#include "rtl8723b/halhwimg8723b_fw.h"
|
||||
#include "rtl8723b/phydm_regconfig8723b.h"
|
||||
#include "rtl8723b/phydm_rtl8723b.h"
|
||||
#include "rtl8723b/hal8723breg.h"
|
||||
#include "rtl8723b/version_rtl8723b.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8723b/halphyrf_8723b_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8723b/halphyrf_8723b_ce.h"
|
||||
#include "rtl8723b/halhwimg8723b_mp.h"
|
||||
#include "rtl8723b_hal.h"
|
||||
#else
|
||||
#include "rtl8723b/halphyrf_8723b_ap.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT==1)
|
||||
#include "rtl8821a/halhwimg8821a_mac.h"
|
||||
#include "rtl8821a/halhwimg8821a_rf.h"
|
||||
#include "rtl8821a/halhwimg8821a_bb.h"
|
||||
#include "rtl8821a/halhwimg8821a_fw.h"
|
||||
#include "rtl8821a/phydm_regconfig8821a.h"
|
||||
#include "rtl8821a/phydm_rtl8821a.h"
|
||||
#include "rtl8821a/version_rtl8821a.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8821a/halphyrf_8821a_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8821a/halphyrf_8821a_ce.h"
|
||||
#include "rtl8821a/phydm_iqk_8821a_ce.h"/*for IQK*/
|
||||
#include "rtl8812a/halphyrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/
|
||||
#include "rtl8812a_hal.h"
|
||||
#else
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT==1)
|
||||
#include "rtl8822b/halhwimg8822b_mac.h"
|
||||
#include "rtl8822b/halhwimg8822b_rf.h"
|
||||
#include "rtl8822b/halhwimg8822b_bb.h"
|
||||
#include "rtl8822b/halhwimg8822b_fw.h"
|
||||
#include "rtl8822b/phydm_regconfig8822b.h"
|
||||
#include "rtl8822b/halphyrf_8822b.h"
|
||||
#include "rtl8822b/phydm_rtl8822b.h"
|
||||
#include "rtl8822b/phydm_hal_api8822b.h"
|
||||
#include "rtl8822b/version_rtl8822b.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include <hal_data.h> /* struct HAL_DATA_TYPE */
|
||||
#include <rtl8822b_hal.h> /* Rx_Smooth_Factor, reg definition and etc.*/
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (RTL8703B_SUPPORT==1)
|
||||
#include "rtl8703b/phydm_regconfig8703b.h"
|
||||
#include "rtl8703b/halhwimg8703b_mac.h"
|
||||
#include "rtl8703b/halhwimg8703b_rf.h"
|
||||
#include "rtl8703b/halhwimg8703b_bb.h"
|
||||
#include "rtl8703b/halhwimg8703b_fw.h"
|
||||
#include "rtl8703b/halphyrf_8703b.h"
|
||||
#include "rtl8703b/version_rtl8703b.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8703b_hal.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8188F_SUPPORT == 1)
|
||||
#include "rtl8188f/halhwimg8188f_mac.h"
|
||||
#include "rtl8188f/halhwimg8188f_rf.h"
|
||||
#include "rtl8188f/halhwimg8188f_bb.h"
|
||||
#include "rtl8188f/halhwimg8188f_fw.h"
|
||||
#include "rtl8188f/hal8188freg.h"
|
||||
#include "rtl8188f/phydm_rtl8188f.h"
|
||||
#include "rtl8188f/phydm_regconfig8188f.h"
|
||||
#include "rtl8188f/halphyrf_8188f.h" /* for IQK,LCK,Power-tracking */
|
||||
#include "rtl8188f/version_rtl8188f.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8188f_hal.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8723D_SUPPORT==1)
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
|
||||
#include "rtl8723d/halhwimg8723d_bb.h"
|
||||
#include "rtl8723d/halhwimg8723d_mac.h"
|
||||
#include "rtl8723d/halhwimg8723d_rf.h"
|
||||
#include "rtl8723d/phydm_regconfig8723d.h"
|
||||
#include "rtl8723d/halhwimg8723d_fw.h"
|
||||
#include "rtl8723d/hal8723dreg.h"
|
||||
#include "rtl8723d/phydm_rtl8723d.h"
|
||||
#include "rtl8723d/halphyrf_8723d.h"
|
||||
#include "rtl8723d/version_rtl8723d.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8723d_hal.h"
|
||||
#endif
|
||||
#endif //8723D End
|
||||
|
||||
#if (RTL8197F_SUPPORT == 1)
|
||||
#include "rtl8197f/halhwimg8197f_mac.h"
|
||||
#include "rtl8197f/halhwimg8197f_rf.h"
|
||||
#include "rtl8197f/halhwimg8197f_bb.h"
|
||||
#include "rtl8197f/phydm_hal_api8197f.h"
|
||||
#include "rtl8197f/version_rtl8197f.h"
|
||||
#include "rtl8197f/phydm_rtl8197f.h"
|
||||
#include "rtl8197f/phydm_regconfig8197f.h"
|
||||
#include "rtl8197f/halphyrf_8197f.h"
|
||||
#include "rtl8197f/phydm_iqk_8197f.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT==1)
|
||||
#include "rtl8821c/phydm_hal_api8821c.h"
|
||||
#include "rtl8821c/halhwimg8821c_testchip_mac.h"
|
||||
#include "rtl8821c/halhwimg8821c_testchip_rf.h"
|
||||
#include "rtl8821c/halhwimg8821c_testchip_bb.h"
|
||||
#include "rtl8821c/halhwimg8821c_mac.h"
|
||||
#include "rtl8821c/halhwimg8821c_rf.h"
|
||||
#include "rtl8821c/halhwimg8821c_bb.h"
|
||||
#include "rtl8821c/halhwimg8821c_fw.h"
|
||||
#include "rtl8821c/phydm_regconfig8821c.h"
|
||||
#include "rtl8821c/halphyrf_8821c.h"
|
||||
#include "rtl8821c/version_rtl8821c.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8821c_hal.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif // __ODM_PRECOMP_H__
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,583 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMRAINFO_H__
|
||||
#define __PHYDMRAINFO_H__
|
||||
|
||||
/*#define RAINFO_VERSION "2.0" //2014.11.04*/
|
||||
/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/
|
||||
/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/
|
||||
/*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/
|
||||
/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
|
||||
/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */
|
||||
/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */
|
||||
#define RAINFO_VERSION "4.2" /*2016.05.17 Dino, Add H2C debug cmd */
|
||||
|
||||
#define H2C_0X42_LENGTH 5
|
||||
#define H2C_MAX_LENGTH 7
|
||||
|
||||
#define RA_FLOOR_UP_GAP 3
|
||||
#define RA_FLOOR_TABLE_SIZE 7
|
||||
|
||||
#define ACTIVE_TP_THRESHOLD 150
|
||||
#define RA_RETRY_DESCEND_NUM 2
|
||||
#define RA_RETRY_LIMIT_LOW 4
|
||||
#define RA_RETRY_LIMIT_HIGH 32
|
||||
|
||||
#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL
|
||||
#define RAINFO_STBC_STATE BIT1
|
||||
//#define RAINFO_LDPC_STATE BIT2
|
||||
#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection
|
||||
#define RAINFO_SHURTCUT_STATE BIT3
|
||||
#define RAINFO_SHURTCUT_FLAG BIT4
|
||||
#define RAINFO_INIT_RSSI_RATE_STATE BIT5
|
||||
#define RAINFO_BF_STATE BIT6
|
||||
#define RAINFO_BE_TX_STATE BIT7 // 1:TX
|
||||
|
||||
#define RA_MASK_CCK 0xf
|
||||
#define RA_MASK_OFDM 0xff0
|
||||
#define RA_MASK_HT1SS 0xff000
|
||||
#define RA_MASK_HT2SS 0xff00000
|
||||
/*#define RA_MASK_MCS3SS */
|
||||
#define RA_MASK_HT4SS 0xff0
|
||||
#define RA_MASK_VHT1SS 0x3ff000
|
||||
#define RA_MASK_VHT2SS 0xffc00000
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#define RA_FIRST_MACID 1
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define RA_FIRST_MACID 0
|
||||
#define WIN_DEFAULT_PORT_MACID 0
|
||||
#define WIN_BT_PORT_MACID 2
|
||||
#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
|
||||
#define RA_FIRST_MACID 0
|
||||
#endif
|
||||
|
||||
#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit
|
||||
|
||||
#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN)
|
||||
#define DM_RATR_STA_INIT 0
|
||||
#define DM_RATR_STA_HIGH 1
|
||||
#define DM_RATR_STA_MIDDLE 2
|
||||
#define DM_RATR_STA_LOW 3
|
||||
#define DM_RATR_STA_ULTRA_LOW 4
|
||||
#endif
|
||||
|
||||
typedef enum _phydm_arfr_num {
|
||||
ARFR_0_RATE_ID = 0x9,
|
||||
ARFR_1_RATE_ID = 0xa,
|
||||
ARFR_2_RATE_ID = 0xb,
|
||||
ARFR_3_RATE_ID = 0xc,
|
||||
ARFR_4_RATE_ID = 0xd,
|
||||
ARFR_5_RATE_ID = 0xe
|
||||
} PHYDM_RA_ARFR_NUM_E;
|
||||
|
||||
typedef enum _Phydm_ra_dbg_para {
|
||||
RADBG_PCR_TH_OFFSET = 0,
|
||||
RADBG_RTY_PENALTY = 1,
|
||||
RADBG_N_HIGH = 2,
|
||||
RADBG_N_LOW = 3,
|
||||
RADBG_TRATE_UP_TABLE = 4,
|
||||
RADBG_TRATE_DOWN_TABLE = 5,
|
||||
RADBG_TRYING_NECESSARY = 6,
|
||||
RADBG_TDROPING_NECESSARY = 7,
|
||||
RADBG_RATE_UP_RTY_RATIO = 8,
|
||||
RADBG_RATE_DOWN_RTY_RATIO = 9, //u8
|
||||
|
||||
RADBG_DEBUG_MONITOR1 = 0xc,
|
||||
RADBG_DEBUG_MONITOR2 = 0xd,
|
||||
RADBG_DEBUG_MONITOR3 = 0xe,
|
||||
RADBG_DEBUG_MONITOR4 = 0xf,
|
||||
RADBG_DEBUG_MONITOR5 = 0x10,
|
||||
NUM_RA_PARA
|
||||
} PHYDM_RA_DBG_PARA_E;
|
||||
|
||||
typedef enum PHYDM_WIRELESS_MODE {
|
||||
|
||||
PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
|
||||
PHYDM_WIRELESS_MODE_A = 0x01,
|
||||
PHYDM_WIRELESS_MODE_B = 0x02,
|
||||
PHYDM_WIRELESS_MODE_G = 0x04,
|
||||
PHYDM_WIRELESS_MODE_AUTO = 0x08,
|
||||
PHYDM_WIRELESS_MODE_N_24G = 0x10,
|
||||
PHYDM_WIRELESS_MODE_N_5G = 0x20,
|
||||
PHYDM_WIRELESS_MODE_AC_5G = 0x40,
|
||||
PHYDM_WIRELESS_MODE_AC_24G = 0x80,
|
||||
PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
|
||||
PHYDM_WIRELESS_MODE_MAX = 0x800,
|
||||
PHYDM_WIRELESS_MODE_ALL = 0xFFFF
|
||||
} PHYDM_WIRELESS_MODE_E;
|
||||
|
||||
typedef enum PHYDM_RATEID_IDX_ {
|
||||
|
||||
PHYDM_BGN_40M_2SS = 0,
|
||||
PHYDM_BGN_40M_1SS = 1,
|
||||
PHYDM_BGN_20M_2SS = 2,
|
||||
PHYDM_BGN_20M_1SS = 3,
|
||||
PHYDM_GN_N2SS = 4,
|
||||
PHYDM_GN_N1SS = 5,
|
||||
PHYDM_BG = 6,
|
||||
PHYDM_G = 7,
|
||||
PHYDM_B_20M = 8,
|
||||
PHYDM_ARFR0_AC_2SS = 9,
|
||||
PHYDM_ARFR1_AC_1SS = 10,
|
||||
PHYDM_ARFR2_AC_2G_1SS = 11,
|
||||
PHYDM_ARFR3_AC_2G_2SS = 12,
|
||||
PHYDM_ARFR4_AC_3SS = 13,
|
||||
PHYDM_ARFR5_N_3SS = 14
|
||||
} PHYDM_RATEID_IDX_E;
|
||||
|
||||
typedef enum _PHYDM_RF_TYPE_DEFINITION {
|
||||
PHYDM_RF_1T1R = 0,
|
||||
PHYDM_RF_1T2R,
|
||||
PHYDM_RF_2T2R,
|
||||
PHYDM_RF_2T2R_GREEN,
|
||||
PHYDM_RF_2T3R,
|
||||
PHYDM_RF_2T4R,
|
||||
PHYDM_RF_3T3R,
|
||||
PHYDM_RF_3T4R,
|
||||
PHYDM_RF_4T4R,
|
||||
PHYDM_RF_MAX_TYPE
|
||||
} PHYDM_RF_TYPE_DEF_E;
|
||||
|
||||
typedef enum _PHYDM_BW {
|
||||
PHYDM_BW_20 = 0,
|
||||
PHYDM_BW_40,
|
||||
PHYDM_BW_80,
|
||||
PHYDM_BW_80_80,
|
||||
PHYDM_BW_160,
|
||||
PHYDM_BW_10,
|
||||
PHYDM_BW_5
|
||||
} PHYDM_BW_E;
|
||||
|
||||
|
||||
#if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA
|
||||
typedef struct _ODM_RA_Info_ {
|
||||
u1Byte RateID;
|
||||
u4Byte RateMask;
|
||||
u4Byte RAUseRate;
|
||||
u1Byte RateSGI;
|
||||
u1Byte RssiStaRA;
|
||||
u1Byte PreRssiStaRA;
|
||||
u1Byte SGIEnable;
|
||||
u1Byte DecisionRate;
|
||||
u1Byte PreRate;
|
||||
u1Byte HighestRate;
|
||||
u1Byte LowestRate;
|
||||
u4Byte NscUp;
|
||||
u4Byte NscDown;
|
||||
u2Byte RTY[5];
|
||||
u4Byte TOTAL;
|
||||
u2Byte DROP;
|
||||
u1Byte Active;
|
||||
u2Byte RptTime;
|
||||
u1Byte RAWaitingCounter;
|
||||
u1Byte RAPendingCounter;
|
||||
u1Byte RADropAfterDown;
|
||||
#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
|
||||
u1Byte PTActive; // on or off
|
||||
u1Byte PTTryState; // 0 trying state, 1 for decision state
|
||||
u1Byte PTStage; // 0~6
|
||||
u1Byte PTStopCount; //Stop PT counter
|
||||
u1Byte PTPreRate; // if rate change do PT
|
||||
u1Byte PTPreRssi; // if RSSI change 5% do PT
|
||||
u1Byte PTModeSS; // decide whitch rate should do PT
|
||||
u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
|
||||
u1Byte PTSmoothFactor;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
|
||||
u1Byte RateDownCounter;
|
||||
u1Byte RateUpCounter;
|
||||
u1Byte RateDirection;
|
||||
u1Byte BoundingType;
|
||||
u1Byte BoundingCounter;
|
||||
u1Byte BoundingLearningTime;
|
||||
u1Byte RateDownStartTime;
|
||||
#endif
|
||||
} ODM_RA_INFO_T, *PODM_RA_INFO_T;
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct _Rate_Adaptive_Table_ {
|
||||
u1Byte firstconnect;
|
||||
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
|
||||
BOOLEAN PT_collision_pre;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_RA_DBG_CMD))
|
||||
BOOLEAN is_ra_dbg_init;
|
||||
|
||||
u1Byte RTY_P[ODM_NUM_RATE_IDX];
|
||||
u1Byte RTY_P_default[ODM_NUM_RATE_IDX];
|
||||
BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX];
|
||||
|
||||
u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
|
||||
u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
|
||||
BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
|
||||
|
||||
u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
|
||||
u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
|
||||
BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
|
||||
|
||||
BOOLEAN RA_Para_feedback_req;
|
||||
|
||||
u1Byte para_idx;
|
||||
u1Byte rate_idx;
|
||||
u1Byte value;
|
||||
u2Byte value_16;
|
||||
u1Byte rate_length;
|
||||
#endif
|
||||
u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u1Byte highest_client_tx_order;
|
||||
u2Byte highest_client_tx_rate_order;
|
||||
u1Byte power_tracking_flag;
|
||||
u1Byte RA_threshold_offset;
|
||||
u1Byte RA_offset_direction;
|
||||
|
||||
#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
|
||||
u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
|
||||
u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
|
||||
u1Byte retry_descend_num;
|
||||
u1Byte retrylimit_low;
|
||||
u1Byte retrylimit_high;
|
||||
#endif
|
||||
|
||||
|
||||
} RA_T, *pRA_T;
|
||||
|
||||
typedef struct _ODM_RATE_ADAPTIVE {
|
||||
u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
|
||||
u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
|
||||
u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
|
||||
u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC
|
||||
BOOLEAN bLowerRtsRate;
|
||||
#endif
|
||||
|
||||
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
u1Byte RtsThres;
|
||||
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
BOOLEAN bUseLdpc;
|
||||
#else
|
||||
u1Byte UltraLowRSSIThresh;
|
||||
u4Byte LastRATR; // RATR Register Content
|
||||
#endif
|
||||
|
||||
} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
|
||||
|
||||
VOID
|
||||
phydm_h2C_debug(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *const dm_value,
|
||||
IN u4Byte *_used,
|
||||
OUT char *output,
|
||||
IN u4Byte *_out_len
|
||||
);
|
||||
|
||||
#if (defined(CONFIG_RA_DBG_CMD))
|
||||
|
||||
VOID
|
||||
odm_RA_debug(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *const dm_value
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RA_ParaAdjust_init(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
#else
|
||||
|
||||
VOID
|
||||
phydm_RA_debug_PCR(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte *const dm_value,
|
||||
IN u4Byte *_used,
|
||||
OUT char *output,
|
||||
IN u4Byte *_out_len
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
VOID
|
||||
ODM_C2HRaParaReportHandler(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte CmdBuf,
|
||||
IN u1Byte CmdLen
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RA_ParaAdjust(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_ra_dynamic_retry_count(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_ra_dynamic_retry_limit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_ra_dynamic_rate_id_on_assoc(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte wireless_mode,
|
||||
IN u1Byte init_rate_id
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_print_rate(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte rate,
|
||||
IN u4Byte dbg_component
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_c2h_ra_report_handler(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte CmdBuf,
|
||||
IN u1Byte CmdLen
|
||||
);
|
||||
|
||||
u1Byte
|
||||
phydm_rate_order_compute(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte rate_idx
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_ra_info_watchdog(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_ra_info_init(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RSSIMonitorInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_modify_RA_PCR_threshold(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte RA_offset_direction,
|
||||
IN u1Byte RA_threshold_offset
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RSSIMonitorCheck(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_initRaInfo(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
u1Byte
|
||||
phydm_vht_en_mapping(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte WirelessMode
|
||||
);
|
||||
|
||||
u1Byte
|
||||
phydm_rate_id_mapping(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte WirelessMode,
|
||||
IN u1Byte RfType,
|
||||
IN u1Byte bw
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_UpdateHalRAMask(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte wirelessMode,
|
||||
IN u1Byte RfType,
|
||||
IN u1Byte BW,
|
||||
IN u1Byte MimoPs_enable,
|
||||
IN u1Byte disable_cck_rate,
|
||||
IN u4Byte *ratr_bitmap_msb_in,
|
||||
IN u4Byte *ratr_bitmap_in,
|
||||
IN u1Byte tx_rate_level
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RateAdaptiveMaskInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RefreshRateAdaptiveMask(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RefreshRateAdaptiveMaskMP(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RefreshRateAdaptiveMaskCE(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RefreshRateAdaptiveMaskAPADSL(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
u1Byte
|
||||
phydm_RA_level_decision(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte rssi,
|
||||
IN u1Byte Ratr_State
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
ODM_RAStateCheck(
|
||||
IN PVOID pDM_VOID,
|
||||
IN s4Byte RSSI,
|
||||
IN BOOLEAN bForceUpdate,
|
||||
OUT pu1Byte pRATRState
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RefreshBasicRateMask(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
VOID
|
||||
ODM_RAPostActionOnAssoc(
|
||||
IN PVOID pDM_Odm
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
|
||||
u1Byte
|
||||
odm_Find_RTS_Rate(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Tx_Rate,
|
||||
IN BOOLEAN bErpProtect
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_UpdateNoisyState(
|
||||
IN PVOID pDM_VOID,
|
||||
IN BOOLEAN bNoisyStateFromC2H
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_update_pwr_track(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Rate
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
s4Byte
|
||||
phydm_FindMinimumRSSI(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN PADAPTER pAdapter,
|
||||
IN OUT BOOLEAN *pbLink_temp
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_UpdateInitRateWorkItemCallback(
|
||||
IN PVOID pContext
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RSSIDumpToRegister(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
odm_RefreshLdpcRtsMP(
|
||||
IN PADAPTER pAdapter,
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u1Byte mMacId,
|
||||
IN u1Byte IOTPeer,
|
||||
IN s4Byte UndecoratedSmoothedPWDB
|
||||
);
|
||||
|
||||
#if 0
|
||||
VOID
|
||||
ODM_DynamicARFBSelect(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte rate,
|
||||
IN BOOLEAN Collision_State
|
||||
);
|
||||
#endif
|
||||
|
||||
VOID
|
||||
ODM_RateAdaptiveStateApInit(
|
||||
IN PVOID PADAPTER_VOID,
|
||||
IN PRT_WLAN_STA pEntry
|
||||
);
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
static void
|
||||
FindMinimumRSSI(
|
||||
IN PADAPTER pAdapter
|
||||
);
|
||||
|
||||
u8Byte
|
||||
PhyDM_Get_Rate_Bitmap_Ex(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte macid,
|
||||
IN u8Byte ra_mask,
|
||||
IN u1Byte rssi_level,
|
||||
OUT u8Byte *dm_RA_Mask,
|
||||
OUT u1Byte *dm_RteID
|
||||
);
|
||||
u4Byte
|
||||
ODM_Get_Rate_Bitmap(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u4Byte macid,
|
||||
IN u4Byte ra_mask,
|
||||
IN u1Byte rssi_level
|
||||
);
|
||||
|
||||
void phydm_ra_rssi_rpt_wk(PVOID pContext);
|
||||
#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
VOID
|
||||
phydm_gen_ramask_h2c_AP(
|
||||
IN PVOID pDM_VOID,
|
||||
IN struct rtl8192cd_priv *priv,
|
||||
IN PSTA_INFO_T *pEntry,
|
||||
IN u1Byte rssi_level
|
||||
);
|
||||
|
||||
#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
|
||||
|
||||
#endif /*#ifndef __ODMRAINFO_H__*/
|
||||
|
||||
|
||||
@@ -0,0 +1,215 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
//============================================================
|
||||
// File Name: odm_reg.h
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This file is for general register definition.
|
||||
//
|
||||
//
|
||||
//============================================================
|
||||
#ifndef __HAL_ODM_REG_H__
|
||||
#define __HAL_ODM_REG_H__
|
||||
|
||||
//
|
||||
// Register Definition
|
||||
//
|
||||
|
||||
//MAC REG
|
||||
#define ODM_BB_RESET 0x002
|
||||
#define ODM_DUMMY 0x4fe
|
||||
#define RF_T_METER_OLD 0x24
|
||||
#define RF_T_METER_NEW 0x42
|
||||
|
||||
#define ODM_EDCA_VO_PARAM 0x500
|
||||
#define ODM_EDCA_VI_PARAM 0x504
|
||||
#define ODM_EDCA_BE_PARAM 0x508
|
||||
#define ODM_EDCA_BK_PARAM 0x50C
|
||||
#define ODM_TXPAUSE 0x522
|
||||
|
||||
/* LTE_COEX */
|
||||
#define REG_LTECOEX_CTRL 0x07C0
|
||||
#define REG_LTECOEX_WRITE_DATA 0x07C4
|
||||
#define REG_LTECOEX_READ_DATA 0x07C8
|
||||
#define REG_LTECOEX_PATH_CONTROL 0x70
|
||||
|
||||
//BB REG
|
||||
#define ODM_FPGA_PHY0_PAGE8 0x800
|
||||
#define ODM_PSD_SETTING 0x808
|
||||
#define ODM_AFE_SETTING 0x818
|
||||
#define ODM_TXAGC_B_6_18 0x830
|
||||
#define ODM_TXAGC_B_24_54 0x834
|
||||
#define ODM_TXAGC_B_MCS32_5 0x838
|
||||
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
|
||||
#define ODM_TXAGC_B_MCS4_MCS7 0x848
|
||||
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
|
||||
#define ODM_ANALOG_REGISTER 0x85c
|
||||
#define ODM_RF_INTERFACE_OUTPUT 0x860
|
||||
#define ODM_TXAGC_B_MCS12_MCS15 0x868
|
||||
#define ODM_TXAGC_B_11_A_2_11 0x86c
|
||||
#define ODM_AD_DA_LSB_MASK 0x874
|
||||
#define ODM_ENABLE_3_WIRE 0x88c
|
||||
#define ODM_PSD_REPORT 0x8b4
|
||||
#define ODM_R_ANT_SELECT 0x90c
|
||||
#define ODM_CCK_ANT_SELECT 0xa07
|
||||
#define ODM_CCK_PD_THRESH 0xa0a
|
||||
#define ODM_CCK_RF_REG1 0xa11
|
||||
#define ODM_CCK_MATCH_FILTER 0xa20
|
||||
#define ODM_CCK_RAKE_MAC 0xa2e
|
||||
#define ODM_CCK_CNT_RESET 0xa2d
|
||||
#define ODM_CCK_TX_DIVERSITY 0xa2f
|
||||
#define ODM_CCK_FA_CNT_MSB 0xa5b
|
||||
#define ODM_CCK_FA_CNT_LSB 0xa5c
|
||||
#define ODM_CCK_NEW_FUNCTION 0xa75
|
||||
#define ODM_OFDM_PHY0_PAGE_C 0xc00
|
||||
#define ODM_OFDM_RX_ANT 0xc04
|
||||
#define ODM_R_A_RXIQI 0xc14
|
||||
#define ODM_R_A_AGC_CORE1 0xc50
|
||||
#define ODM_R_A_AGC_CORE2 0xc54
|
||||
#define ODM_R_B_AGC_CORE1 0xc58
|
||||
#define ODM_R_AGC_PAR 0xc70
|
||||
#define ODM_R_HTSTF_AGC_PAR 0xc7c
|
||||
#define ODM_TX_PWR_TRAINING_A 0xc90
|
||||
#define ODM_TX_PWR_TRAINING_B 0xc98
|
||||
#define ODM_OFDM_FA_CNT1 0xcf0
|
||||
#define ODM_OFDM_PHY0_PAGE_D 0xd00
|
||||
#define ODM_OFDM_FA_CNT2 0xda0
|
||||
#define ODM_OFDM_FA_CNT3 0xda4
|
||||
#define ODM_OFDM_FA_CNT4 0xda8
|
||||
#define ODM_TXAGC_A_6_18 0xe00
|
||||
#define ODM_TXAGC_A_24_54 0xe04
|
||||
#define ODM_TXAGC_A_1_MCS32 0xe08
|
||||
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
|
||||
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
|
||||
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
|
||||
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
|
||||
|
||||
//RF REG
|
||||
#define ODM_GAIN_SETTING 0x00
|
||||
#define ODM_CHANNEL 0x18
|
||||
#define ODM_RF_T_METER 0x24
|
||||
#define ODM_RF_T_METER_92D 0x42
|
||||
#define ODM_RF_T_METER_88E 0x42
|
||||
#define ODM_RF_T_METER_92E 0x42
|
||||
#define ODM_RF_T_METER_8812 0x42
|
||||
#define rRF_TxGainOffset 0x55
|
||||
|
||||
//Ant Detect Reg
|
||||
#define ODM_DPDT 0x300
|
||||
|
||||
//PSD Init
|
||||
#define ODM_PSDREG 0x808
|
||||
|
||||
//92D Path Div
|
||||
#define PATHDIV_REG 0xB30
|
||||
#define PATHDIV_TRI 0xBA0
|
||||
|
||||
|
||||
//
|
||||
// Bitmap Definition
|
||||
//
|
||||
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
// TX AGC
|
||||
#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
|
||||
#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
|
||||
#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
|
||||
#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
|
||||
#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
|
||||
#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
|
||||
#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
|
||||
#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
|
||||
#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
|
||||
#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
|
||||
#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
|
||||
#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
|
||||
#if defined(CONFIG_WLAN_HAL_8814AE)
|
||||
#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8
|
||||
#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc
|
||||
#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0
|
||||
#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4
|
||||
#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8
|
||||
#endif
|
||||
#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
|
||||
#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
|
||||
#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
|
||||
#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
|
||||
#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
|
||||
#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
|
||||
#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
|
||||
#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
|
||||
#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
|
||||
#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
|
||||
#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
|
||||
#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
|
||||
#if defined(CONFIG_WLAN_HAL_8814AE)
|
||||
#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8
|
||||
#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc
|
||||
#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0
|
||||
#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4
|
||||
#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8
|
||||
#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820
|
||||
#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824
|
||||
#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828
|
||||
#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c
|
||||
#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830
|
||||
#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834
|
||||
#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838
|
||||
#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c
|
||||
#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840
|
||||
#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844
|
||||
#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848
|
||||
#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c
|
||||
#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8
|
||||
#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc
|
||||
#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0
|
||||
#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4
|
||||
#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8
|
||||
#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20
|
||||
#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24
|
||||
#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28
|
||||
#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c
|
||||
#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30
|
||||
#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34
|
||||
#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38
|
||||
#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c
|
||||
#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40
|
||||
#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44
|
||||
#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48
|
||||
#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c
|
||||
#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8
|
||||
#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc
|
||||
#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0
|
||||
#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4
|
||||
#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8
|
||||
#endif
|
||||
|
||||
#define bTxAGC_byte0_Jaguar 0xff
|
||||
#define bTxAGC_byte1_Jaguar 0xff00
|
||||
#define bTxAGC_byte2_Jaguar 0xff0000
|
||||
#define bTxAGC_byte3_Jaguar 0xff000000
|
||||
#endif
|
||||
|
||||
#define BIT_FA_RESET BIT0
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,94 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODM_REGDEFINE11AC_H__
|
||||
#define __ODM_REGDEFINE11AC_H__
|
||||
|
||||
//2 RF REG LIST
|
||||
|
||||
|
||||
|
||||
//2 BB REG LIST
|
||||
//PAGE 8
|
||||
#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
|
||||
#define ODM_REG_BB_RX_PATH_11AC 0x808
|
||||
#define ODM_REG_BB_TX_PATH_11AC 0x80c
|
||||
#define ODM_REG_BB_ATC_11AC 0x860
|
||||
#define ODM_REG_EDCCA_POWER_CAL 0x8dc
|
||||
#define ODM_REG_DBG_RPT_11AC 0x8fc
|
||||
//PAGE 9
|
||||
#define ODM_REG_EDCCA_DOWN_OPT 0x900
|
||||
#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
|
||||
#define ODM_ADC_TRIGGER_Jaguar2 0x95C /*ADC sample mode*/
|
||||
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
|
||||
#define ODM_REG_CCX_PERIOD_11AC 0x990
|
||||
#define ODM_REG_NHM_TH9_TH10_11AC 0x994
|
||||
#define ODM_REG_CLM_11AC 0x994
|
||||
#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
|
||||
#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
|
||||
#define ODM_REG_NHM_TH8_11AC 0x9a0
|
||||
#define ODM_REG_NHM_9E8_11AC 0x9e8
|
||||
#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
|
||||
//PAGE A
|
||||
#define ODM_REG_CCK_CCA_11AC 0xA0A
|
||||
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
|
||||
#define ODM_REG_CCK_FA_11AC 0xA5C
|
||||
//PAGE B
|
||||
#define ODM_REG_RST_RPT_11AC 0xB58
|
||||
//PAGE C
|
||||
#define ODM_REG_TRMUX_11AC 0xC08
|
||||
#define ODM_REG_IGI_A_11AC 0xC50
|
||||
//PAGE E
|
||||
#define ODM_REG_IGI_B_11AC 0xE50
|
||||
#define ODM_REG_TRMUX_11AC_B 0xE08
|
||||
//PAGE F
|
||||
#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04
|
||||
#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
|
||||
#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c
|
||||
#define ODM_REG_HT_CRC32_CNT_11AC 0xF10
|
||||
#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14
|
||||
#define ODM_REG_OFDM_FA_11AC 0xF48
|
||||
#define ODM_REG_RPT_11AC 0xfa0
|
||||
#define ODM_REG_CLM_RESULT_11AC 0xfa4
|
||||
#define ODM_REG_NHM_CNT_11AC 0xfa8
|
||||
#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
|
||||
|
||||
#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
|
||||
#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
|
||||
#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
|
||||
//PAGE 18
|
||||
#define ODM_REG_IGI_C_11AC 0x1850
|
||||
//PAGE 1A
|
||||
#define ODM_REG_IGI_D_11AC 0x1A50
|
||||
|
||||
//2 MAC REG LIST
|
||||
#define ODM_REG_RESP_TX_11AC 0x6D8
|
||||
|
||||
|
||||
|
||||
//DIG Related
|
||||
#define ODM_BIT_IGI_11AC 0xFFFFFFFF
|
||||
#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16
|
||||
#define ODM_BIT_BB_RX_PATH_11AC 0xF
|
||||
#define ODM_BIT_BB_TX_PATH_11AC 0xF
|
||||
#define ODM_BIT_BB_ATC_11AC BIT14
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,213 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODM_REGDEFINE11N_H__
|
||||
#define __ODM_REGDEFINE11N_H__
|
||||
|
||||
|
||||
//2 RF REG LIST
|
||||
#define ODM_REG_RF_MODE_11N 0x00
|
||||
#define ODM_REG_RF_0B_11N 0x0B
|
||||
#define ODM_REG_CHNBW_11N 0x18
|
||||
#define ODM_REG_T_METER_11N 0x24
|
||||
#define ODM_REG_RF_25_11N 0x25
|
||||
#define ODM_REG_RF_26_11N 0x26
|
||||
#define ODM_REG_RF_27_11N 0x27
|
||||
#define ODM_REG_RF_2B_11N 0x2B
|
||||
#define ODM_REG_RF_2C_11N 0x2C
|
||||
#define ODM_REG_RXRF_A3_11N 0x3C
|
||||
#define ODM_REG_T_METER_92D_11N 0x42
|
||||
#define ODM_REG_T_METER_88E_11N 0x42
|
||||
|
||||
|
||||
|
||||
//2 BB REG LIST
|
||||
//PAGE 8
|
||||
#define ODM_REG_BB_CTRL_11N 0x800
|
||||
#define ODM_REG_RF_PIN_11N 0x804
|
||||
#define ODM_REG_PSD_CTRL_11N 0x808
|
||||
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
|
||||
#define ODM_REG_BB_PWR_SAV5_11N 0x818
|
||||
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
|
||||
#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
|
||||
#define ODM_REG_RX_DEFUALT_A_11N 0x858
|
||||
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
|
||||
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
|
||||
#define ODM_REG_ANTSEL_CTRL_11N 0x860
|
||||
#define ODM_REG_RX_ANT_CTRL_11N 0x864
|
||||
#define ODM_REG_PIN_CTRL_11N 0x870
|
||||
#define ODM_REG_BB_PWR_SAV1_11N 0x874
|
||||
#define ODM_REG_ANTSEL_PATH_11N 0x878
|
||||
#define ODM_REG_BB_3WIRE_11N 0x88C
|
||||
#define ODM_REG_SC_CNT_11N 0x8C4
|
||||
#define ODM_REG_PSD_DATA_11N 0x8B4
|
||||
#define ODM_REG_CCX_PERIOD_11N 0x894
|
||||
#define ODM_REG_NHM_TH9_TH10_11N 0x890
|
||||
#define ODM_REG_CLM_11N 0x890
|
||||
#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
|
||||
#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
|
||||
#define ODM_REG_NHM_TH8_11N 0xe28
|
||||
#define ODM_REG_CLM_READY_11N 0x8b4
|
||||
#define ODM_REG_CLM_RESULT_11N 0x8d0
|
||||
#define ODM_REG_NHM_CNT_11N 0x8d8
|
||||
|
||||
// For ACS, Jeffery, 2014-12-26
|
||||
#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
|
||||
#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
|
||||
#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
|
||||
|
||||
//PAGE 9
|
||||
#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
|
||||
#define ODM_REG_DBG_RPT_11N 0x908
|
||||
#define ODM_REG_BB_TX_PATH_11N 0x90c
|
||||
#define ODM_REG_ANT_MAPPING1_11N 0x914
|
||||
#define ODM_REG_ANT_MAPPING2_11N 0x918
|
||||
#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
|
||||
#define ODM_REG_RX_DFIR_MOD_97F 0x948
|
||||
|
||||
//PAGE A
|
||||
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
|
||||
#define ODM_REG_CCK_ANT_SEL_11N 0xA04
|
||||
#define ODM_REG_CCK_CCA_11N 0xA0A
|
||||
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
|
||||
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
|
||||
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
|
||||
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
|
||||
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
|
||||
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
|
||||
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
|
||||
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
|
||||
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
|
||||
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
|
||||
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
|
||||
#define ODM_REG_CCK_FA_RST_11N 0xA2C
|
||||
#define ODM_REG_CCK_FA_MSB_11N 0xA58
|
||||
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
|
||||
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
|
||||
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
|
||||
//PAGE B
|
||||
#define ODM_REG_LNA_SWITCH_11N 0xB2C
|
||||
#define ODM_REG_PATH_SWITCH_11N 0xB30
|
||||
#define ODM_REG_RSSI_CTRL_11N 0xB38
|
||||
#define ODM_REG_CONFIG_ANTA_11N 0xB68
|
||||
#define ODM_REG_RSSI_BT_11N 0xB9C
|
||||
#define ODM_REG_RXCK_RFMOD 0xBB0
|
||||
#define ODM_REG_EDCCA_DCNF_97F 0xBC0
|
||||
|
||||
//PAGE C
|
||||
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
|
||||
#define ODM_REG_BB_RX_PATH_11N 0xC04
|
||||
#define ODM_REG_TRMUX_11N 0xC08
|
||||
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
|
||||
#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
|
||||
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
|
||||
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
|
||||
#define ODM_REG_IGI_A_11N 0xC50
|
||||
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
|
||||
#define ODM_REG_IGI_B_11N 0xC58
|
||||
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
|
||||
#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
|
||||
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
|
||||
#define ODM_REG_BB_AGC_SET_2_11N 0xc74
|
||||
#define ODM_REG_RX_OFF_11N 0xC7C
|
||||
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
|
||||
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
|
||||
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
|
||||
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
|
||||
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
|
||||
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
|
||||
#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
|
||||
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
|
||||
//PAGE D
|
||||
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
|
||||
#define ODM_REG_BB_RX_ANT_11N 0xD04
|
||||
#define ODM_REG_BB_ATC_11N 0xD2C
|
||||
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
|
||||
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
|
||||
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
|
||||
#define ODM_REG_RPT_11N 0xDF4
|
||||
//PAGE E
|
||||
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
|
||||
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
|
||||
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
|
||||
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
|
||||
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
|
||||
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
|
||||
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
|
||||
#define ODM_REG_EDCCA_DCNF_11N 0xE24
|
||||
#define ODM_REG_TAP_UPD_97F 0xE24
|
||||
#define ODM_REG_FPGA0_IQK_11N 0xE28
|
||||
#define ODM_REG_PAGE_B1_97F 0xE28
|
||||
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
|
||||
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
|
||||
#define ODM_REG_TXIQK_PI_A_11N 0xE38
|
||||
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
|
||||
#define ODM_REG_TXIQK_11N 0xE40
|
||||
#define ODM_REG_RXIQK_11N 0xE44
|
||||
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
|
||||
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
|
||||
#define ODM_REG_BLUETOOTH_11N 0xE6C
|
||||
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
|
||||
#define ODM_REG_TX_CCK_RFON_11N 0xE74
|
||||
#define ODM_REG_TX_CCK_BBON_11N 0xE78
|
||||
#define ODM_REG_OFDM_RFON_11N 0xE7C
|
||||
#define ODM_REG_OFDM_BBON_11N 0xE80
|
||||
#define ODM_REG_TX2RX_11N 0xE84
|
||||
#define ODM_REG_TX2TX_11N 0xE88
|
||||
#define ODM_REG_RX_CCK_11N 0xE8C
|
||||
#define ODM_REG_RX_OFDM_11N 0xED0
|
||||
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
|
||||
#define ODM_REG_RX2RX_11N 0xED8
|
||||
#define ODM_REG_STANDBY_11N 0xEDC
|
||||
#define ODM_REG_SLEEP_11N 0xEE0
|
||||
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
|
||||
/* PAGE F */
|
||||
#define ODM_REG_PAGE_F_RST_11N 0xF14
|
||||
#define ODM_REG_IGI_C_11N 0xF84
|
||||
#define ODM_REG_IGI_D_11N 0xF88
|
||||
#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
|
||||
#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
|
||||
#define ODM_REG_HT_CRC32_CNT_11N 0xF90
|
||||
#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
|
||||
|
||||
//2 MAC REG LIST
|
||||
#define ODM_REG_BB_RST_11N 0x02
|
||||
#define ODM_REG_ANTSEL_PIN_11N 0x4C
|
||||
#define ODM_REG_EARLY_MODE_11N 0x4D0
|
||||
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
|
||||
#define ODM_REG_EDCA_VO_11N 0x500
|
||||
#define ODM_REG_EDCA_VI_11N 0x504
|
||||
#define ODM_REG_EDCA_BE_11N 0x508
|
||||
#define ODM_REG_EDCA_BK_11N 0x50C
|
||||
#define ODM_REG_TXPAUSE_11N 0x522
|
||||
#define ODM_REG_RESP_TX_11N 0x6D8
|
||||
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
|
||||
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
|
||||
|
||||
|
||||
//DIG Related
|
||||
#define ODM_BIT_IGI_11N 0x0000007F
|
||||
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
|
||||
#define ODM_BIT_BB_RX_PATH_11N 0xF
|
||||
#define ODM_BIT_BB_TX_PATH_11N 0xF
|
||||
#define ODM_BIT_BB_ATC_11N BIT11
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,261 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __ODM_TYPES_H__
|
||||
#define __ODM_TYPES_H__
|
||||
|
||||
|
||||
/*Define Different SW team support*/
|
||||
#define ODM_AP 0x01 /*BIT0*/
|
||||
#define ODM_CE 0x04 /*BIT2*/
|
||||
#define ODM_WIN 0x08 /*BIT3*/
|
||||
#define ODM_ADSL 0x10 /*BIT4*/
|
||||
#define ODM_IOT 0x20 /*BIT5*/
|
||||
|
||||
/*Deifne HW endian support*/
|
||||
#define ODM_ENDIAN_BIG 0
|
||||
#define ODM_ENDIAN_LITTLE 1
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc)))
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv)))
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
||||
#define RT_PCI_INTERFACE 1
|
||||
#define RT_USB_INTERFACE 2
|
||||
#define RT_SDIO_INTERFACE 3
|
||||
#endif
|
||||
|
||||
typedef enum _HAL_STATUS{
|
||||
HAL_STATUS_SUCCESS,
|
||||
HAL_STATUS_FAILURE,
|
||||
/*RT_STATUS_PENDING,
|
||||
RT_STATUS_RESOURCE,
|
||||
RT_STATUS_INVALID_CONTEXT,
|
||||
RT_STATUS_INVALID_PARAMETER,
|
||||
RT_STATUS_NOT_SUPPORT,
|
||||
RT_STATUS_OS_API_FAILED,*/
|
||||
}HAL_STATUS,*PHAL_STATUS;
|
||||
|
||||
#if( DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#define MP_DRIVER 0
|
||||
#endif
|
||||
#if(DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
||||
|
||||
#define VISTA_USB_RX_REVISE 0
|
||||
|
||||
//
|
||||
// Declare for ODM spin lock defintion temporarily fro compile pass.
|
||||
//
|
||||
typedef enum _RT_SPINLOCK_TYPE{
|
||||
RT_TX_SPINLOCK = 1,
|
||||
RT_RX_SPINLOCK = 2,
|
||||
RT_RM_SPINLOCK = 3,
|
||||
RT_CAM_SPINLOCK = 4,
|
||||
RT_SCAN_SPINLOCK = 5,
|
||||
RT_LOG_SPINLOCK = 7,
|
||||
RT_BW_SPINLOCK = 8,
|
||||
RT_CHNLOP_SPINLOCK = 9,
|
||||
RT_RF_OPERATE_SPINLOCK = 10,
|
||||
RT_INITIAL_SPINLOCK = 11,
|
||||
RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30.
|
||||
#if VISTA_USB_RX_REVISE
|
||||
RT_USBRX_CONTEXT_SPINLOCK = 13,
|
||||
RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR
|
||||
#endif
|
||||
//Shall we define Ndis 6.2 SpinLock Here ?
|
||||
RT_PORT_SPINLOCK=16,
|
||||
RT_VNIC_SPINLOCK=17,
|
||||
RT_HVL_SPINLOCK=18,
|
||||
RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09.
|
||||
|
||||
RT_BTData_SPINLOCK=25,
|
||||
|
||||
RT_WAPI_OPTION_SPINLOCK=26,
|
||||
RT_WAPI_RX_SPINLOCK=27,
|
||||
|
||||
// add for 92D CCK control issue
|
||||
RT_CCK_PAGEA_SPINLOCK = 28,
|
||||
RT_BUFFER_SPINLOCK = 29,
|
||||
RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
|
||||
RT_GEN_TEMP_BUF_SPINLOCK = 31,
|
||||
RT_AWB_SPINLOCK = 32,
|
||||
RT_FW_PS_SPINLOCK = 33,
|
||||
RT_HW_TIMER_SPIN_LOCK = 34,
|
||||
RT_MPT_WI_SPINLOCK = 35,
|
||||
RT_P2P_SPIN_LOCK = 36, // Protect P2P context
|
||||
RT_DBG_SPIN_LOCK = 37,
|
||||
RT_IQK_SPINLOCK = 38,
|
||||
RT_PENDED_OID_SPINLOCK = 39,
|
||||
RT_CHNLLIST_SPINLOCK = 40,
|
||||
RT_INDIC_SPINLOCK = 41, //protect indication
|
||||
RT_RFD_SPINLOCK = 42,
|
||||
RT_SYNC_IO_CNT_SPINLOCK = 43,
|
||||
RT_LAST_SPINLOCK,
|
||||
}RT_SPINLOCK_TYPE;
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define STA_INFO_T RT_WLAN_STA
|
||||
#define PSTA_INFO_T PRT_WLAN_STA
|
||||
#define __func__ __FUNCTION__
|
||||
#define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT
|
||||
#define bMaskH3Bytes 0xffffff00
|
||||
#define SUCCESS 0
|
||||
#define FAIL (-1)
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
|
||||
#define ADSL_AP_BUILD_WORKAROUND
|
||||
#define AP_BUILD_WORKAROUND
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
#include "../typedef.h"
|
||||
#else
|
||||
typedef void VOID,*PVOID;
|
||||
typedef unsigned char BOOLEAN,*PBOOLEAN;
|
||||
typedef unsigned char u1Byte,*pu1Byte;
|
||||
typedef unsigned short u2Byte,*pu2Byte;
|
||||
typedef unsigned int u4Byte,*pu4Byte;
|
||||
typedef unsigned long long u8Byte,*pu8Byte;
|
||||
#if 1
|
||||
/* In ARM platform, system would use the type -- "char" as "unsigned char"
|
||||
* And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/
|
||||
typedef signed char s1Byte,*ps1Byte;
|
||||
#else
|
||||
typedef char s1Byte,*ps1Byte;
|
||||
#endif
|
||||
typedef short s2Byte,*ps2Byte;
|
||||
typedef long s4Byte,*ps4Byte;
|
||||
typedef long long s8Byte,*ps8Byte;
|
||||
#endif
|
||||
|
||||
typedef struct rtl8192cd_priv *prtl8192cd_priv;
|
||||
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
|
||||
typedef struct timer_list RT_TIMER, *PRT_TIMER;
|
||||
typedef void * RT_TIMER_CALL_BACK;
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define DEV_BUS_TYPE RT_PCI_INTERFACE
|
||||
#endif
|
||||
|
||||
#define _TRUE 1
|
||||
#define _FALSE 0
|
||||
|
||||
#if (defined(TESTCHIP_SUPPORT))
|
||||
#define PHYDM_TESTCHIP_SUPPORT 1
|
||||
#else
|
||||
#define PHYDM_TESTCHIP_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include <drv_types.h>
|
||||
#if 0
|
||||
typedef u8 u1Byte, *pu1Byte;
|
||||
typedef u16 u2Byte,*pu2Byte;
|
||||
typedef u32 u4Byte,*pu4Byte;
|
||||
typedef u64 u8Byte,*pu8Byte;
|
||||
typedef s8 s1Byte,*ps1Byte;
|
||||
typedef s16 s2Byte,*ps2Byte;
|
||||
typedef s32 s4Byte,*ps4Byte;
|
||||
typedef s64 s8Byte,*ps8Byte;
|
||||
#else
|
||||
#define u1Byte u8
|
||||
#define pu1Byte u8*
|
||||
|
||||
#define u2Byte u16
|
||||
#define pu2Byte u16*
|
||||
|
||||
#define u4Byte u32
|
||||
#define pu4Byte u32*
|
||||
|
||||
#define u8Byte u64
|
||||
#define pu8Byte u64*
|
||||
|
||||
#define s1Byte s8
|
||||
#define ps1Byte s8*
|
||||
|
||||
#define s2Byte s16
|
||||
#define ps2Byte s16*
|
||||
|
||||
#define s4Byte s32
|
||||
#define ps4Byte s32*
|
||||
|
||||
#define s8Byte s64
|
||||
#define ps8Byte s64*
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#define DEV_BUS_TYPE RT_USB_INTERFACE
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
#define DEV_BUS_TYPE RT_PCI_INTERFACE
|
||||
#elif defined(CONFIG_SDIO_HCI)
|
||||
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
|
||||
#elif defined(CONFIG_GSPI_HCI)
|
||||
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_LITTLE_ENDIAN)
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
|
||||
#elif defined (CONFIG_BIG_ENDIAN)
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
|
||||
#endif
|
||||
|
||||
typedef struct timer_list RT_TIMER, *PRT_TIMER;
|
||||
typedef void * RT_TIMER_CALL_BACK;
|
||||
#define STA_INFO_T struct sta_info
|
||||
#define PSTA_INFO_T struct sta_info *
|
||||
|
||||
|
||||
|
||||
#define TRUE _TRUE
|
||||
#define FALSE _FALSE
|
||||
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
|
||||
|
||||
//define useless flag to avoid compile warning
|
||||
#define USE_WORKITEM 0
|
||||
#define FOR_BRAZIL_PRETEST 0
|
||||
#define FPGA_TWO_MAC_VERIFICATION 0
|
||||
#define RTL8881A_SUPPORT 0
|
||||
|
||||
#if (defined(TESTCHIP_SUPPORT))
|
||||
#define PHYDM_TESTCHIP_SUPPORT 1
|
||||
#else
|
||||
#define PHYDM_TESTCHIP_SUPPORT 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
|
||||
#define COND_ELSE 2
|
||||
#define COND_ENDIF 3
|
||||
|
||||
#include "phydm_features.h"
|
||||
|
||||
#endif // __ODM_TYPES_H__
|
||||
|
||||
@@ -0,0 +1,481 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
|
||||
History:
|
||||
Data Who Remark (Internal History)
|
||||
|
||||
05/14/2012 MH Collect RTK inernal infromation and generate channel plan draft.
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
#include "rtchnlplan.h"
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Channel Plan Domain Code
|
||||
//
|
||||
|
||||
/*
|
||||
Channel Plan Contents
|
||||
Domain Code EEPROM Countries in Specific Domain
|
||||
2G RD 5G RD Bit[6:0] 2G 5G
|
||||
Case Old Define 00h~1Fh Old Define Old Define
|
||||
1 2G_WORLD 5G_NULL 20h Worldwird 13 NA
|
||||
2 2G_ETSI1 5G_NULL 21h Europe 2G NA
|
||||
3 2G_FCC1 5G_NULL 22h US 2G NA
|
||||
4 2G_MKK1 5G_NULL 23h Japan 2G NA
|
||||
5 2G_ETSI2 5G_NULL 24h France 2G NA
|
||||
6 2G_FCC1 5G_FCC1 25h US 2G US 5G 八大國認證
|
||||
7 2G_WORLD 5G_ETSI1 26h Worldwird 13 Europe 八大國認證
|
||||
8 2G_MKK1 5G_MKK1 27h Japan 2G Japan 5G 八大國認證
|
||||
9 2G_WORLD 5G_KCC1 28h Worldwird 13 Korea 八大國認證
|
||||
10 2G_WORLD 5G_FCC2 29h Worldwird 13 US o/w DFS Channels
|
||||
11 2G_WORLD 5G_FCC3 30h Worldwird 13 India, Mexico
|
||||
12 2G_WORLD 5G_FCC4 31h Worldwird 13 Venezuela
|
||||
13 2G_WORLD 5G_FCC5 32h Worldwird 13 China
|
||||
14 2G_WORLD 5G_FCC6 33h Worldwird 13 Israel
|
||||
15 2G_FCC1 5G_FCC7 34h US 2G US/Canada 八大國認證
|
||||
16 2G_WORLD 5G_ETSI2 35h Worldwird 13 Australia, New Zealand 八大國認證
|
||||
17 2G_WORLD 5G_ETSI3 36h Worldwird 13 Russia
|
||||
18 2G_MKK1 5G_MKK2 37h Japan 2G Japan (W52, W53)
|
||||
19 2G_MKK1 5G_MKK3 38h Japan 2G Japan (W56)
|
||||
20 2G_FCC1 5G_NCC1 39h US 2G Taiwan 八大國認證
|
||||
|
||||
NA 2G_WORLD 5G_FCC1 7F FCC FCC DFS Channels Realtek Define
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
2.4G Regulatory Domains
|
||||
Case 2G RD Regulation Channels Frequencyes Note Countries in Specific Domain
|
||||
1 2G_WORLD ETSI 1~13 2412~2472 Passive scan CH 12, 13 Worldwird 13
|
||||
2 2G_ETSI1 ETSI 1~13 2412~2472 Europe
|
||||
3 2G_FCC1 FCC 1~11 2412~2462 US
|
||||
4 2G_MKK1 MKK 1~13, 14 2412~2472, 2484 Japan
|
||||
5 2G_ETSI2 ETSI 10~13 2457~2472 France
|
||||
|
||||
|
||||
|
||||
|
||||
5G Regulatory Domains
|
||||
Case 5G RD Regulation Channels Frequencyes Note Countries in Specific Domain
|
||||
1 5G_NULL NA NA NA Do not support 5GHz
|
||||
2 5G_ETSI1 ETSI "36~48, 52~64,
|
||||
100~140" "5180~5240, 5260~5230
|
||||
5500~5700" Band1, Ban2, Band3 Europe
|
||||
3 5G_ETSI2 ETSI "36~48, 52~64,
|
||||
100~140, 149~165" "5180~5240, 5260~5230
|
||||
5500~5700, 5745~5825" Band1, Ban2, Band3, Band4 Australia, New Zealand
|
||||
4 5G_ETSI3 ETSI "36~48, 52~64,
|
||||
100~132, 149~165"
|
||||
"5180~5240, 5260~5230
|
||||
5500~5660, 5745~5825" Band1, Ban2, Band3(except CH 136, 140), Band4" Russia
|
||||
5 5G_FCC1 FCC "36~48, 52~64,
|
||||
100~140, 149~165"
|
||||
"5180~5240, 5260~5230
|
||||
5500~5700, 5745~5825" Band1(5150~5250MHz),
|
||||
Band2(5250~5350MHz),
|
||||
Band3(5470~5725MHz),
|
||||
Band4(5725~5850MHz)" US
|
||||
6 5G_FCC2 FCC 36~48, 149~165 5180~5240, 5745~5825 Band1, Band4 FCC o/w DFS Channels
|
||||
7 5G_FCC3 FCC "36~48, 52~64,
|
||||
149~165" "5180~5240, 5260~5230
|
||||
5745~5825" Band1, Ban2, Band4 India, Mexico
|
||||
8 5G_FCC4 FCC "36~48, 52~64,
|
||||
149~161" "5180~5240, 5260~5230
|
||||
5745~5805" Band1, Ban2,
|
||||
Band4(except CH 165)" Venezuela
|
||||
9 5G_FCC5 FCC 149~165 5745~5825 Band4 China
|
||||
10 5G_FCC6 FCC 36~48, 52~64 5180~5240, 5260~5230 Band1, Band2 Israel
|
||||
11 5G_FCC7
|
||||
5G_IC1 FCC
|
||||
IC" "36~48, 52~64,
|
||||
100~116, 136, 140,
|
||||
149~165" "5180~5240, 5260~5230
|
||||
5500~5580, 5680, 5700,
|
||||
5745~5825" "Band1, Band2,
|
||||
Band3(except 5600~5650MHz),
|
||||
Band4" "US
|
||||
Canada"
|
||||
12 5G_KCC1 KCC "36~48, 52~64,
|
||||
100~124, 149~165" "5180~5240, 5260~5230
|
||||
5500~5620, 5745~5825" "Band1, Ban2,
|
||||
Band3(5470~5650MHz),
|
||||
Band4" Korea
|
||||
13 5G_MKK1 MKK "36~48, 52~64,
|
||||
100~140" "5180~5240, 5260~5230
|
||||
5500~5700" W52, W53, W56 Japan
|
||||
14 5G_MKK2 MKK 36~48, 52~64 5180~5240, 5260~5230 W52, W53 Japan (W52, W53)
|
||||
15 5G_MKK3 MKK 100~140 5500~5700 W56 Japan (W56)
|
||||
16 5G_NCC1 NCC "56~64,
|
||||
100~116, 136, 140,
|
||||
149~165" "5260~5320
|
||||
5500~5580, 5680, 5700,
|
||||
5745~5825" "Band2(except CH 52),
|
||||
Band3(except 5600~5650MHz),
|
||||
Band4" Taiwan
|
||||
|
||||
|
||||
*/
|
||||
|
||||
//
|
||||
// 2.4G CHannel
|
||||
//
|
||||
/*
|
||||
|
||||
2.4G Band Regulatory Domains RTL8192D
|
||||
Channel Number Channel Frequency US Canada Europe Spain France Japan Japan 20M 40M
|
||||
(MHz) (FCC) (IC) (ETSI) (MPHPT)
|
||||
1 2412 v v v v v
|
||||
2 2417 v v v v v
|
||||
3 2422 v v v v v v
|
||||
4 2427 v v v v v v
|
||||
5 2432 v v v v v v
|
||||
6 2437 v v v v v v
|
||||
7 2442 v v v v v v
|
||||
8 2447 v v v v v v
|
||||
9 2452 v v v v v v
|
||||
10 2457 v v v v v v v v
|
||||
11 2462 v v v v v v v v
|
||||
12 2467 v v v v v
|
||||
13 2472 v v v v
|
||||
14 2484 v v
|
||||
|
||||
|
||||
*/
|
||||
|
||||
|
||||
//
|
||||
// 5G Operating Channel
|
||||
//
|
||||
/*
|
||||
|
||||
5G Band RTL8192D RTL8195 (Jaguar) Jaguar 2 Regulatory Domains
|
||||
Channel Number Channel Frequency Global Global Global "US
|
||||
(FCC 15.407)" "Canada
|
||||
(FCC, except 5.6~5.65GHz)" Argentina, Australia, New Zealand, Brazil, S. Africa (FCC/ETSI) "Europe
|
||||
(CE 301 893)" China India, Mexico, Singapore Israel, Turkey "Japan
|
||||
(MIC Item 19-3, 19-3-2)" Korea Russia, Ukraine "Taiwan
|
||||
(NCC)" Venezuela
|
||||
(MHz) (20MHz) (20MHz) (40MHz) (80MHz) (160MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz)
|
||||
"Band 1
|
||||
5.15GHz
|
||||
~
|
||||
5.25GHz" 36 5180 v v v v v Indoor Indoor v Indoor v Indoor Indoor v v v
|
||||
40 5200 v v v Indoor Indoor v Indoor v Indoor Indoor v v v
|
||||
44 5220 v v v v Indoor Indoor v Indoor v Indoor Indoor v v v
|
||||
48 5240 v v v Indoor Indoor v Indoor v Indoor Indoor v v v
|
||||
"Band 2
|
||||
5.25GHz
|
||||
~
|
||||
5.35GHz
|
||||
(DFS)" 52 5260 v v v v v v v v Indoor v Indoor Indoor v v v
|
||||
56 5280 v v v v v v Indoor v Indoor Indoor v v Indoor v
|
||||
60 5300 v v v v v v v Indoor v Indoor Indoor v v Indoor v
|
||||
64 5320 v v v v v v Indoor v Indoor Indoor v v Indoor v
|
||||
|
||||
"Band 3
|
||||
5.47GHz
|
||||
~
|
||||
5.725GHz
|
||||
(DFS)" 100 5500 v v v v v v v v v v v v v
|
||||
104 5520 v v v v v v v v v v v
|
||||
108 5540 v v v v v v v v v v v v
|
||||
112 5560 v v v v v v v v v v v
|
||||
116 5580 v v v v v v v v v v v v v
|
||||
120 5600 v v v Indoor v Indoor v v v
|
||||
124 5620 v v v v Indoor v Indoor v v v
|
||||
128 5640 v v v Indoor v Indoor v v
|
||||
132 5660 v v v E v Indoor v Indoor v v
|
||||
136 5680 v v v v v v v v v
|
||||
140 5700 v v E v v v v v v v
|
||||
144 5720 E E E
|
||||
"Band 4
|
||||
5.725GHz
|
||||
~
|
||||
5.85GHz
|
||||
(~5.9GHz)" 149 5745 v v v v v v v v v v v v v v
|
||||
153 5765 v v v v v v v v v v v v
|
||||
157 5785 v v v v v v v v v v v v v
|
||||
161 5805 v v v v v v v v v v v v
|
||||
165 5825 v v P P v v v v v v v v v
|
||||
169 5845 P P P
|
||||
173 5865 P P P P
|
||||
177 5885 P P P
|
||||
Channel Count 28 28 14 7 0 28 24 20 24 19 5 13 8 19 20 22 15 12
|
||||
E: FCC accepted the ask for CH144 from Accord. PS: 160MHz 用 80MHz+80MHz實現？ Argentina Belgium (比利時) India Israel Russia
|
||||
P: Customer's requirement from James. Australia The Netherlands (荷蘭) Mexico Turkey Ukraine
|
||||
New Zealand UK (英國) Singapore
|
||||
Brazil Switzerland (瑞士)
|
||||
|
||||
|
||||
*/
|
||||
|
||||
/*---------------------------Define Local Constant---------------------------*/
|
||||
|
||||
|
||||
// define Maximum Power v.s each band for each region
|
||||
// ISRAEL
|
||||
// Format:
|
||||
// RT_CHANNEL_DOMAIN_Region ={{{Chnl_Start, Chnl_end, Pwr_dB_Max}, {Chn2_Start, Chn2_end, Pwr_dB_Max}, {Chn3_Start, Chn3_end, Pwr_dB_Max}, {Chn4_Start, Chn4_end, Pwr_dB_Max}, {Chn5_Start, Chn5_end, Pwr_dB_Max}}, Limit_Num} */
|
||||
// RT_CHANNEL_DOMAIN_FCC ={{{01,11,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5}
|
||||
// "NR" is non-release channle.
|
||||
// Issue--- Israel--Russia--New Zealand
|
||||
// DOMAIN_01= (2G_WORLD, 5G_NULL)
|
||||
// DOMAIN_02= (2G_ETSI1, 5G_NULL)
|
||||
// DOMAIN_03= (2G_FCC1, 5G_NULL)
|
||||
// DOMAIN_04= (2G_MKK1, 5G_NULL)
|
||||
// DOMAIN_05= (2G_ETSI2, 5G_NULL)
|
||||
// DOMAIN_06= (2G_FCC1, 5G_FCC1)
|
||||
// DOMAIN_07= (2G_WORLD, 5G_ETSI1)
|
||||
// DOMAIN_08= (2G_MKK1, 5G_MKK1)
|
||||
// DOMAIN_09= (2G_WORLD, 5G_KCC1)
|
||||
// DOMAIN_10= (2G_WORLD, 5G_FCC2)
|
||||
// DOMAIN_11= (2G_WORLD, 5G_FCC3)----india
|
||||
// DOMAIN_12= (2G_WORLD, 5G_FCC4)----Venezuela
|
||||
// DOMAIN_13= (2G_WORLD, 5G_FCC5)----China
|
||||
// DOMAIN_14= (2G_WORLD, 5G_FCC6)----Israel
|
||||
// DOMAIN_15= (2G_FCC1, 5G_FCC7)-----Canada
|
||||
// DOMAIN_16= (2G_WORLD, 5G_ETSI2)---Australia
|
||||
// DOMAIN_17= (2G_WORLD, 5G_ETSI3)---Russia
|
||||
// DOMAIN_18= (2G_MKK1, 5G_MKK2)-----Japan
|
||||
// DOMAIN_19= (2G_MKK1, 5G_MKK3)-----Japan
|
||||
// DOMAIN_20= (2G_FCC1, 5G_NCC1)-----Taiwan
|
||||
// DOMAIN_21= (2G_FCC1, 5G_NCC1)-----Taiwan
|
||||
|
||||
|
||||
static RT_CHANNEL_PLAN_MAXPWR ChnlPlanPwrMax_2G[] = {
|
||||
|
||||
// 2G_WORLD,
|
||||
{{1, 13, 20}, 1},
|
||||
|
||||
// 2G_ETSI1
|
||||
{{1, 13, 20}, 1},
|
||||
|
||||
/* RT_CHANNEL_DOMAIN_ETSI */
|
||||
{{{1, 11, 17}, {40, 56, 17}, {60, 128, 17}, {0, 0, 0}, {149, 165, 17}}, 4},
|
||||
|
||||
// RT_CHANNEL_DOMAIN_MKK
|
||||
{{{1, 11, 17}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}}, 1},
|
||||
|
||||
// Add new channel plan mex power table.
|
||||
// ......
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
//===========================================1:(2G_WORLD, 5G_NULL)
|
||||
|
||||
RT_CHANNEL_PLAN_MAXPWR RT_DOMAIN_01 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1}
|
||||
|
||||
//===========================================2:(2G_ETSI1, 5G_NULL)
|
||||
|
||||
RT_DOMAIN_02 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1}
|
||||
|
||||
//===========================================3:(2G_FCC1, 5G_NULL)
|
||||
|
||||
RT_DOMAIN_03 ={{{01,11,30}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1}
|
||||
|
||||
//===========================================4:(2G_MKK1, 5G_NULL)
|
||||
|
||||
RT_DOMAIN_04 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1}
|
||||
|
||||
//===========================================5:(2G_ETSI2, 5G_NULL)
|
||||
|
||||
RT_DOMAIN_05 ={{{10,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1}
|
||||
|
||||
//===========================================6:(2G_FCC1, 5G_FCC1)
|
||||
|
||||
RT_DOMAIN_06 ={{{01,13,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5}
|
||||
|
||||
//===========================================7:(2G_WORLD, 5G_ETSI1)
|
||||
|
||||
RT_DOMAIN_07 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {NR,NR,0}}, 4}
|
||||
|
||||
//===========================================8:(2G_MKK1, 5G_MKK1)
|
||||
|
||||
RT_DOMAIN_08 ={{{01,14,23}, {36,48,23}, {52,64,23}, {100,140,23}, {NR,NR,0}}, 4}
|
||||
|
||||
//===========================================9:(2G_WORLD, 5G_KCC1)
|
||||
|
||||
RT_DOMAIN_09 ={{{01,13,20}, {36,48,17}, {52,64,23}, {100,124,23}, {149,165,23}}, 5}
|
||||
|
||||
//===========================================10:(2G_WORLD, 5G_FCC2)
|
||||
|
||||
RT_DOMAIN_10 ={{{01,13,20}, {36,48,17}, {NR,NR,0}, {NR,NR,0}, {149,165,30}}, 3}
|
||||
|
||||
//===========================================11:(2G_WORLD, 5G_FCC3)
|
||||
RT_DOMAIN_11 ={{{01,13,20}, {36,48,23}, {52,64,23}, {NR,NR,0}, {149,165,23}}, 4}
|
||||
|
||||
//===========================================12:(2G_WORLD, 5G_FCC4)
|
||||
RT_DOMAIN_12 ={{{01,13,20}, {36,48,24}, {52,64,24}, {NR,NR,0}, {149,161,27}}, 4}
|
||||
|
||||
//===========================================13:(2G_WORLD, 5G_FCC5)
|
||||
RT_DOMAIN_13 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {149,165,27}}, 2}
|
||||
|
||||
//===========================================14:(2G_WORLD, 5G_FCC6)
|
||||
RT_DOMAIN_14 ={{{01,13,20}, {36,48,17}, {52,64,17}, {NR,NR,0}, {NR,NR,0}}, 3}
|
||||
|
||||
//===========================================15:(2G_FCC1, 5G_FCC7)
|
||||
RT_DOMAIN_15 ={{{01,11,30}, {36,48,23}, {52,64,24}, {100,140,24}, {149,165,30}}, 5}
|
||||
|
||||
//===========================================16:(2G_WORLD, 5G_ETSI2)
|
||||
RT_DOMAIN_16 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5}
|
||||
|
||||
//===========================================17:(2G_WORLD, 5G_ETSI3)
|
||||
RT_DOMAIN_17 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,132,30}, {149,165,20}}, 5}
|
||||
|
||||
//===========================================18:(2G_MKK1, 5G_MKK2)
|
||||
RT_DOMAIN_18 ={{{01,14,23}, {36,48,23}, {52,64,23}, {NR,NR,0}, {NR,NR,0}}, 3}
|
||||
|
||||
//===========================================19:(2G_MKK1, 5G_MKK3)
|
||||
RT_DOMAIN_19 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {100,140,23}, {NR,NR,0}}, 2}
|
||||
|
||||
//===========================================20:(2G_FCC1, 5G_NCC1)
|
||||
RT_DOMAIN_20 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {100,140,24}, {149,165,30}}, 4}
|
||||
|
||||
//===========================================21:(2G_FCC1, 5G_NCC2)
|
||||
RT_DOMAIN_21 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {NR,NR,0}, {149,165,30}}, 3}
|
||||
|
||||
//===========================================22:(2G_WORLD, 5G_FCC3)
|
||||
RT_DOMAIN_22 ={{{01,13,24}, {36,48,20}, {52,64,24}, {NR,NR,0}, {149,165,30}}, 4}
|
||||
|
||||
//===========================================23:(2G_WORLD, 5G_ETSI2)
|
||||
RT_DOMAIN_23 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5}
|
||||
|
||||
*/
|
||||
|
||||
//
|
||||
// Counter & Realtek Channel plan transfer table.
|
||||
//
|
||||
RT_CHNL_CTRY_TBL RtCtryChnlTbl[] =
|
||||
{
|
||||
|
||||
{
|
||||
RT_CTRY_AL, // "Albania阿爾巴尼亞"
|
||||
"AL",
|
||||
RT_2G_WORLD,
|
||||
RT_5G_WORLD,
|
||||
RT_CHANNEL_DOMAIN_UNDEFINED // 2G/5G world.
|
||||
},
|
||||
#if 0
|
||||
{
|
||||
RT_CTRY_BB, // "Barbados巴巴多斯"
|
||||
"BB",
|
||||
RT_2G_WORLD,
|
||||
RT_5G_NULL,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x20 // 2G world. 5G_NULL
|
||||
},
|
||||
|
||||
{
|
||||
RT_CTRY_DE, // "Germany德國"
|
||||
"DE",
|
||||
RT_2G_WORLD,
|
||||
RT_5G_ETSI1,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x26
|
||||
},
|
||||
|
||||
{
|
||||
RT_CTRY_US, // "Germany德國"
|
||||
"US",
|
||||
RT_2G_FCC1,
|
||||
RT_5G_FCC7,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x34
|
||||
},
|
||||
|
||||
{
|
||||
RT_CTRY_JP, // "Germany德國"
|
||||
"JP",
|
||||
RT_2G_MKK1,
|
||||
RT_5G_MKK1,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x34
|
||||
},
|
||||
|
||||
{
|
||||
RT_CTRY_TW, // "Germany德國"
|
||||
"TW",
|
||||
RT_2G_FCC1,
|
||||
RT_5G_NCC1,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x39
|
||||
},
|
||||
#endif
|
||||
|
||||
}; // RtCtryChnlTbl
|
||||
|
||||
//
|
||||
// Realtek Defined Channel plan.
|
||||
//
|
||||
#if 0
|
||||
|
||||
static RT_CHANNEL_PLAN_NEW RtChnlPlan[] =
|
||||
{
|
||||
// Channel Plan 0x20.
|
||||
{
|
||||
&RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table.
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x20, // RT_CHANNEL_DOMAIN RT Channel Plan Define
|
||||
RT_2G_WORLD, // RT_REGULATION_2G
|
||||
RT_5G_NULL, // RT_REGULATION_5G
|
||||
RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition.
|
||||
RT_SREQ_NA, // RT Channel plan special & customerize requirement.
|
||||
|
||||
CHNL_RT_2G_WORLD,
|
||||
CHNL_RT_2G_WORLD_SCAN_TYPE,
|
||||
&ChnlPlanPwrMax_2G[0],
|
||||
|
||||
CHNL_RT_5G_NULL,
|
||||
CHNL_RT_5G_NULL_SCAN_TYPE,
|
||||
|
||||
|
||||
},
|
||||
|
||||
// Channel Plan 0x26.
|
||||
{
|
||||
&RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table.
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x26, // RT_CHANNEL_DOMAIN RT Channel Plan Define
|
||||
RT_2G_WORLD, // RT_REGULATION_2G
|
||||
RT_5G_ETSI1, // RT_REGULATION_5G
|
||||
RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition.
|
||||
RT_SREQ_NA, // RT Channel plan special & customerize requirement.
|
||||
|
||||
CHNL_RT_2G_WORLD, // 2G workd cannel
|
||||
CHNL_RT_2G_WORLD_SCAN_TYPE,
|
||||
&ChnlPlanPwrMax_2G[1],
|
||||
|
||||
CHNL_RT_5G_ETSI1,
|
||||
CHNL_RT_5G_ETSI1_SCAN_TYPE,
|
||||
|
||||
}
|
||||
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,699 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __RT_CHANNELPLAN_H__
|
||||
#define __RT_CHANNELPLAN_H__
|
||||
|
||||
typedef enum _RT_CHANNEL_DOMAIN_NEW
|
||||
{
|
||||
|
||||
//===== Add new channel plan above this line ===============//
|
||||
|
||||
// For new architecture we define different 2G/5G CH area for all country.
|
||||
// 2.4 G only
|
||||
RT_CHANNEL_DOMAIN_2G_WORLD_5G_NULL = 0x20,
|
||||
RT_CHANNEL_DOMAIN_2G_ETSI1_5G_NULL = 0x21,
|
||||
RT_CHANNEL_DOMAIN_2G_FCC1_5G_NULL = 0x22,
|
||||
RT_CHANNEL_DOMAIN_2G_MKK1_5G_NULL = 0x23,
|
||||
RT_CHANNEL_DOMAIN_2G_ETSI2_5G_NULL = 0x24,
|
||||
// 2.4 G + 5G type 1
|
||||
RT_CHANNEL_DOMAIN_2G_FCC1_5G_FCC1 = 0x25,
|
||||
RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x26,
|
||||
//RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x27,
|
||||
// .....
|
||||
|
||||
RT_CHANNEL_DOMAIN_MAX_NEW,
|
||||
|
||||
}RT_CHANNEL_DOMAIN_NEW, *PRT_CHANNEL_DOMAIN_NEW;
|
||||
|
||||
|
||||
#if 0
|
||||
#define DOMAIN_CODE_2G_WORLD \
|
||||
{1,2,3,4,5,6,7,8,9,10,11,12,13}, 13
|
||||
#define DOMAIN_CODE_2G_ETSI1 \
|
||||
{1,2,3,4,5,6,7,8,9,10,11,12,13}, 13
|
||||
#define DOMAIN_CODE_2G_ETSI2 \
|
||||
{1,2,3,4,5,6,7,8,9,10,11}, 11
|
||||
#define DOMAIN_CODE_2G_FCC1 \
|
||||
{1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14
|
||||
#define DOMAIN_CODE_2G_MKK1 \
|
||||
{10,11,12,13}, 4
|
||||
|
||||
#define DOMAIN_CODE_5G_ETSI1 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19
|
||||
#define DOMAIN_CODE_5G_ETSI2 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24
|
||||
#define DOMAIN_CODE_5G_ETSI3 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22
|
||||
#define DOMAIN_CODE_5G_FCC1 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24
|
||||
#define DOMAIN_CODE_5G_FCC2 \
|
||||
{36,40,44,48,149,153,157,161,165}, 9
|
||||
#define DOMAIN_CODE_5G_FCC3 \
|
||||
{36,40,44,48,52,56,60,64,149,153,157,161,165}, 13
|
||||
#define DOMAIN_CODE_5G_FCC4 \
|
||||
{36,40,44,48,52,56,60,64,149,153,157,161}, 12
|
||||
#define DOMAIN_CODE_5G_FCC5 \
|
||||
{149,153,157,161,165}, 5
|
||||
#define DOMAIN_CODE_5G_FCC6 \
|
||||
{36,40,44,48,52,56,60,64}, 8
|
||||
#define DOMAIN_CODE_5G_FCC7 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20
|
||||
#define DOMAIN_CODE_5G_IC1 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20
|
||||
#define DOMAIN_CODE_5G_KCC1 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20
|
||||
#define DOMAIN_CODE_5G_MKK1 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19
|
||||
#define DOMAIN_CODE_5G_MKK2 \
|
||||
{36,40,44,48,52,56,60,64}, 8
|
||||
#define DOMAIN_CODE_5G_MKK3 \
|
||||
{100,104,108,112,116,120,124,128,132,136,140}, 11
|
||||
#define DOMAIN_CODE_5G_NCC1 \
|
||||
{56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24
|
||||
#define DOMAIN_CODE_5G_NCC2 \
|
||||
{56,60,64,149,153,157,161,165}, 8
|
||||
#define UNDEFINED \
|
||||
{0}, 0
|
||||
#endif
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
/*
|
||||
|
||||
Countries "Country Abbreviation" Domain Code SKU's Ch# of 20MHz
|
||||
2G 5G Ch# of 40MHz
|
||||
"Albania阿爾巴尼亞" AL Local Test
|
||||
|
||||
"Algeria阿爾及利亞" DZ CE TCF
|
||||
|
||||
"Antigua & Barbuda安提瓜島&巴布達" AG 2G_WORLD FCC TCF
|
||||
|
||||
"Argentina阿根廷" AR 2G_WORLD Local Test
|
||||
|
||||
"Armenia亞美尼亞" AM 2G_WORLD ETSI
|
||||
|
||||
"Aruba阿魯巴島" AW 2G_WORLD FCC TCF
|
||||
|
||||
"Australia澳洲" AU 2G_WORLD 5G_ETSI2
|
||||
|
||||
"Austria奧地利" AT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Azerbaijan阿塞拜彊" AZ 2G_WORLD CE TCF
|
||||
|
||||
"Bahamas巴哈馬" BS 2G_WORLD
|
||||
|
||||
"Barbados巴巴多斯" BB 2G_WORLD FCC TCF
|
||||
|
||||
"Belgium比利時" BE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Bermuda百慕達" BM 2G_WORLD FCC TCF
|
||||
|
||||
"Brazil巴西" BR 2G_WORLD Local Test
|
||||
|
||||
"Bulgaria保加利亞" BG 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Canada加拿大" CA 2G_FCC1 5G_FCC7 IC / FCC IC / FCC
|
||||
|
||||
"Cayman Islands開曼群島" KY 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Chile智利" CL 2G_WORLD FCC TCF
|
||||
|
||||
"China中國" CN 2G_WORLD 5G_FCC5 信部?【2002】353?
|
||||
|
||||
"Columbia哥倫比亞" CO 2G_WORLD Voluntary
|
||||
|
||||
"Costa Rica哥斯達黎加" CR 2G_WORLD FCC TCF
|
||||
|
||||
"Cyprus塞浦路斯" CY 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Czech 捷克" CZ 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Denmark丹麥" DK 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Dominican Republic多明尼加共和國" DO 2G_WORLD FCC TCF
|
||||
|
||||
"Egypt埃及" EG 2G_WORLD CE T CF
|
||||
|
||||
"El Salvador薩爾瓦多" SV 2G_WORLD Voluntary
|
||||
|
||||
"Estonia愛沙尼亞" EE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Finland芬蘭" FI 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"France法國" FR 5G_E TSI1 CE
|
||||
|
||||
"Germany德國" DE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Greece 希臘" GR 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Guam關島" GU 2G_WORLD
|
||||
|
||||
"Guatemala瓜地馬拉" GT 2G_WORLD
|
||||
|
||||
"Haiti海地" HT 2G_WORLD FCC TCF
|
||||
|
||||
"Honduras宏都拉斯" HN 2G_WORLD FCC TCF
|
||||
|
||||
"Hungary匈牙利" HU 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Iceland冰島" IS 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"India印度" IN 2G_WORLD 5G_FCC3 FCC/CE TCF
|
||||
|
||||
"Ireland愛爾蘭" IE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Israel以色列" IL 5G_F CC6 CE TCF
|
||||
|
||||
"Italy義大利" IT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Japan日本" JP 2G_MKK1 5G_MKK1 MKK MKK
|
||||
|
||||
"Korea韓國" KR 2G_WORLD 5G_KCC1 KCC KCC
|
||||
|
||||
"Latvia拉脫維亞" LV 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Lithuania立陶宛" LT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Luxembourg盧森堡" LU 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Malaysia馬來西亞" MY 2G_WORLD Local Test
|
||||
|
||||
"Malta馬爾他" MT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Mexico墨西哥" MX 2G_WORLD 5G_FCC3 Local Test
|
||||
|
||||
"Morocco摩洛哥" MA CE TCF
|
||||
|
||||
"Netherlands荷蘭" NL 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"New Zealand紐西蘭" NZ 2G_WORLD 5G_ETSI2
|
||||
|
||||
"Norway挪威" NO 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Panama巴拿馬 " PA 2G_FCC1 Voluntary
|
||||
|
||||
"Philippines菲律賓" PH 2G_WORLD FCC TCF
|
||||
|
||||
"Poland波蘭" PL 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Portugal葡萄牙" PT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Romania羅馬尼亞" RO 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Russia俄羅斯" RU 2G_WORLD 5G_ETSI3 CE TCF
|
||||
|
||||
"Saudi Arabia沙地阿拉伯" SA 2G_WORLD CE TCF
|
||||
|
||||
"Singapore新加坡" SG 2G_WORLD
|
||||
|
||||
"Slovakia斯洛伐克" SK 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Slovenia斯洛維尼亞" SI 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"South Africa南非" ZA 2G_WORLD CE TCF
|
||||
|
||||
"Spain西班牙" ES 5G_ETSI1 CE
|
||||
|
||||
"Sweden瑞典" SE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Switzerland瑞士" CH 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Taiwan臺灣" TW 2G_FCC1 5G_NCC1 NCC
|
||||
|
||||
"Thailand泰國" TH 2G_WORLD FCC/CE TCF
|
||||
|
||||
"Turkey土耳其" TR 2G_WORLD
|
||||
|
||||
"Ukraine烏克蘭" UA 2G_WORLD Local Test
|
||||
|
||||
"United Kingdom英國" GB 2G_WORLD 5G_ETSI1 CE ETSI
|
||||
|
||||
"United States美國" US 2G_FCC1 5G_FCC7 FCC FCC
|
||||
|
||||
"Venezuela委內瑞拉" VE 2G_WORLD 5G_FCC4 FCC TCF
|
||||
|
||||
"Vietnam越南" VN 2G_WORLD FCC/CE TCF
|
||||
|
||||
|
||||
|
||||
*/
|
||||
|
||||
// Counter abbervation.
|
||||
typedef enum _RT_COUNTRY_DEFINE_NUM
|
||||
{
|
||||
RT_CTRY_AL, // "Albania阿爾巴尼亞"
|
||||
RT_CTRY_DZ, // "Algeria阿爾及利亞"
|
||||
RT_CTRY_AG, // "Antigua & Barbuda安提瓜島&巴布達"
|
||||
RT_CTRY_AR, // "Argentina阿根廷"
|
||||
RT_CTRY_AM, // "Armenia亞美尼亞"
|
||||
RT_CTRY_AW, // "Aruba阿魯巴島"
|
||||
RT_CTRY_AU, // "Australia澳洲"
|
||||
RT_CTRY_AT, // "Austria奧地利"
|
||||
RT_CTRY_AZ, // "Azerbaijan阿塞拜彊"
|
||||
RT_CTRY_BS, // "Bahamas巴哈馬"
|
||||
RT_CTRY_BB, // "Barbados巴巴多斯"
|
||||
RT_CTRY_BE, // "Belgium比利時"
|
||||
RT_CTRY_BM, // "Bermuda百慕達"
|
||||
RT_CTRY_BR, // "Brazil巴西"
|
||||
RT_CTRY_BG, // "Bulgaria保加利亞"
|
||||
RT_CTRY_CA, // "Canada加拿大"
|
||||
RT_CTRY_KY, // "Cayman Islands開曼群島"
|
||||
RT_CTRY_CL, // "Chile智利"
|
||||
RT_CTRY_CN, // "China中國"
|
||||
RT_CTRY_CO, // "Columbia哥倫比亞"
|
||||
RT_CTRY_CR, // "Costa Rica哥斯達黎加"
|
||||
RT_CTRY_CY, // "Cyprus塞浦路斯"
|
||||
RT_CTRY_CZ, // "Czech 捷克"
|
||||
RT_CTRY_DK, // "Denmark丹麥"
|
||||
RT_CTRY_DO, // "Dominican Republic多明尼加共和國"
|
||||
RT_CTRY_CE, // "Egypt埃及" EG 2G_WORLD
|
||||
RT_CTRY_SV, // "El Salvador薩爾瓦多"
|
||||
RT_CTRY_EE, // "Estonia愛沙尼亞"
|
||||
RT_CTRY_FI, // "Finland芬蘭"
|
||||
RT_CTRY_FR, // "France法國"
|
||||
RT_CTRY_DE, // "Germany德國"
|
||||
RT_CTRY_GR, // "Greece 希臘"
|
||||
RT_CTRY_GU, // "Guam關島"
|
||||
RT_CTRY_GT, // "Guatemala瓜地馬拉"
|
||||
RT_CTRY_HT, // "Haiti海地"
|
||||
RT_CTRY_HN, // "Honduras宏都拉斯"
|
||||
RT_CTRY_HU, // "Hungary匈牙利"
|
||||
RT_CTRY_IS, // "Iceland冰島"
|
||||
RT_CTRY_IN, // "India印度"
|
||||
RT_CTRY_IE, // "Ireland愛爾蘭"
|
||||
RT_CTRY_IL, // "Israel以色列"
|
||||
RT_CTRY_IT, // "Italy義大利"
|
||||
RT_CTRY_JP, // "Japan日本"
|
||||
RT_CTRY_KR, // "Korea韓國"
|
||||
RT_CTRY_LV, // "Latvia拉脫維亞"
|
||||
RT_CTRY_LT, // "Lithuania立陶宛"
|
||||
RT_CTRY_LU, // "Luxembourg盧森堡"
|
||||
RT_CTRY_MY, // "Malaysia馬來西亞"
|
||||
RT_CTRY_MT, // "Malta馬爾他"
|
||||
RT_CTRY_MX, // "Mexico墨西哥"
|
||||
RT_CTRY_MA, // "Morocco摩洛哥"
|
||||
RT_CTRY_NL, // "Netherlands荷蘭"
|
||||
RT_CTRY_NZ, // "New Zealand紐西蘭"
|
||||
RT_CTRY_NO, // "Norway挪威"
|
||||
RT_CTRY_PA, // "Panama巴拿馬 "
|
||||
RT_CTRY_PH, // "Philippines菲律賓"
|
||||
RT_CTRY_PL, // "Poland波蘭"
|
||||
RT_CTRY_PT, // "Portugal葡萄牙"
|
||||
RT_CTRY_RO, // "Romania羅馬尼亞"
|
||||
RT_CTRY_RU, // "Russia俄羅斯"
|
||||
RT_CTRY_SA, // "Saudi Arabia沙地阿拉伯"
|
||||
RT_CTRY_SG, // "Singapore新加坡"
|
||||
RT_CTRY_SK, // "Slovakia斯洛伐克"
|
||||
RT_CTRY_SI, // "Slovenia斯洛維尼亞"
|
||||
RT_CTRY_ZA, // "South Africa南非"
|
||||
RT_CTRY_ES, // "Spain西班牙"
|
||||
RT_CTRY_SE, // "Sweden瑞典"
|
||||
RT_CTRY_CH, // "Switzerland瑞士"
|
||||
RT_CTRY_TW, // "Taiwan臺灣"
|
||||
RT_CTRY_TH, // "Thailand泰國"
|
||||
RT_CTRY_TR, // "Turkey土耳其"
|
||||
RT_CTRY_UA, // "Ukraine烏克蘭"
|
||||
RT_CTRY_GB, // "United Kingdom英國"
|
||||
RT_CTRY_US, // "United States美國"
|
||||
RT_CTRY_VE, // "Venezuela委內瑞拉"
|
||||
RT_CTRY_VN, // "Vietnam越南"
|
||||
RT_CTRY_MAX, //
|
||||
|
||||
}RT_COUNTRY_NAME, *PRT_COUNTRY_NAME;
|
||||
|
||||
// Scan type including active and passive scan.
|
||||
typedef enum _RT_SCAN_TYPE_NEW
|
||||
{
|
||||
SCAN_NULL,
|
||||
SCAN_ACT,
|
||||
SCAN_PAS,
|
||||
SCAN_BOTH,
|
||||
}RT_SCAN_TYPE_NEW, *PRT_SCAN_TYPE_NEW;
|
||||
|
||||
|
||||
// Power table sample.
|
||||
|
||||
typedef struct _RT_CHNL_PLAN_LIMIT
|
||||
{
|
||||
u2Byte Chnl_Start;
|
||||
u2Byte Chnl_end;
|
||||
|
||||
u2Byte Freq_Start;
|
||||
u2Byte Freq_end;
|
||||
}RT_CHNL_PLAN_LIMIT, *PRT_CHNL_PLAN_LIMIT;
|
||||
|
||||
|
||||
//
|
||||
// 2.4G Regulatory Domains
|
||||
//
|
||||
typedef enum _RT_REGULATION_DOMAIN_2G
|
||||
{
|
||||
RT_2G_NULL,
|
||||
RT_2G_WORLD,
|
||||
RT_2G_ETSI1,
|
||||
RT_2G_FCC1,
|
||||
RT_2G_MKK1,
|
||||
RT_2G_ETSI2
|
||||
|
||||
}RT_REGULATION_2G, *PRT_REGULATION_2G;
|
||||
|
||||
|
||||
//typedef struct _RT_CHANNEL_BEHAVIOR
|
||||
//{
|
||||
// u1Byte Chnl;
|
||||
// RT_SCAN_TYPE_NEW
|
||||
//
|
||||
//}RT_CHANNEL_BEHAVIOR, *PRT_CHANNEL_BEHAVIOR;
|
||||
|
||||
//typedef struct _RT_CHANNEL_PLAN_TYPE
|
||||
//{
|
||||
// RT_CHANNEL_BEHAVIOR
|
||||
// u1Byte Chnl_num;
|
||||
//}RT_CHNL_PLAN_TYPE, *PRT_CHNL_PLAN_TYPE;
|
||||
|
||||
//
|
||||
// 2.4G Channel Number
|
||||
// Channel definition & number
|
||||
//
|
||||
#define CHNL_RT_2G_NULL \
|
||||
{0}, 0
|
||||
#define CHNL_RT_2G_WORLD \
|
||||
{1,2,3,4,5,6,7,8,9,10,11,12,13}, 13
|
||||
#define CHNL_RT_2G_WORLD_TEST \
|
||||
{1,2,3,4,5,6,7,8,9,10,11,12,13}, 13
|
||||
|
||||
#define CHNL_RT_2G_EFSI1 \
|
||||
{1,2,3,4,5,6,7,8,9,10,11,12,13}, 13
|
||||
#define CHNL_RT_2G_FCC1 \
|
||||
{1,2,3,4,5,6,7,8,9,10,11}, 11
|
||||
#define CHNL_RT_2G_MKK1 \
|
||||
{1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14
|
||||
#define CHNL_RT_2G_ETSI2 \
|
||||
{10,11,12,13}, 4
|
||||
|
||||
//
|
||||
// 2.4G Channel Active or passive scan.
|
||||
//
|
||||
#define CHNL_RT_2G_NULL_SCAN_TYPE \
|
||||
{SCAN_NULL}
|
||||
#define CHNL_RT_2G_WORLD_SCAN_TYPE \
|
||||
{1,1,1,1,1,1,1,1,1,1,1,0,0}
|
||||
#define CHNL_RT_2G_EFSI1_SCAN_TYPE \
|
||||
{1,1,1,1,1,1,1,1,1,1,1,1,1}
|
||||
#define CHNL_RT_2G_FCC1_SCAN_TYPE \
|
||||
{1,1,1,1,1,1,1,1,1,1,1}
|
||||
#define CHNL_RT_2G_MKK1_SCAN_TYPE \
|
||||
{1,1,1,1,1,1,1,1,1,1,1,1,1,1}
|
||||
#define CHNL_RT_2G_ETSI2_SCAN_TYPE \
|
||||
{1,1,1,1}
|
||||
|
||||
|
||||
//
|
||||
// 2.4G Band & Frequency Section
|
||||
// Freqency start & end / band number
|
||||
//
|
||||
#define FREQ_RT_2G_NULL \
|
||||
{0}, 0
|
||||
// Passive scan CH 12, 13
|
||||
#define FREQ_RT_2G_WORLD \
|
||||
{2412, 2472}, 1
|
||||
#define FREQ_RT_2G_EFSI1 \
|
||||
{2412, 2472}, 1
|
||||
#define FREQ_RT_2G_FCC1 \
|
||||
{2412, 2462}, 1
|
||||
#define FREQ_RT_2G_MKK1 \
|
||||
{2412, 2484}, 1
|
||||
#define FREQ_RT_2G_ETSI2 \
|
||||
{2457, 2472}, 1
|
||||
|
||||
|
||||
//
|
||||
// 5G Regulatory Domains
|
||||
//
|
||||
typedef enum _RT_REGULATION_DOMAIN_5G
|
||||
{
|
||||
RT_5G_NULL,
|
||||
RT_5G_WORLD,
|
||||
RT_5G_ETSI1,
|
||||
RT_5G_ETSI2,
|
||||
RT_5G_ETSI3,
|
||||
RT_5G_FCC1,
|
||||
RT_5G_FCC2,
|
||||
RT_5G_FCC3,
|
||||
RT_5G_FCC4,
|
||||
RT_5G_FCC5,
|
||||
RT_5G_FCC6,
|
||||
RT_5G_FCC7,
|
||||
RT_5G_IC1,
|
||||
RT_5G_KCC1,
|
||||
RT_5G_MKK1,
|
||||
RT_5G_MKK2,
|
||||
RT_5G_MKK3,
|
||||
RT_5G_NCC1,
|
||||
|
||||
}RT_REGULATION_5G, *PRT_REGULATION_5G;
|
||||
|
||||
//
|
||||
// 5G Channel Number
|
||||
//
|
||||
#define CHNL_RT_5G_NULL \
|
||||
{0}, 0
|
||||
#define CHNL_RT_5G_WORLD \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19
|
||||
#define CHNL_RT_5G_ETSI1 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24
|
||||
#define CHNL_RT_5G_ETSI2 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22
|
||||
#define CHNL_RT_5G_ETSI3 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24
|
||||
#define CHNL_RT_5G_FCC1 \
|
||||
{36,40,44,48,149,153,157,161,165}, 9
|
||||
#define CHNL_RT_5G_FCC2 \
|
||||
{36,40,44,48,52,56,60,64,149,153,157,161,165}, 13
|
||||
#define CHNL_RT_5G_FCC3 \
|
||||
{36,40,44,48,52,56,60,64,149,153,157,161}, 12
|
||||
#define CHNL_RT_5G_FCC4 \
|
||||
{149,153,157,161,165}, 5
|
||||
#define CHNL_RT_5G_FCC5 \
|
||||
{36,40,44,48,52,56,60,64}, 8
|
||||
#define CHNL_RT_5G_FCC6 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20
|
||||
#define CHNL_RT_5G_FCC7 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20
|
||||
#define CHNL_RT_5G_IC1 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20
|
||||
#define CHNL_RT_5G_KCC1 \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19
|
||||
#define CHNL_RT_5G_MKK1 \
|
||||
{36,40,44,48,52,56,60,64}, 8
|
||||
#define CHNL_RT_5G_MKK2 \
|
||||
{100,104,108,112,116,120,124,128,132,136,140}, 11
|
||||
#define CHNL_RT_5G_MKK3 \
|
||||
{56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24
|
||||
#define CHNL_RT_5G_NCC1 \
|
||||
{56,60,64,149,153,157,161,165}, 8
|
||||
|
||||
//
|
||||
// 5G Channel Active or passive scan.
|
||||
//
|
||||
#define CHNL_RT_5G_NULL_SCAN_TYPE \
|
||||
{SCAN_NULL}
|
||||
#define CHNL_RT_5G_WORLD_SCAN_TYPE \
|
||||
{1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}
|
||||
#define CHNL_RT_5G_ETSI1_SCAN_TYPE \
|
||||
{1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}
|
||||
#define CHNL_RT_5G_ETSI2_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22
|
||||
#define CHNL_RT_5G_ETSI3_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24
|
||||
#define CHNL_RT_5G_FCC1_SCAN_TYPE \
|
||||
{36,40,44,48,149,153,157,161,165}, 9
|
||||
#define CHNL_RT_5G_FCC2_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64,149,153,157,161,165}, 13
|
||||
#define CHNL_RT_5G_FCC3_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64,149,153,157,161}, 12
|
||||
#define CHNL_RT_5G_FCC4_SCAN_TYPE \
|
||||
{149,153,157,161,165}, 5
|
||||
#define CHNL_RT_5G_FCC5_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64}, 8
|
||||
#define CHNL_RT_5G_FCC6_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20
|
||||
#define CHNL_RT_5G_FCC7_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20
|
||||
#define CHNL_RT_5G_IC1_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20
|
||||
#define CHNL_RT_5G_KCC1_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19
|
||||
#define CHNL_RT_5G_MKK1_SCAN_TYPE \
|
||||
{36,40,44,48,52,56,60,64}, 8
|
||||
#define CHNL_RT_5G_MKK2_SCAN_TYPE \
|
||||
{100,104,108,112,116,120,124,128,132,136,140}, 11
|
||||
#define CHNL_RT_5G_MKK3_SCAN_TYPE \
|
||||
{56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24
|
||||
#define CHNL_RT_5G_NCC1_SCAN_TYPE \
|
||||
{56,60,64,149,153,157,161,165}, 8
|
||||
|
||||
//
|
||||
// Global Regulation
|
||||
//
|
||||
typedef enum _RT_REGULATION_COMMON
|
||||
{
|
||||
RT_WORLD,
|
||||
RT_FCC,
|
||||
RT_MKK,
|
||||
RT_ETSI,
|
||||
RT_IC,
|
||||
RT_CE,
|
||||
RT_NCC,
|
||||
|
||||
}RT_REGULATION_CMN, *PRT_REGULATION_CMN;
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Special requirement for different regulation domain.
|
||||
// For internal test or customerize special request.
|
||||
//
|
||||
typedef enum _RT_CHNLPLAN_SREQ
|
||||
{
|
||||
RT_SREQ_NA = 0x0,
|
||||
RT_SREQ_2G_ADHOC_11N = 0x00000001,
|
||||
RT_SREQ_2G_ADHOC_11B = 0x00000002,
|
||||
RT_SREQ_2G_ALL_PASS = 0x00000004,
|
||||
RT_SREQ_2G_ALL_ACT = 0x00000008,
|
||||
RT_SREQ_5G_ADHOC_11N = 0x00000010,
|
||||
RT_SREQ_5G_ADHOC_11AC = 0x00000020,
|
||||
RT_SREQ_5G_ALL_PASS = 0x00000040,
|
||||
RT_SREQ_5G_ALL_ACT = 0x00000080,
|
||||
RT_SREQ_C1_PLAN = 0x00000100,
|
||||
RT_SREQ_C2_PLAN = 0x00000200,
|
||||
RT_SREQ_C3_PLAN = 0x00000400,
|
||||
RT_SREQ_C4_PLAN = 0x00000800,
|
||||
RT_SREQ_NFC_ON = 0x00001000,
|
||||
RT_SREQ_MASK = 0x0000FFFF, /* Requirements bit mask */
|
||||
|
||||
}RT_CHNLPLAN_SREQ, *PRT_CHNLPLAN_SREQ;
|
||||
|
||||
|
||||
//
|
||||
// RT_COUNTRY_NAME & RT_REGULATION_2G & RT_REGULATION_5G transfer table
|
||||
//
|
||||
//
|
||||
typedef struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE
|
||||
{
|
||||
//
|
||||
// Define countery domain and corresponding
|
||||
//
|
||||
RT_COUNTRY_NAME Country_Enum;
|
||||
char Country_Name[3];
|
||||
|
||||
//char Domain_Name[12];
|
||||
RT_REGULATION_2G Domain_2G;
|
||||
|
||||
RT_REGULATION_5G Domain_5G;
|
||||
|
||||
RT_CHANNEL_DOMAIN RtChDomain;
|
||||
//u1Byte Country_Area;
|
||||
|
||||
}RT_CHNL_CTRY_TBL, *PRT_CHNL_CTRY_TBL;
|
||||
|
||||
|
||||
#define RT_MAX_CHNL_NUM_2G 13
|
||||
#define RT_MAX_CHNL_NUM_5G 44
|
||||
|
||||
// Power table sample.
|
||||
|
||||
typedef struct _RT_CHNL_PLAN_PWR_LIMIT
|
||||
{
|
||||
u2Byte Chnl_Start;
|
||||
u2Byte Chnl_end;
|
||||
u1Byte dB_Max;
|
||||
u2Byte mW_Max;
|
||||
}RT_CHNL_PWR_LIMIT, *PRT_CHNL_PWR_LIMIT;
|
||||
|
||||
|
||||
#define RT_MAX_BAND_NUM 5
|
||||
|
||||
typedef struct _RT_CHANNEL_PLAN_MAXPWR
|
||||
{
|
||||
// STRING_T
|
||||
RT_CHNL_PWR_LIMIT Chnl[RT_MAX_BAND_NUM];
|
||||
u1Byte Band_Useful_Num;
|
||||
|
||||
|
||||
}RT_CHANNEL_PLAN_MAXPWR, *PRT_CHANNEL_PLAN_MAXPWR;
|
||||
|
||||
|
||||
//
|
||||
// Power By Rate Table.
|
||||
//
|
||||
|
||||
|
||||
|
||||
typedef struct _RT_CHANNEL_PLAN_NEW
|
||||
{
|
||||
//
|
||||
// Define countery domain and corresponding
|
||||
//
|
||||
//char Country_Name[36];
|
||||
//u1Byte Country_Enum;
|
||||
|
||||
//char Domain_Name[12];
|
||||
|
||||
|
||||
PRT_CHNL_CTRY_TBL pCtryTransfer;
|
||||
|
||||
RT_CHANNEL_DOMAIN RtChDomain;
|
||||
|
||||
RT_REGULATION_2G Domain_2G;
|
||||
|
||||
RT_REGULATION_5G Domain_5G;
|
||||
|
||||
RT_REGULATION_CMN Regulator;
|
||||
|
||||
RT_CHNLPLAN_SREQ ChnlSreq;
|
||||
|
||||
//RT_CHNL_PLAN_LIMIT RtChnl;
|
||||
|
||||
u1Byte Chnl2G[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD
|
||||
u1Byte Len2G;
|
||||
u1Byte Chnl2GScanTp[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD_SCAN_TYPE
|
||||
//u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD
|
||||
|
||||
u1Byte Chnl5G[MAX_CHANNEL_NUM];
|
||||
u1Byte Len5G;
|
||||
u1Byte Chnl5GScanTp[MAX_CHANNEL_NUM];
|
||||
//u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD
|
||||
|
||||
RT_CHANNEL_PLAN_MAXPWR ChnlMaxPwr;
|
||||
|
||||
|
||||
}RT_CHANNEL_PLAN_NEW, *PRT_CHANNEL_PLAN_NEW;
|
||||
|
||||
|
||||
#endif // __RT_CHANNELPLAN_H__
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,927 @@
|
||||
/*****************************************************************************
|
||||
* Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved.
|
||||
*
|
||||
* Module: __INC_HAL8723DREG_H
|
||||
*
|
||||
*
|
||||
* Note: 1. Define Mac register address and corresponding bit mask map
|
||||
*
|
||||
*
|
||||
* Export: Constants, macro, functions(API), global variables(None).
|
||||
*
|
||||
* Abbrev:
|
||||
*
|
||||
* History:
|
||||
* Data Who Remark
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8723DREG_H
|
||||
#define __INC_HAL8723DREG_H
|
||||
|
||||
|
||||
|
||||
//============================================================
|
||||
//
|
||||
//============================================================
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0000h ~ 0x00FFh System Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_SYS_ISO_CTRL_8723D 0x0000 // 2 Byte
|
||||
#define REG_SYS_FUNC_EN_8723D 0x0002 // 2 Byte
|
||||
#define REG_SYS_PW_CTRL_8723D 0x0004 // 4 Byte
|
||||
#define REG_SYS_CLKR_8723D 0x0008 // 2 Byte
|
||||
#define REG_SYS_EEPROM_CTRL_8723D 0x000A // 2 Byte
|
||||
#define REG_EE_VPD_8723D 0x000C // 2 Byte
|
||||
#define REG_SYS_SWR_CTRL1_8723D 0x0010 // 1 Byte
|
||||
#define REG_SYS_SWR_CTRL2_8723D 0x0014 // 1 Byte
|
||||
#define REG_SYS_SWR_CTRL3_8723D 0x0018 // 4 Byte
|
||||
#define REG_RSV_CTRL_8723D 0x001C // 3 Byte
|
||||
#define REG_RF_CTRL_8723D 0x001F // 1 Byte
|
||||
#define REG_AFE_CTRL1_8723D 0x0024 // 4 Byte
|
||||
#define REG_AFE_CTRL2_8723D 0x0028 // 4 Byte
|
||||
#define REG_AFE_CTRL3_8723D 0x002c // 4 Byte
|
||||
#define REG_EFUSE_CTRL_8723D 0x0030
|
||||
#define REG_LDO_EFUSE_CTRL_8723D 0x0034
|
||||
#define REG_PWR_DATA_8723D 0x0038
|
||||
#define REG_CAL_TIMER_8723D 0x003C
|
||||
#define REG_ACLK_MON_8723D 0x003E
|
||||
#define REG_GPIO_MUXCFG_8723D 0x0040
|
||||
#define REG_GPIO_IO_SEL_8723D 0x0042
|
||||
#define REG_MAC_PINMUX_CFG_8723D 0x0043 // ??????
|
||||
#define REG_GPIO_PIN_CTRL_8723D 0x0044
|
||||
#define REG_GPIO_INTM_8723D 0x0048
|
||||
#define BIT_REG_LED_CFG_8723D 0x004C
|
||||
#define REG_LEDCFG2_8723D 0x004E // ??????
|
||||
#define REG_FSIMR_8723D 0x0050
|
||||
#define REG_FSISR_8723D 0x0054
|
||||
#define REG_HSIMR_8723D 0x0058
|
||||
#define REG_HSISR_8723D 0x005c
|
||||
#define REG_GPIO_EXT_CTRL_8723D 0x0060
|
||||
#define REG_MULTI_FUNC_CTRL_8723D 0x0068
|
||||
#define REG_GPIO_STATUS_8723D 0x006C
|
||||
#define REG_SDIO_CTRL_8723D 0x0070
|
||||
#define REG_HCI_OPT_CTRL_8723D 0x0074
|
||||
#define REG_AFE_CTRL4_8723D 0x0078
|
||||
#define REG_LDO_SWR_CTRL_8723D 0x007C
|
||||
#define REG_8051FW_CTRL_8723D 0x0080
|
||||
#define REG_FW_DBG_STATUS_8723D 0x0088
|
||||
#define REG_FW_DBG_CTRL_8723D 0x008F
|
||||
#define REG_WLLPS_CTRL_8723D 0x0090
|
||||
#define REG_HIMR0_8723D 0x00B0
|
||||
#define REG_HISR0_8723D 0x00B4
|
||||
#define REG_HIMR1_8723D 0x00B8
|
||||
#define REG_HISR1_8723D 0x00BC
|
||||
#define REG_PMC_DBG_CTRL2_8723D 0x00CC
|
||||
#define REG_EFUSE_BURN_GNT_8723D 0x00CF
|
||||
#define REG_XTAL_AAC_8723D 0x00EC
|
||||
#define REG_SYS_CFG1_8723D 0x00F0
|
||||
#define REG_SYS_CFG2_8723D 0x00FC
|
||||
#define REG_ROM_VERSION 0x00FD
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_CR_8723D 0x0100
|
||||
#define REG_PBP_8723D 0x0104 // ??????
|
||||
#define REG_PKT_BUFF_ACCESS_CTRL_8723D 0x0106 // ??????
|
||||
#define REG_TRXDMA_CTRL_8723D 0x010C
|
||||
#define REG_TRXFF_BNDY_8723D 0x0114
|
||||
#define REG_RXFF_PTR_8723D 0x011C
|
||||
#define REG_CPWM_8723D 0x012C
|
||||
#define REG_FWIMR_8723D 0x0130
|
||||
#define REG_FWISR_8723D 0x0134
|
||||
#define REG_FTIMR_8723D 0x0138
|
||||
#define REG_PKTBUF_DBG_CTRL_8723D 0x0140
|
||||
#define REG_RXPKTBUF_CTRL_8723D 0x0142 // ??????
|
||||
#define REG_PKTBUF_DBG_DATA_L_8723D 0x0144
|
||||
#define REG_PKTBUF_DBG_DATA_H_8723D 0x0148
|
||||
|
||||
#define REG_TC0_CTRL_8723D 0x0150
|
||||
#define REG_TC1_CTRL_8723D 0x0154
|
||||
#define REG_TC2_CTRL_8723D 0x0158
|
||||
#define REG_TC3_CTRL_8723D 0x015C
|
||||
#define REG_TC4_CTRL_8723D 0x0160
|
||||
#define REG_TCUNIT_BASE_8723D 0x0164
|
||||
#define REG_RSVD3_8723D 0x0168 // ?????
|
||||
|
||||
#define REG_C2HEVT_MSG_NORMAL_8723D 0x01A0 // ??????
|
||||
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 // ??????
|
||||
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 // ??????
|
||||
#define REG_C2HEVT_CMD_LEN_88XX 0x01AE // ??????
|
||||
#define REG_C2HEVT_CLEAR_8723D 0x01AF // ??????
|
||||
#define REG_MCUTST_1_8723D 0x01C0
|
||||
#define REG_MCUTST_2_8723D 0x01C4
|
||||
#define REG_MCUTST_WOWLAN_8723D 0x01C7 // ??????
|
||||
#define REG_FMETHR_8723D 0x01C8
|
||||
#define REG_HMETFR_8723D 0x01CC
|
||||
#define REG_HMEBOX_0_8723D 0x01D0
|
||||
#define REG_HMEBOX_1_8723D 0x01D4
|
||||
#define REG_HMEBOX_2_8723D 0x01D8
|
||||
#define REG_HMEBOX_3_8723D 0x01DC
|
||||
#define REG_LLT_INIT_8723D 0x01E0
|
||||
#define REG_HMEBOX_EXT0_8723D 0x01F0 // ??????
|
||||
#define REG_HMEBOX_EXT1_8723D 0x01F4 // ??????
|
||||
#define REG_HMEBOX_EXT2_8723D 0x01F8 // ??????
|
||||
#define REG_HMEBOX_EXT3_8723D 0x01FC // ??????
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_RQPN_8723D 0x0200
|
||||
#define REG_FIFOPAGE_8723D 0x0204
|
||||
#define REG_TDECTRL_8723D 0x0208
|
||||
#define REG_TXDMA_OFFSET_CHK_8723D 0x020C
|
||||
#define REG_TXDMA_STATUS_8723D 0x0210
|
||||
#define REG_RQPN_NPQ_8723D 0x0214
|
||||
#define REG_AUTO_LLT_8723D 0x0224
|
||||
#define REG_DWBCN1_CTRL_8723D 0x0228
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_RXDMA_AGG_PG_TH_8723D 0x0280
|
||||
#define REG_RXPKT_NUM_8723D 0x0284 // The number of packets in RXPKTBUF.
|
||||
#define REG_RXDMA_CONTROL_8723D 0x0286 // ?????? Control the RX DMA.
|
||||
#define REG_RXDMA_STATUS_8723D 0x0288
|
||||
#define REG_RXDMA_PRO_8723D 0x0290 // ??????
|
||||
#define REG_EARLY_MODE_CONTROL_8723D 0x02BC // ??????
|
||||
#define REG_RSVD5_8723D 0x02F0 // ??????
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0300h ~ 0x03FFh PCIe
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_PCIE_CTRL_REG_8723D 0x0300
|
||||
#define REG_INT_MIG_8723D 0x0304 // Interrupt Migration
|
||||
#define REG_BCNQ_TXBD_DESA_8723D 0x0308 // TX Beacon Descriptor Address
|
||||
#define REG_MGQ_TXBD_DESA_8723D 0x0310 // TX Manage Queue Descriptor Address
|
||||
#define REG_VOQ_TXBD_DESA_8723D 0x0318 // TX VO Queue Descriptor Address
|
||||
#define REG_VIQ_TXBD_DESA_8723D 0x0320 // TX VI Queue Descriptor Address
|
||||
#define REG_BEQ_TXBD_DESA_8723D 0x0328 // TX BE Queue Descriptor Address
|
||||
#define REG_BKQ_TXBD_DESA_8723D 0x0330 // TX BK Queue Descriptor Address
|
||||
#define REG_RXQ_RXBD_DESA_8723D 0x0338 // RX Queue Descriptor Address
|
||||
#define REG_HI0Q_TXBD_DESA_8723D 0x0340
|
||||
#define REG_HI1Q_TXBD_DESA_8723D 0x0348
|
||||
#define REG_HI2Q_TXBD_DESA_8723D 0x0350
|
||||
#define REG_HI3Q_TXBD_DESA_8723D 0x0358
|
||||
#define REG_HI4Q_TXBD_DESA_8723D 0x0360
|
||||
#define REG_HI5Q_TXBD_DESA_8723D 0x0368
|
||||
#define REG_HI6Q_TXBD_DESA_8723D 0x0370
|
||||
#define REG_HI7Q_TXBD_DESA_8723D 0x0378
|
||||
#define REG_MGQ_TXBD_NUM_8723D 0x0380
|
||||
#define REG_RX_RXBD_NUM_8723D 0x0382
|
||||
#define REG_VOQ_TXBD_NUM_8723D 0x0384
|
||||
#define REG_VIQ_TXBD_NUM_8723D 0x0386
|
||||
#define REG_BEQ_TXBD_NUM_8723D 0x0388
|
||||
#define REG_BKQ_TXBD_NUM_8723D 0x038A
|
||||
#define REG_HI0Q_TXBD_NUM_8723D 0x038C
|
||||
#define REG_HI1Q_TXBD_NUM_8723D 0x038E
|
||||
#define REG_HI2Q_TXBD_NUM_8723D 0x0390
|
||||
#define REG_HI3Q_TXBD_NUM_8723D 0x0392
|
||||
#define REG_HI4Q_TXBD_NUM_8723D 0x0394
|
||||
#define REG_HI5Q_TXBD_NUM_8723D 0x0396
|
||||
#define REG_HI6Q_TXBD_NUM_8723D 0x0398
|
||||
#define REG_HI7Q_TXBD_NUM_8723D 0x039A
|
||||
#define REG_TSFTIMER_HCI_8723D 0x039C
|
||||
|
||||
//Read Write Point
|
||||
#define REG_VOQ_TXBD_IDX_8723D 0x03A0
|
||||
#define REG_VIQ_TXBD_IDX_8723D 0x03A4
|
||||
#define REG_BEQ_TXBD_IDX_8723D 0x03A8
|
||||
#define REG_BKQ_TXBD_IDX_8723D 0x03AC
|
||||
#define REG_MGQ_TXBD_IDX_8723D 0x03B0
|
||||
#define REG_RXQ_TXBD_IDX_8723D 0x03B4
|
||||
#define REG_HI0Q_TXBD_IDX_8723D 0x03B8
|
||||
#define REG_HI1Q_TXBD_IDX_8723D 0x03BC
|
||||
#define REG_HI2Q_TXBD_IDX_8723D 0x03C0
|
||||
#define REG_HI3Q_TXBD_IDX_8723D 0x03C4
|
||||
#define REG_HI4Q_TXBD_IDX_8723D 0x03C8
|
||||
#define REG_HI5Q_TXBD_IDX_8723D 0x03CC
|
||||
#define REG_HI6Q_TXBD_IDX_8723D 0x03D0
|
||||
#define REG_HI7Q_TXBD_IDX_8723D 0x03D4
|
||||
|
||||
#define REG_PCIE_HCPWM_8723DE 0x03D8 // ??????
|
||||
#define REG_PCIE_HRPWM_8723DE 0x03DC //PCIe RPWM // ??????
|
||||
#define REG_DBI_WDATA_V1_8723D 0x03E8
|
||||
#define REG_DBI_RDATA_V1_8723D 0x03EC
|
||||
#define REG_DBI_FLAG_V1_8723D 0x03F0
|
||||
#define REG_MDIO_V1_8723D 0x03F4
|
||||
#define REG_PCIE_MIX_CFG_8723D 0x03F8
|
||||
#define REG_HCI_MIX_CFG_8723D 0x03FC
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_TXPKT_EMPTY_8723D 0x041A
|
||||
#define REG_PTCL_POLL_MGN_8723D 0x041F
|
||||
#define REG_FWHW_TXQ_CTRL_8723D 0x0420
|
||||
#define REG_HWSEQ_CTRL_8723D 0x0423
|
||||
#define REG_BCNQ_BDNY_8723D 0x0424
|
||||
#define REG_MGQ_BDNY_8723D 0x0425
|
||||
#define REG_LIFETIME_EN_8723D 0x0426
|
||||
#define REG_FW_FREE_TAIL_8723D 0x0427
|
||||
#define REG_SPEC_SIFS_8723D 0x0428
|
||||
#define REG_RETRY_LIMIT_8723D 0x042A
|
||||
#define REG_TXBF_CTRL_8723D 0x042C
|
||||
#define REG_DARFRC_8723D 0x0430
|
||||
#define REG_RARFRC_8723D 0x0438
|
||||
#define REG_RRSR_8723D 0x0440
|
||||
#define REG_ARFR0_8723D 0x0444
|
||||
#define REG_ARFR1_8723D 0x044C
|
||||
#define REG_CCK_CHECK_8723D 0x0454
|
||||
#define REG_BCNQ2_BDNY_8723D 0x0455
|
||||
#define REG_AMPDU_MAX_TIME_8723D 0x0456
|
||||
#define REG_BCNQ1_BDNY_8723D 0x0457
|
||||
#define REG_AMPDU_MAX_LENGTH_8723D 0x0458
|
||||
#define REG_WMAC_LBK_BUF_HD_8723D 0x045D
|
||||
#define REG_NDPA_OPT_CTRL_8723D 0x045F
|
||||
#define REG_FAST_EDCA_CTRL_8723D 0x0460
|
||||
#define REG_RD_RESP_PKT_TH_8723D 0x0463
|
||||
#define REG_DATA_SC_8723D 0x0483
|
||||
#define REG_TXRPT_START_OFFSET 0x04AC
|
||||
#define REG_POWER_STAGE1_8723D 0x04B4
|
||||
#define REG_PTCL_SDF_STATUS_8723D 0x04BB
|
||||
#define REG_SW_AMPDU_BURST_MODE_CTRL_8723D 0x04BC
|
||||
#define REG_EVTQ_BNDY_8723D 0x04BF
|
||||
#define REG_PKT_LIFE_TIME_8723D 0x04C0
|
||||
#define REG_PKT_BE_BK_LIFE_TIME_8723D 0x04C2 // ??????
|
||||
|
||||
#define REG_STBC_SETTING_8723D 0x04C4
|
||||
#define REG_HT_SINGLE_AMPDU_8723D 0x04C7
|
||||
#define REG_PROT_MODE_CTRL_8723D 0x04C8
|
||||
#define REG_MAX_AGGR_NUM_8723D 0x04CA
|
||||
#define REG_RTS_MAX_AGGR_NUM_8723D 0x04CB
|
||||
#define REG_BAR_MODE_CTRL_8723D 0x04CC
|
||||
#define REG_RA_TRY_RATE_AGG_LMT_8723D 0x04CF
|
||||
#define REG_MACID_SLEEP2_8723D 0x04D0
|
||||
#define REG_PTCL_HWSSN0_8723D 0x04D8
|
||||
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D 0x045D // ??????
|
||||
|
||||
|
||||
/************* 0x1480~0x14A7 is for NAN ***************/
|
||||
//Own Master Rank, 8Bytes
|
||||
#define REG_NAN_INTERFACE_ADDR_8723D 0x2480 // 6 bytes
|
||||
#define REG_NAN_RANDOM_FACTOR_8723D 0x2486 // 1 byte
|
||||
#define REG_NAN_MASTER_PREF_8723D 0x2487 // 1 byte
|
||||
|
||||
//0x5dc[25:24] NAN role
|
||||
|
||||
//Current Anchor Master Record
|
||||
#define REG_NAN_CAMR_L_8723D 0x2488 // 4 bytes
|
||||
#define REG_NAN_CAMR_H_8723D 0x248C // 4 byte
|
||||
//#define REG_HOP_CNT_8723D 0x05DC
|
||||
#define REG_NAN_CAMR_AMBTT_8723D 0x2490 // 4 bytes
|
||||
|
||||
//Last Anchor Master Record
|
||||
#define REG_NAN_LAMR_L_8723D 0x2494 // 4 bytes
|
||||
#define REG_NAN_LAMR_H_8723D 0x2498 // 4 byte
|
||||
#define REG_NAN_LAMR_AMBTT_8723D 0x249C // 4 bytes
|
||||
|
||||
//TSF Synced:bit 0
|
||||
//Anchor Master: bit 7
|
||||
#define REG_NAN_STATUS_8723D 0x24A0 //BIT0
|
||||
/***************************************************/
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
// gogogo
|
||||
#define REG_EDCA_VO_PARAM_8723D 0x0500
|
||||
#define REG_EDCA_VI_PARAM_8723D 0x0504
|
||||
#define REG_EDCA_BE_PARAM_8723D 0x0508
|
||||
#define REG_EDCA_BK_PARAM_8723D 0x050C
|
||||
#define REG_BCNTCFG_8723D 0x0510
|
||||
#define REG_PIFS_8723D 0x0512
|
||||
#define REG_RDG_PIFS_8723D 0x0513
|
||||
#define REG_SIFS_CTX_8723D 0x0514
|
||||
#define REG_SIFS_TRX_8723D 0x0516
|
||||
#define REG_AGGR_BREAK_TIME_8723D 0x051A
|
||||
#define REG_SLOT_8723D 0x051B
|
||||
#define REG_TX_PTCL_CTRL_8723D 0x0520
|
||||
#define REG_TXPAUSE_8723D 0x0522
|
||||
#define REG_DIS_TXREQ_CLR_8723D 0x0523
|
||||
#define REG_RD_CTRL_8723D 0x0524
|
||||
//
|
||||
// Format for offset 540h-542h:
|
||||
// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
|
||||
// [7:4]: Reserved.
|
||||
// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
|
||||
// [23:20]: Reserved
|
||||
// Description:
|
||||
// |
|
||||
// |<--Setup--|--Hold------------>|
|
||||
// --------------|----------------------
|
||||
// |
|
||||
// TBTT
|
||||
// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
|
||||
// Described by Designer Tim and Bruce, 2011-01-14.
|
||||
//
|
||||
#define REG_TBTT_PROHIBIT_8723D 0x0540
|
||||
#define REG_RD_NAV_NXT_8723D 0x0544
|
||||
#define REG_NAV_PROT_LEN_8723D 0x0546
|
||||
#define REG_BCN_CTRL_8723D 0x0550
|
||||
#define REG_EDCA_BCNCTRL1_IOREG_8723D 0x0551
|
||||
#define REG_MBID_NUM_8723D 0x0552
|
||||
#define REG_DUAL_TSF_RST_8723D 0x0553
|
||||
#define REG_BCN_INTERVAL_8723D 0x0554
|
||||
#define REG_DRVERLYINT_8723D 0x0558
|
||||
#define REG_BCNDMATIM_8723D 0x0559
|
||||
#define REG_ATIMWND_8723D 0x055A
|
||||
#define REG_USTIME_TSF_8723D 0x055C
|
||||
#define REG_BCN_MAX_ERR_8723D 0x055D
|
||||
#define REG_RXTSF_OFFSET_CCK_8723D 0x055E
|
||||
#define REG_RXTSF_OFFSET_OFDM_8723D 0x055F
|
||||
#define REG_TSFTR_8723D 0x0560
|
||||
#define REG_CTWND_8723D 0x0572
|
||||
#define REG_SECONDARY_CCA_CTRL_8723D 0x0577 // ??????
|
||||
#define REG_TSFTR2_8723D 0x0578
|
||||
#define REG_PSTIMER_8723D 0x0580
|
||||
#define REG_TIMER0_8723D 0x0584
|
||||
#define REG_TIMER1_8723D 0x0588
|
||||
#define REG_SCH_MULTI_BCN_8723D 0x05B2
|
||||
#define REG_SCH_CURRENT_BCN_8723D 0x05B3
|
||||
#define REG_ACMHWCTRL_8723D 0x05C0
|
||||
#define REG_SCH_SDFX_EARLY_8723D 0x05CF
|
||||
#define REG_SCH_PORT2_EARLY_8723D 0x05D0
|
||||
#define REG_SCH_TSFT_DIFF_8723D 0x05D2
|
||||
#define REG_EDCA_BCNCTRL2_IOREG_8723D 0x05D4
|
||||
#define REG_EDCA_DRVERLYINT1_IOREG_8723D 0x05D4
|
||||
#define REG_EDCA_BCNSPACE3_IOREG_8723D 0x05D8
|
||||
#define REG_EDCA_BCNSPACE4_IOREG_8723D 0x05DA
|
||||
#define REG_HOP_CNT_8723D 0x05DC
|
||||
#define REG_SCH_M_DW_8723D 0x05DD
|
||||
#define REG_SCH_M_SLOT_8723D 0x05DE
|
||||
#define REG_SCH_EARLY_DWEND_8723D 0x05DF
|
||||
#define REG_SCH_TXCMD_8723D 0x05F8
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
// gogogo
|
||||
#define REG_MAC_CR_8723D 0x0600
|
||||
#define REG_TCR_8723D 0x0604
|
||||
#define REG_RCR_8723D 0x0608
|
||||
#define REG_RX_PKT_LIMIT_8723D 0x060C
|
||||
#define REG_RX_DLK_TIME_8723D 0x060D
|
||||
#define REG_RX_DRVINFO_SZ_8723D 0x060F
|
||||
|
||||
#define REG_MACID_8723D 0x0610
|
||||
#define REG_BSSID_8723D 0x0618
|
||||
#define REG_MAR_8723D 0x0620
|
||||
#define REG_MBIDCAMCFG_8723D 0x0628
|
||||
|
||||
#define REG_USTIME_EDCA_8723D 0x0638
|
||||
#define REG_MAC_SPEC_SIFS_8723D 0x063A
|
||||
#define REG_RESP_SIFP_CCK_8723D 0x063C
|
||||
#define REG_RESP_SIFS_OFDM_8723D 0x063E
|
||||
#define REG_ACKTO_8723D 0x0640
|
||||
#define REG_CTS2TO_8723D 0x0641
|
||||
#define REG_EIFS_8723D 0x0642
|
||||
|
||||
#define REG_NAV_UPPER_8723D 0x0652 // ??????
|
||||
#define REG_TRXPTCL_CTL_8723D 0x0668
|
||||
|
||||
// Security
|
||||
#define REG_CAMCMD_8723D 0x0670
|
||||
#define REG_CAMWRITE_8723D 0x0674
|
||||
#define REG_CAMREAD_8723D 0x0678
|
||||
#define REG_CAMDBG_8723D 0x067C
|
||||
#define REG_SECCFG_8723D 0x0680
|
||||
|
||||
// Power
|
||||
#define REG_WOW_CTRL_8723D 0x0690
|
||||
#define REG_PS_RX_INFO_8723D 0x0692
|
||||
#define REG_UAPSD_TID_8723D 0x0693
|
||||
#define REG_WKFMCAM_NUM_8723D 0x0698
|
||||
#define REG_RXFLTMAP0_8723D 0x06A0
|
||||
#define REG_RXFLTMAP1_8723D 0x06A2
|
||||
#define REG_RXFLTMAP2_8723D 0x06A4
|
||||
#define REG_BCN_PSR_RPT_8723D 0x06A8
|
||||
#define REG_BT_COEX_TABLE_8723D 0x06C0
|
||||
#define REG_ASSOCIATED_BFMER0_INFO_8723D 0x06E4
|
||||
#define REG_ASSOCIATED_BFMER1_INFO_8723D 0x06EC
|
||||
#define REG_CSI_RPT_PARAM_BW20_8723D 0x06F4
|
||||
#define REG_CSI_RPT_PARAM_BW40_8723D 0x06F8
|
||||
#define REG_CSI_RPT_PARAM_BW80_8723D 0x06FC
|
||||
|
||||
// Hardware Port 2
|
||||
#define REG_MACID1_8723D 0x0700
|
||||
#define REG_BSSID1_8723D 0x0708
|
||||
#define REG_ASSOCIATED_BFMEE_SEL_8723D 0x0714
|
||||
#define REG_SND_PTCL_CTRL_8723D 0x0718
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// Redifine 8192C register definition for compatibility
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
// TODO: use these definition when using REG_xxx naming rule.
|
||||
// NOTE: DO NOT Remove these definition. Use later.
|
||||
#define EFUSE_CTRL_8723D REG_EFUSE_CTRL_8723D // E-Fuse Control.
|
||||
#define EFUSE_TEST_8723D REG_LDO_EFUSE_CTRL_8723D // E-Fuse Test.
|
||||
#define MSR_8723D (REG_CR_8723D + 2) // Media Status register
|
||||
#define ISR_8723D REG_HISR0_8723D
|
||||
#define TSFR_8723D REG_TSFTR_8723D // Timing Sync Function Timer Register.
|
||||
|
||||
// Redifine MACID register, to compatible prior ICs.
|
||||
#define IDR0_8723D REG_MACID_8723D // MAC ID Register, Offset 0x0050-0x0053
|
||||
#define IDR4_8723D (REG_MACID_8723D + 4) // MAC ID Register, Offset 0x0054-0x0055
|
||||
|
||||
|
||||
//
|
||||
// 9. Security Control Registers (Offset: )
|
||||
//
|
||||
#define RWCAM_8723D REG_CAMCMD_8723D //IN 8190 Data Sheet is called CAMcmd
|
||||
#define WCAMI_8723D REG_CAMWRITE_8723D // Software write CAM input content
|
||||
#define RCAMO_8723D REG_CAMREAD_8723D // Software read/write CAM config
|
||||
#define CAMDBG_8723D REG_CAMDBG_8723D
|
||||
#define SECR_8723D REG_SECCFG_8723D //Security Configuration Register
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// 8195 IMR/ISR bits (offset 0xB0, 8bits)
|
||||
//----------------------------------------------------------------------------
|
||||
#define IMR_DISABLED_8723D 0
|
||||
// IMR DW0(0x00B0-00B3) Bit 0-31
|
||||
#define IMR_TIMER2_8723D BIT31 // Timeout interrupt 2
|
||||
#define IMR_TIMER1_8723D BIT30 // Timeout interrupt 1
|
||||
#define IMR_PSTIMEOUT_8723D BIT29 // Power Save Time Out Interrupt
|
||||
#define IMR_GTINT4_8723D BIT28 // When GTIMER4 expires, this bit is set to 1
|
||||
#define IMR_GTINT3_8723D BIT27 // When GTIMER3 expires, this bit is set to 1
|
||||
#define IMR_TXBCN0ERR_8723D BIT26 // Transmit Beacon0 Error
|
||||
#define IMR_TXBCN0OK_8723D BIT25 // Transmit Beacon0 OK
|
||||
#define IMR_TSF_BIT32_TOGGLE_8723D BIT24 // TSF Timer BIT32 toggle indication interrupt
|
||||
#define IMR_BCNDMAINT0_8723D BIT20 // Beacon DMA Interrupt 0
|
||||
#define IMR_BCNDERR0_8723D BIT16 // Beacon Queue DMA OK0
|
||||
#define IMR_HSISR_IND_ON_INT_8723D BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
|
||||
#define IMR_BCNDMAINT_E_8723D BIT14 // Beacon DMA Interrupt Extension for Win7
|
||||
#define IMR_ATIMEND_8723D BIT12 // CTWidnow End or ATIM Window End
|
||||
#define IMR_C2HCMD_8723D BIT10 // CPU to Host Command INT Status, Write 1 clear
|
||||
#define IMR_CPWM2_8723D BIT9 // CPU power Mode exchange INT Status, Write 1 clear
|
||||
#define IMR_CPWM_8723D BIT8 // CPU power Mode exchange INT Status, Write 1 clear
|
||||
#define IMR_HIGHDOK_8723D BIT7 // High Queue DMA OK
|
||||
#define IMR_MGNTDOK_8723D BIT6 // Management Queue DMA OK
|
||||
#define IMR_BKDOK_8723D BIT5 // AC_BK DMA OK
|
||||
#define IMR_BEDOK_8723D BIT4 // AC_BE DMA OK
|
||||
#define IMR_VIDOK_8723D BIT3 // AC_VI DMA OK
|
||||
#define IMR_VODOK_8723D BIT2 // AC_VO DMA OK
|
||||
#define IMR_RDU_8723D BIT1 // Rx Descriptor Unavailable
|
||||
#define IMR_ROK_8723D BIT0 // Receive DMA OK
|
||||
|
||||
// IMR DW1(0x00B4-00B7) Bit 0-31
|
||||
#define IMR_BCNDMAINT7_8723D BIT27 // Beacon DMA Interrupt 7
|
||||
#define IMR_BCNDMAINT6_8723D BIT26 // Beacon DMA Interrupt 6
|
||||
#define IMR_BCNDMAINT5_8723D BIT25 // Beacon DMA Interrupt 5
|
||||
#define IMR_BCNDMAINT4_8723D BIT24 // Beacon DMA Interrupt 4
|
||||
#define IMR_BCNDMAINT3_8723D BIT23 // Beacon DMA Interrupt 3
|
||||
#define IMR_BCNDMAINT2_8723D BIT22 // Beacon DMA Interrupt 2
|
||||
#define IMR_BCNDMAINT1_8723D BIT21 // Beacon DMA Interrupt 1
|
||||
#define IMR_BCNDOK7_8723D BIT20 // Beacon Queue DMA OK Interrup 7
|
||||
#define IMR_BCNDOK6_8723D BIT19 // Beacon Queue DMA OK Interrup 6
|
||||
#define IMR_BCNDOK5_8723D BIT18 // Beacon Queue DMA OK Interrup 5
|
||||
#define IMR_BCNDOK4_8723D BIT17 // Beacon Queue DMA OK Interrup 4
|
||||
#define IMR_BCNDOK3_8723D BIT16 // Beacon Queue DMA OK Interrup 3
|
||||
#define IMR_BCNDOK2_8723D BIT15 // Beacon Queue DMA OK Interrup 2
|
||||
#define IMR_BCNDOK1_8723D BIT14 // Beacon Queue DMA OK Interrup 1
|
||||
#define IMR_ATIMEND_E_8723D BIT13 // ATIM Window End Extension for Win7
|
||||
#define IMR_TXERR_8723D BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
|
||||
#define IMR_RXERR_8723D BIT10 // Rx Error Flag INT Status, Write 1 clear
|
||||
#define IMR_TXFOVW_8723D BIT9 // Transmit FIFO Overflow
|
||||
#define IMR_RXFOVW_8723D BIT8 // Receive FIFO Overflow
|
||||
|
||||
|
||||
|
||||
#define IMR_MCUERR_8723D BIT28 // Beacon DMA Interrupt 7
|
||||
|
||||
|
||||
/*===================================================================
|
||||
=====================================================================
|
||||
Here the register defines are for 92C. When the define is as same with 92C,
|
||||
we will use the 92C's define for the consistency
|
||||
So the following defines for 92C is not entire!!!!!!
|
||||
=====================================================================
|
||||
=====================================================================*/
|
||||
/*
|
||||
Based on Datasheet V33---090401
|
||||
Register Summary
|
||||
Current IOREG MAP
|
||||
0x0000h ~ 0x00FFh System Configuration (256 Bytes)
|
||||
0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
|
||||
0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
|
||||
0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
|
||||
0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
|
||||
0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
|
||||
0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
|
||||
0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
|
||||
0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
|
||||
*/
|
||||
//----------------------------------------------------------------------------
|
||||
// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits)
|
||||
//----------------------------------------------------------------------------
|
||||
/*
|
||||
#define StopBecon BIT6
|
||||
#define StopHigh BIT5
|
||||
#define StopMgt BIT4
|
||||
#define StopVO BIT3
|
||||
#define StopVI BIT2
|
||||
#define StopBE BIT1
|
||||
#define StopBK BIT0
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//============================================================================
|
||||
// 8192C Regsiter Bit and Content definition
|
||||
//============================================================================
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0000h ~ 0x00FFh System Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
/*
|
||||
//2 SYS_ISO_CTRL
|
||||
#define ISO_MD2PP BIT(0)
|
||||
#define ISO_UA2USB BIT(1)
|
||||
#define ISO_UD2CORE BIT(2)
|
||||
#define ISO_PA2PCIE BIT(3)
|
||||
#define ISO_PD2CORE BIT(4)
|
||||
#define ISO_IP2MAC BIT(5)
|
||||
#define ISO_DIOP BIT(6)
|
||||
#define ISO_DIOE BIT(7)
|
||||
#define ISO_EB2CORE BIT(8)
|
||||
#define ISO_DIOR BIT(9)
|
||||
#define PWC_EV12V BIT(15)
|
||||
|
||||
|
||||
//2 SYS_FUNC_EN
|
||||
#define FEN_BBRSTB BIT(0)
|
||||
#define FEN_BB_GLB_RSTn BIT(1)
|
||||
#define FEN_USBA BIT(2)
|
||||
#define FEN_UPLL BIT(3)
|
||||
#define FEN_USBD BIT(4)
|
||||
#define FEN_DIO_PCIE BIT(5)
|
||||
#define FEN_PCIEA BIT(6)
|
||||
#define FEN_PPLL BIT(7)
|
||||
#define FEN_PCIED BIT(8)
|
||||
#define FEN_DIOE BIT(9)
|
||||
#define FEN_CPUEN BIT(10)
|
||||
#define FEN_DCORE BIT(11)
|
||||
#define FEN_ELDR BIT(12)
|
||||
#define FEN_DIO_RF BIT(13)
|
||||
#define FEN_HWPDN BIT(14)
|
||||
#define FEN_MREGEN BIT(15)
|
||||
|
||||
//2 APS_FSMCO
|
||||
#define PFM_LDALL BIT(0)
|
||||
#define PFM_ALDN BIT(1)
|
||||
#define PFM_LDKP BIT(2)
|
||||
#define PFM_WOWL BIT(3)
|
||||
#define EnPDN BIT(4)
|
||||
#define PDN_PL BIT(5)
|
||||
#define APFM_ONMAC BIT(8)
|
||||
#define APFM_OFF BIT(9)
|
||||
#define APFM_RSM BIT(10)
|
||||
#define AFSM_HSUS BIT(11)
|
||||
#define AFSM_PCIE BIT(12)
|
||||
#define APDM_MAC BIT(13)
|
||||
#define APDM_HOST BIT(14)
|
||||
#define APDM_HPDN BIT(15)
|
||||
#define RDY_MACON BIT(16)
|
||||
#define SUS_HOST BIT(17)
|
||||
#define ROP_ALD BIT(20)
|
||||
#define ROP_PWR BIT(21)
|
||||
#define ROP_SPS BIT(22)
|
||||
#define SOP_MRST BIT(25)
|
||||
#define SOP_FUSE BIT(26)
|
||||
#define SOP_ABG BIT(27)
|
||||
#define SOP_AMB BIT(28)
|
||||
#define SOP_RCK BIT(29)
|
||||
#define SOP_A8M BIT(30)
|
||||
#define XOP_BTCK BIT(31)
|
||||
|
||||
//2 SYS_CLKR
|
||||
#define ANAD16V_EN BIT(0)
|
||||
#define ANA8M BIT(1)
|
||||
#define MACSLP BIT(4)
|
||||
#define LOADER_CLK_EN BIT(5)
|
||||
|
||||
|
||||
//2 9346CR
|
||||
|
||||
#define BOOT_FROM_EEPROM BIT(4)
|
||||
#define EEPROM_EN BIT(5)
|
||||
|
||||
|
||||
//2 RF_CTRL
|
||||
#define RF_EN BIT(0)
|
||||
#define RF_RSTB BIT(1)
|
||||
#define RF_SDMRSTB BIT(2)
|
||||
|
||||
//2 LDOV12D_CTRL
|
||||
#define LDV12_EN BIT(0)
|
||||
#define LDV12_SDBY BIT(1)
|
||||
#define LPLDO_HSM BIT(2)
|
||||
#define LPLDO_LSM_DIS BIT(3)
|
||||
#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
|
||||
|
||||
|
||||
//2 EFUSE_TEST (For RTL8723 partially)
|
||||
#define EF_TRPT BIT(7)
|
||||
#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2
|
||||
#define LDOE25_EN BIT(31)
|
||||
#define EFUSE_SEL(x) (((x) & 0x3) << 8)
|
||||
#define EFUSE_SEL_MASK 0x300
|
||||
#define EFUSE_WIFI_SEL_0 0x0
|
||||
#define EFUSE_BT_SEL_0 0x1
|
||||
#define EFUSE_BT_SEL_1 0x2
|
||||
#define EFUSE_BT_SEL_2 0x3
|
||||
|
||||
|
||||
//2 8051FWDL
|
||||
//2 MCUFWDL
|
||||
#define MCUFWDL_EN BIT(0)
|
||||
#define MCUFWDL_RDY BIT(1)
|
||||
#define FWDL_ChkSum_rpt BIT(2)
|
||||
#define MACINI_RDY BIT(3)
|
||||
#define BBINI_RDY BIT(4)
|
||||
#define RFINI_RDY BIT(5)
|
||||
#define WINTINI_RDY BIT(6)
|
||||
#define RAM_DL_SEL BIT(7)
|
||||
#define ROM_DLEN BIT(19)
|
||||
#define CPRST BIT(23)
|
||||
|
||||
|
||||
|
||||
//2 REG_SYS_CFG
|
||||
#define XCLK_VLD BIT(0)
|
||||
#define ACLK_VLD BIT(1)
|
||||
#define UCLK_VLD BIT(2)
|
||||
#define PCLK_VLD BIT(3)
|
||||
#define PCIRSTB BIT(4)
|
||||
#define V15_VLD BIT(5)
|
||||
#define TRP_B15V_EN BIT(7)
|
||||
#define SIC_IDLE BIT(8)
|
||||
#define BD_MAC2 BIT(9)
|
||||
#define BD_MAC1 BIT(10)
|
||||
#define IC_MACPHY_MODE BIT(11)
|
||||
#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15))
|
||||
#define BT_FUNC BIT(16)
|
||||
#define VENDOR_ID BIT(19)
|
||||
#define PAD_HWPD_IDN BIT(22)
|
||||
#define TRP_VAUX_EN BIT(23) // RTL ID
|
||||
#define TRP_BT_EN BIT(24)
|
||||
#define BD_PKG_SEL BIT(25)
|
||||
#define BD_HCI_SEL BIT(26)
|
||||
#define TYPE_ID BIT(27)
|
||||
|
||||
#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15
|
||||
#define CHIP_VER_RTL_SHIFT 12
|
||||
|
||||
*/
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
/*
|
||||
|
||||
//2 Function Enable Registers
|
||||
//2 CR 0x0100-0x0103
|
||||
|
||||
|
||||
#define HCI_TXDMA_EN BIT(0)
|
||||
#define HCI_RXDMA_EN BIT(1)
|
||||
#define TXDMA_EN BIT(2)
|
||||
#define RXDMA_EN BIT(3)
|
||||
#define PROTOCOL_EN BIT(4)
|
||||
#define SCHEDULE_EN BIT(5)
|
||||
#define MACTXEN BIT(6)
|
||||
#define MACRXEN BIT(7)
|
||||
#define ENSWBCN BIT(8)
|
||||
#define ENSEC BIT(9)
|
||||
#define CALTMR_EN BIT(10) // 32k CAL TMR enable
|
||||
|
||||
// Network type
|
||||
#define _NETTYPE(x) (((x) & 0x3) << 16)
|
||||
#define MASK_NETTYPE 0x30000
|
||||
#define NT_NO_LINK 0x0
|
||||
#define NT_LINK_AD_HOC 0x1
|
||||
#define NT_LINK_AP 0x2
|
||||
#define NT_AS_AP 0x3
|
||||
|
||||
|
||||
//2 PBP - Page Size Register 0x0104
|
||||
#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
|
||||
#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
|
||||
#define _PSRX_MASK 0xF
|
||||
#define _PSTX_MASK 0xF0
|
||||
#define _PSRX(x) (x)
|
||||
#define _PSTX(x) ((x) << 4)
|
||||
|
||||
#define PBP_64 0x0
|
||||
#define PBP_128 0x1
|
||||
#define PBP_256 0x2
|
||||
#define PBP_512 0x3
|
||||
#define PBP_1024 0x4
|
||||
|
||||
|
||||
//2 TX/RXDMA 0x010C
|
||||
#define RXDMA_ARBBW_EN BIT(0)
|
||||
#define RXSHFT_EN BIT(1)
|
||||
#define RXDMA_AGG_EN BIT(2)
|
||||
#define QS_VO_QUEUE BIT(8)
|
||||
#define QS_VI_QUEUE BIT(9)
|
||||
#define QS_BE_QUEUE BIT(10)
|
||||
#define QS_BK_QUEUE BIT(11)
|
||||
#define QS_MANAGER_QUEUE BIT(12)
|
||||
#define QS_HIGH_QUEUE BIT(13)
|
||||
|
||||
#define HQSEL_VOQ BIT(0)
|
||||
#define HQSEL_VIQ BIT(1)
|
||||
#define HQSEL_BEQ BIT(2)
|
||||
#define HQSEL_BKQ BIT(3)
|
||||
#define HQSEL_MGTQ BIT(4)
|
||||
#define HQSEL_HIQ BIT(5)
|
||||
|
||||
// For normal driver, 0x10C
|
||||
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
|
||||
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
|
||||
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
|
||||
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
|
||||
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
|
||||
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
|
||||
|
||||
#define QUEUE_LOW 1
|
||||
#define QUEUE_NORMAL 2
|
||||
#define QUEUE_HIGH 3
|
||||
|
||||
|
||||
//2 REG_C2HEVT_CLEAR 0x01AF
|
||||
#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message
|
||||
#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver.
|
||||
|
||||
|
||||
|
||||
//2 LLT_INIT 0x01E0
|
||||
#define _LLT_NO_ACTIVE 0x0
|
||||
#define _LLT_WRITE_ACCESS 0x1
|
||||
#define _LLT_READ_ACCESS 0x2
|
||||
|
||||
#define _LLT_INIT_DATA(x) ((x) & 0xFF)
|
||||
#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
|
||||
#define _LLT_OP(x) (((x) & 0x3) << 30)
|
||||
#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
|
||||
|
||||
*/
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
/*
|
||||
//2 TDECTL 0x0208
|
||||
#define BLK_DESC_NUM_SHIFT 4
|
||||
#define BLK_DESC_NUM_MASK 0xF
|
||||
|
||||
|
||||
//2 TXDMA_OFFSET_CHK 0x020C
|
||||
#define DROP_DATA_EN BIT(9)
|
||||
*/
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0280h ~ 0x028Bh RX DMA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
/*
|
||||
//2 REG_RXDMA_CONTROL, 0x0286h
|
||||
|
||||
// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before
|
||||
// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear.
|
||||
#define RXPKT_RELEASE_POLL BIT(0)
|
||||
// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in
|
||||
// this bit. FW can start releasing packets after RXDMA entering idle mode.
|
||||
#define RXDMA_IDLE BIT(1)
|
||||
// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host
|
||||
// completed, and stop DMA packet to host. RXDMA will then report Default: 0;
|
||||
#define RW_RELEASE_EN BIT(2)
|
||||
*/
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
/*
|
||||
//2 FWHW_TXQ_CTRL 0x0420
|
||||
#define EN_AMPDU_RTY_NEW BIT(7)
|
||||
|
||||
|
||||
//2 REG_LIFECTRL_CTRL 0x0426
|
||||
#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3
|
||||
#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2
|
||||
#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1
|
||||
#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0
|
||||
|
||||
#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim.
|
||||
|
||||
|
||||
//2 SPEC SIFS 0x0428
|
||||
#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
|
||||
#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
|
||||
|
||||
//2 RL 0x042A
|
||||
#define RETRY_LIMIT_SHORT_SHIFT 8
|
||||
#define RETRY_LIMIT_LONG_SHIFT 0
|
||||
|
||||
#define _LRL(x) ((x) & 0x3F)
|
||||
#define _SRL(x) (((x) & 0x3F) << 8)
|
||||
*/
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
/*
|
||||
//2 EDCA setting 0x050C
|
||||
#define AC_PARAM_TXOP_LIMIT_OFFSET 16
|
||||
#define AC_PARAM_ECW_MAX_OFFSET 12
|
||||
#define AC_PARAM_ECW_MIN_OFFSET 8
|
||||
#define AC_PARAM_AIFS_OFFSET 0
|
||||
|
||||
|
||||
//2 BCN_CTRL 0x0550
|
||||
#define EN_TXBCN_RPT BIT(2)
|
||||
#define EN_BCN_FUNCTION BIT(3)
|
||||
|
||||
//2 TxPause 0x0522
|
||||
#define STOP_BCNQ BIT(6)
|
||||
*/
|
||||
|
||||
|
||||
//2 ACMHWCTRL 0x05C0
|
||||
#define AcmHw_HwEn_8723D BIT(0)
|
||||
#define AcmHw_VoqEn_8723D BIT(1)
|
||||
#define AcmHw_ViqEn_8723D BIT(2)
|
||||
#define AcmHw_BeqEn_8723D BIT(3)
|
||||
#define AcmHw_VoqStatus_8723D BIT(5)
|
||||
#define AcmHw_ViqStatus_8723D BIT(6)
|
||||
#define AcmHw_BeqStatus_8723D BIT(7)
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
/*
|
||||
|
||||
//2 TCR 0x0604
|
||||
#define DIS_GCLK BIT(1)
|
||||
#define PAD_SEL BIT(2)
|
||||
#define PWR_ST BIT(6)
|
||||
#define PWRBIT_OW_EN BIT(7)
|
||||
#define ACRC BIT(8)
|
||||
#define CFENDFORM BIT(9)
|
||||
#define ICV BIT(10)
|
||||
*/
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits)
|
||||
//----------------------------------------------------------------------------
|
||||
/*
|
||||
#define RCR_APPFCS BIT31 // WMAC append FCS after pauload
|
||||
#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet.
|
||||
#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet.
|
||||
#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF
|
||||
#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC.
|
||||
#define RCR_RSVD_BIT26 BIT26 // Reserved
|
||||
*/
|
||||
#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload
|
||||
/*#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries.
|
||||
#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set.
|
||||
#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response.
|
||||
*/
|
||||
|
||||
|
||||
#endif // #ifndef __INC_HAL8723DREG_H
|
||||
@@ -0,0 +1,923 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.26*/
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
static BOOLEAN
|
||||
CheckPositive(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN const u4Byte Condition1,
|
||||
IN const u4Byte Condition2,
|
||||
IN const u4Byte Condition3,
|
||||
IN const u4Byte Condition4
|
||||
)
|
||||
{
|
||||
u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/
|
||||
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/
|
||||
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/
|
||||
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
|
||||
((pDM_Odm->BoardType & BIT2) >> 2) << 4 | /* _BT*/
|
||||
((pDM_Odm->BoardType & BIT1) >> 1) << 5; /* _NGFF*/
|
||||
|
||||
u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4;
|
||||
|
||||
u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion;
|
||||
u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType;
|
||||
|
||||
u4Byte driver1 = cut_version_for_para << 24 |
|
||||
(pDM_Odm->SupportInterface & 0xF0) << 16 |
|
||||
pDM_Odm->SupportPlatform << 16 |
|
||||
pkg_type_for_para << 12 |
|
||||
(pDM_Odm->SupportInterface & 0x0F) << 8 |
|
||||
_BoardType;
|
||||
|
||||
u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 |
|
||||
(pDM_Odm->TypeGPA & 0xFF) << 8 |
|
||||
(pDM_Odm->TypeALNA & 0xFF) << 16 |
|
||||
(pDM_Odm->TypeAPA & 0xFF) << 24;
|
||||
|
||||
u4Byte driver3 = 0;
|
||||
|
||||
u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 |
|
||||
(pDM_Odm->TypeGPA & 0xFF00) |
|
||||
(pDM_Odm->TypeALNA & 0xFF00) << 8 |
|
||||
(pDM_Odm->TypeAPA & 0xFF00) << 16;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
(" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
(" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType));
|
||||
|
||||
|
||||
/*============== Value Defined Check ===============*/
|
||||
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
|
||||
|
||||
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
|
||||
return FALSE;
|
||||
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
|
||||
return FALSE;
|
||||
|
||||
/*=============== Bit Defined Check ================*/
|
||||
/* We don't care [31:28] */
|
||||
|
||||
cond1 &= 0x00FF0FFF;
|
||||
driver1 &= 0x00FF0FFF;
|
||||
|
||||
if ((cond1 & driver1) == cond1) {
|
||||
u4Byte bitMask = 0;
|
||||
|
||||
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
|
||||
return TRUE;
|
||||
|
||||
if ((cond1 & BIT0) != 0) /*GLNA*/
|
||||
bitMask |= 0x000000FF;
|
||||
if ((cond1 & BIT1) != 0) /*GPA*/
|
||||
bitMask |= 0x0000FF00;
|
||||
if ((cond1 & BIT2) != 0) /*ALNA*/
|
||||
bitMask |= 0x00FF0000;
|
||||
if ((cond1 & BIT3) != 0) /*APA*/
|
||||
bitMask |= 0xFF000000;
|
||||
|
||||
if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
} else
|
||||
return FALSE;
|
||||
}
|
||||
static BOOLEAN
|
||||
CheckNegative(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN const u4Byte Condition1,
|
||||
IN const u4Byte Condition2
|
||||
)
|
||||
{
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* AGC_TAB.TXT
|
||||
******************************************************************************/
|
||||
|
||||
u4Byte Array_MP_8723D_AGC_TAB[] = {
|
||||
0xC78, 0xFE000101,
|
||||
0xC78, 0xFD010101,
|
||||
0xC78, 0xFC020101,
|
||||
0xC78, 0xFB030101,
|
||||
0xC78, 0xFA040101,
|
||||
0xC78, 0xF9050101,
|
||||
0xC78, 0xF8060101,
|
||||
0xC78, 0xF7070101,
|
||||
0xC78, 0xF6080101,
|
||||
0xC78, 0xF5090101,
|
||||
0xC78, 0xF40A0101,
|
||||
0xC78, 0xF30B0101,
|
||||
0xC78, 0xF20C0101,
|
||||
0xC78, 0xF10D0101,
|
||||
0xC78, 0xF00E0101,
|
||||
0xC78, 0xEF0F0101,
|
||||
0xC78, 0xEE100101,
|
||||
0xC78, 0xED110101,
|
||||
0xC78, 0xEC120101,
|
||||
0xC78, 0xEB130101,
|
||||
0xC78, 0xEA140101,
|
||||
0xC78, 0xE9150101,
|
||||
0xC78, 0xE8160101,
|
||||
0xC78, 0xE7170101,
|
||||
0xC78, 0xE6180101,
|
||||
0xC78, 0xE5190101,
|
||||
0xC78, 0xE41A0101,
|
||||
0xC78, 0xE31B0101,
|
||||
0xC78, 0xE21C0101,
|
||||
0xC78, 0xE11D0101,
|
||||
0xC78, 0xE01E0101,
|
||||
0xC78, 0x861F0101,
|
||||
0xC78, 0x85200101,
|
||||
0xC78, 0x84210101,
|
||||
0xC78, 0x83220101,
|
||||
0xC78, 0x82230101,
|
||||
0xC78, 0x81240101,
|
||||
0xC78, 0x80250101,
|
||||
0xC78, 0x44260101,
|
||||
0xC78, 0x43270101,
|
||||
0xC78, 0x42280101,
|
||||
0xC78, 0x41290101,
|
||||
0xC78, 0x402A0101,
|
||||
0xC78, 0x022B0101,
|
||||
0xC78, 0x012C0101,
|
||||
0xC78, 0x002D0101,
|
||||
0xC78, 0xC52E0001,
|
||||
0xC78, 0xC42F0001,
|
||||
0xC78, 0xC3300001,
|
||||
0xC78, 0xC2310001,
|
||||
0xC78, 0xC1320001,
|
||||
0xC78, 0xC0330001,
|
||||
0xC78, 0x04340001,
|
||||
0xC78, 0x03350001,
|
||||
0xC78, 0x02360001,
|
||||
0xC78, 0x01370001,
|
||||
0xC78, 0x00380001,
|
||||
0xC78, 0x00390001,
|
||||
0xC78, 0x003A0001,
|
||||
0xC78, 0x003B0001,
|
||||
0xC78, 0x003C0001,
|
||||
0xC78, 0x003D0001,
|
||||
0xC78, 0x003E0001,
|
||||
0xC78, 0x003F0001,
|
||||
0xC78, 0x6F002001,
|
||||
0xC78, 0x6F012001,
|
||||
0xC78, 0x6F022001,
|
||||
0xC78, 0x6F032001,
|
||||
0xC78, 0x6F042001,
|
||||
0xC78, 0x6F052001,
|
||||
0xC78, 0x6F062001,
|
||||
0xC78, 0x6F072001,
|
||||
0xC78, 0x6F082001,
|
||||
0xC78, 0x6F092001,
|
||||
0xC78, 0x6F0A2001,
|
||||
0xC78, 0x6F0B2001,
|
||||
0xC78, 0x6F0C2001,
|
||||
0xC78, 0x6F0D2001,
|
||||
0xC78, 0x6F0E2001,
|
||||
0xC78, 0x6F0F2001,
|
||||
0xC78, 0x6F102001,
|
||||
0xC78, 0x6F112001,
|
||||
0xC78, 0x6F122001,
|
||||
0xC78, 0x6F132001,
|
||||
0xC78, 0x6F142001,
|
||||
0xC78, 0x6F152001,
|
||||
0xC78, 0x6F162001,
|
||||
0xC78, 0x6F172001,
|
||||
0xC78, 0x6F182001,
|
||||
0xC78, 0x6F192001,
|
||||
0xC78, 0x6F1A2001,
|
||||
0xC78, 0x6F1B2001,
|
||||
0xC78, 0x6F1C2001,
|
||||
0xC78, 0x6F1D2001,
|
||||
0xC78, 0x6F1E2001,
|
||||
0xC78, 0x6F1F2001,
|
||||
0xC78, 0x6F202001,
|
||||
0xC78, 0x6F212001,
|
||||
0xC78, 0x6F222001,
|
||||
0xC78, 0x6F232001,
|
||||
0xC78, 0x6E242001,
|
||||
0xC78, 0x6D252001,
|
||||
0xC78, 0x6C262001,
|
||||
0xC78, 0x6B272001,
|
||||
0xC78, 0x6A282001,
|
||||
0xC78, 0x69292001,
|
||||
0xC78, 0x4B2A2001,
|
||||
0xC78, 0x4A2B2001,
|
||||
0xC78, 0x492C2001,
|
||||
0xC78, 0x482D2001,
|
||||
0xC78, 0x472E2001,
|
||||
0xC78, 0x462F2001,
|
||||
0xC78, 0x45302001,
|
||||
0xC78, 0x44312001,
|
||||
0xC78, 0x43322001,
|
||||
0xC78, 0x42332001,
|
||||
0xC78, 0x41342001,
|
||||
0xC78, 0x40352001,
|
||||
0xC78, 0x02362001,
|
||||
0xC78, 0x01372001,
|
||||
0xC78, 0x00382001,
|
||||
0xC78, 0x00392001,
|
||||
0xC78, 0x003A2001,
|
||||
0xC78, 0x003B2001,
|
||||
0xC78, 0x003C2001,
|
||||
0xC78, 0x003D2001,
|
||||
0xC78, 0x003E2001,
|
||||
0xC78, 0x003F2001,
|
||||
0xC78, 0x7F003101,
|
||||
0xC78, 0x7F013101,
|
||||
0xC78, 0x7F023101,
|
||||
0xC78, 0x7F033101,
|
||||
0xC78, 0x7F043101,
|
||||
0xC78, 0x7F053101,
|
||||
0xC78, 0x7F063101,
|
||||
0xC78, 0x7F073101,
|
||||
0xC78, 0x7E083101,
|
||||
0xC78, 0x7D093101,
|
||||
0xC78, 0x7C0A3101,
|
||||
0xC78, 0x7B0B3101,
|
||||
0xC78, 0x7A0C3101,
|
||||
0xC78, 0x790D3101,
|
||||
0xC78, 0x780E3101,
|
||||
0xC78, 0x770F3101,
|
||||
0xC78, 0x76103101,
|
||||
0xC78, 0x75113101,
|
||||
0xC78, 0x74123101,
|
||||
0xC78, 0x73133101,
|
||||
0xC78, 0x72143101,
|
||||
0xC78, 0x71153101,
|
||||
0xC78, 0x70163101,
|
||||
0xC78, 0x6F173101,
|
||||
0xC78, 0x6E183101,
|
||||
0xC78, 0x6D193101,
|
||||
0xC78, 0x6C1A3101,
|
||||
0xC78, 0x6B1B3101,
|
||||
0xC78, 0x6A1C3101,
|
||||
0xC78, 0x691D3101,
|
||||
0xC78, 0x681E3101,
|
||||
0xC78, 0x4B1F3101,
|
||||
0xC78, 0x4A203101,
|
||||
0xC78, 0x49213101,
|
||||
0xC78, 0x48223101,
|
||||
0xC78, 0x47233101,
|
||||
0xC78, 0x46243101,
|
||||
0xC78, 0x45253101,
|
||||
0xC78, 0x44263101,
|
||||
0xC78, 0x43273101,
|
||||
0xC78, 0x42283101,
|
||||
0xC78, 0x41293101,
|
||||
0xC78, 0x402A3101,
|
||||
0xC78, 0x022B3101,
|
||||
0xC78, 0x012C3101,
|
||||
0xC78, 0x002D3101,
|
||||
0xC78, 0x002E3101,
|
||||
0xC78, 0x002F3101,
|
||||
0xC78, 0x00303101,
|
||||
0xC78, 0x00313101,
|
||||
0xC78, 0x00323101,
|
||||
0xC78, 0x00333101,
|
||||
0xC78, 0x00343101,
|
||||
0xC78, 0x00353101,
|
||||
0xC78, 0x00363101,
|
||||
0xC78, 0x00373101,
|
||||
0xC78, 0x00383101,
|
||||
0xC78, 0x00393101,
|
||||
0xC78, 0x003A3101,
|
||||
0xC78, 0x003B3101,
|
||||
0xC78, 0x003C3101,
|
||||
0xC78, 0x003D3101,
|
||||
0xC78, 0x003E3101,
|
||||
0xC78, 0x003F3101,
|
||||
0xC78, 0xFE403101,
|
||||
0xC78, 0xFD413101,
|
||||
0xC78, 0xFC423101,
|
||||
0xC78, 0xFB433101,
|
||||
0xC78, 0xFA443101,
|
||||
0xC78, 0xF9453101,
|
||||
0xC78, 0xF8463101,
|
||||
0xC78, 0xF7473101,
|
||||
0xC78, 0xF6483101,
|
||||
0xC78, 0xF5493101,
|
||||
0xC78, 0xF44A3101,
|
||||
0xC78, 0xF34B3101,
|
||||
0xC78, 0xF24C3101,
|
||||
0xC78, 0xF14D3101,
|
||||
0xC78, 0xF04E3101,
|
||||
0xC78, 0xEF4F3101,
|
||||
0xC78, 0xEE503101,
|
||||
0xC78, 0xED513101,
|
||||
0xC78, 0xEC523101,
|
||||
0xC78, 0xEB533101,
|
||||
0xC78, 0xEA543101,
|
||||
0xC78, 0xE9553101,
|
||||
0xC78, 0xE8563101,
|
||||
0xC78, 0xE7573101,
|
||||
0xC78, 0xE6583101,
|
||||
0xC78, 0xE5593101,
|
||||
0xC78, 0xE45A3101,
|
||||
0xC78, 0xE35B3101,
|
||||
0xC78, 0xE25C3101,
|
||||
0xC78, 0xE15D3101,
|
||||
0xC78, 0xE05E3101,
|
||||
0xC78, 0x865F3101,
|
||||
0xC78, 0x85603101,
|
||||
0xC78, 0x84613101,
|
||||
0xC78, 0x83623101,
|
||||
0xC78, 0x82633101,
|
||||
0xC78, 0x81643101,
|
||||
0xC78, 0x80653101,
|
||||
0xC78, 0x80663101,
|
||||
0xC78, 0x80673101,
|
||||
0xC78, 0x80683101,
|
||||
0xC78, 0x80693101,
|
||||
0xC78, 0x806A3101,
|
||||
0xC78, 0x806B3101,
|
||||
0xC78, 0x806C3101,
|
||||
0xC78, 0x806D3101,
|
||||
0xC78, 0x806E3101,
|
||||
0xC78, 0x806F3101,
|
||||
0xC78, 0x80703101,
|
||||
0xC78, 0x80713101,
|
||||
0xC78, 0x80723101,
|
||||
0xC78, 0x80733101,
|
||||
0xC78, 0x80743101,
|
||||
0xC78, 0x80753101,
|
||||
0xC78, 0x80763101,
|
||||
0xC78, 0x80773101,
|
||||
0xC78, 0x80783101,
|
||||
0xC78, 0x80793101,
|
||||
0xC78, 0x807A3101,
|
||||
0xC78, 0x807B3101,
|
||||
0xC78, 0x807C3101,
|
||||
0xC78, 0x807D3101,
|
||||
0xC78, 0x807E3101,
|
||||
0xC78, 0x807F3101,
|
||||
0xC78, 0xEF402001,
|
||||
0xC78, 0xEF412001,
|
||||
0xC78, 0xEF422001,
|
||||
0xC78, 0xEF432001,
|
||||
0xC78, 0xEF442001,
|
||||
0xC78, 0xEF452001,
|
||||
0xC78, 0xEF462001,
|
||||
0xC78, 0xEF472001,
|
||||
0xC78, 0xEF482001,
|
||||
0xC78, 0xEF492001,
|
||||
0xC78, 0xEF4A2001,
|
||||
0xC78, 0xEF4B2001,
|
||||
0xC78, 0xEF4C2001,
|
||||
0xC78, 0xEF4D2001,
|
||||
0xC78, 0xEF4E2001,
|
||||
0xC78, 0xEF4F2001,
|
||||
0xC78, 0xEF502001,
|
||||
0xC78, 0xEF512001,
|
||||
0xC78, 0xEF522001,
|
||||
0xC78, 0xEF532001,
|
||||
0xC78, 0xEF542001,
|
||||
0xC78, 0xEF552001,
|
||||
0xC78, 0xEF562001,
|
||||
0xC78, 0xEF572001,
|
||||
0xC78, 0xEF582001,
|
||||
0xC78, 0xEF592001,
|
||||
0xC78, 0xEF5A2001,
|
||||
0xC78, 0xEF5B2001,
|
||||
0xC78, 0xEF5C2001,
|
||||
0xC78, 0xEF5D2001,
|
||||
0xC78, 0xEF5E2001,
|
||||
0xC78, 0xEF5F2001,
|
||||
0xC78, 0xEF602001,
|
||||
0xC78, 0xEE612001,
|
||||
0xC78, 0xED622001,
|
||||
0xC78, 0xEC632001,
|
||||
0xC78, 0xEB642001,
|
||||
0xC78, 0xEA652001,
|
||||
0xC78, 0xE9662001,
|
||||
0xC78, 0xE8672001,
|
||||
0xC78, 0xCB682001,
|
||||
0xC78, 0xCA692001,
|
||||
0xC78, 0xC96A2001,
|
||||
0xC78, 0xC86B2001,
|
||||
0xC78, 0xC76C2001,
|
||||
0xC78, 0xC66D2001,
|
||||
0xC78, 0xC56E2001,
|
||||
0xC78, 0xC46F2001,
|
||||
0xC78, 0xC3702001,
|
||||
0xC78, 0xC2712001,
|
||||
0xC78, 0xC1722001,
|
||||
0xC78, 0xC0732001,
|
||||
0xC78, 0x82742001,
|
||||
0xC78, 0x81752001,
|
||||
0xC78, 0x80762001,
|
||||
0xC78, 0x80772001,
|
||||
0xC78, 0x80782001,
|
||||
0xC78, 0x80792001,
|
||||
0xC78, 0x807A2001,
|
||||
0xC78, 0x807B2001,
|
||||
0xC78, 0x807C2001,
|
||||
0xC78, 0x807D2001,
|
||||
0xC78, 0x807E2001,
|
||||
0xC78, 0x807F2001,
|
||||
0xC78, 0xFA001101,
|
||||
0xC78, 0xF9011101,
|
||||
0xC78, 0xF8021101,
|
||||
0xC78, 0xF7031101,
|
||||
0xC78, 0xF6041101,
|
||||
0xC78, 0xF5051101,
|
||||
0xC78, 0xF4061101,
|
||||
0xC78, 0xD7071101,
|
||||
0xC78, 0xD6081101,
|
||||
0xC78, 0xD5091101,
|
||||
0xC78, 0xD40A1101,
|
||||
0xC78, 0x970B1101,
|
||||
0xC78, 0x960C1101,
|
||||
0xC78, 0x950D1101,
|
||||
0xC78, 0x940E1101,
|
||||
0xC78, 0x930F1101,
|
||||
0xC78, 0x92101101,
|
||||
0xC78, 0x91111101,
|
||||
0xC78, 0x90121101,
|
||||
0xC78, 0x8F131101,
|
||||
0xC78, 0x8E141101,
|
||||
0xC78, 0x8D151101,
|
||||
0xC78, 0x8C161101,
|
||||
0xC78, 0x8B171101,
|
||||
0xC78, 0x8A181101,
|
||||
0xC78, 0x89191101,
|
||||
0xC78, 0x881A1101,
|
||||
0xC78, 0x871B1101,
|
||||
0xC78, 0x861C1101,
|
||||
0xC78, 0x851D1101,
|
||||
0xC78, 0x841E1101,
|
||||
0xC78, 0x831F1101,
|
||||
0xC78, 0x82201101,
|
||||
0xC78, 0x81211101,
|
||||
0xC78, 0x80221101,
|
||||
0xC78, 0x43231101,
|
||||
0xC78, 0x42241101,
|
||||
0xC78, 0x41251101,
|
||||
0xC78, 0x04261101,
|
||||
0xC78, 0x03271101,
|
||||
0xC78, 0x02281101,
|
||||
0xC78, 0x01291101,
|
||||
0xC78, 0x002A1101,
|
||||
0xC78, 0xC42B1001,
|
||||
0xC78, 0xC32C1001,
|
||||
0xC78, 0xC22D1001,
|
||||
0xC78, 0xC12E1001,
|
||||
0xC78, 0xC02F1001,
|
||||
0xC78, 0x85301001,
|
||||
0xC78, 0x84311001,
|
||||
0xC78, 0x83321001,
|
||||
0xC78, 0x82331001,
|
||||
0xC78, 0x81341001,
|
||||
0xC78, 0x80351001,
|
||||
0xC78, 0x05361001,
|
||||
0xC78, 0x04371001,
|
||||
0xC78, 0x03381001,
|
||||
0xC78, 0x02391001,
|
||||
0xC78, 0x013A1001,
|
||||
0xC78, 0x003B1001,
|
||||
0xC78, 0x003C1001,
|
||||
0xC78, 0x003D1001,
|
||||
0xC78, 0x003E1001,
|
||||
0xC78, 0x003F1001,
|
||||
0xC50, 0x69553422,
|
||||
0xC50, 0x69553420,
|
||||
|
||||
};
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_AGC_TAB(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
u4Byte i = 0;
|
||||
u1Byte cCond;
|
||||
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
|
||||
u4Byte ArrayLen = sizeof(Array_MP_8723D_AGC_TAB)/sizeof(u4Byte);
|
||||
pu4Byte Array = Array_MP_8723D_AGC_TAB;
|
||||
|
||||
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_AGC_TAB\n"));
|
||||
|
||||
while ((i + 1) < ArrayLen) {
|
||||
v1 = Array[i];
|
||||
v2 = Array[i + 1];
|
||||
|
||||
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
|
||||
if (v1 & BIT31) {/* positive condition*/
|
||||
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
|
||||
if (cCond == COND_ENDIF) {/*end*/
|
||||
bMatched = TRUE;
|
||||
bSkipped = FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
|
||||
} else if (cCond == COND_ELSE) { /*else*/
|
||||
bMatched = bSkipped?FALSE:TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
|
||||
} else {/*if , else if*/
|
||||
pre_v1 = v1;
|
||||
pre_v2 = v2;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
|
||||
}
|
||||
} else if (v1 & BIT30) { /*negative condition*/
|
||||
if (bSkipped == FALSE) {
|
||||
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
|
||||
bMatched = TRUE;
|
||||
bSkipped = TRUE;
|
||||
} else {
|
||||
bMatched = FALSE;
|
||||
bSkipped = FALSE;
|
||||
}
|
||||
} else
|
||||
bMatched = FALSE;
|
||||
}
|
||||
} else {
|
||||
if (bMatched)
|
||||
odm_ConfigBB_AGC_8723D(pDM_Odm, v1, bMaskDWord, v2);
|
||||
}
|
||||
i = i + 2;
|
||||
}
|
||||
}
|
||||
|
||||
u4Byte
|
||||
ODM_GetVersion_MP_8723D_AGC_TAB(void)
|
||||
{
|
||||
return 31;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
u4Byte Array_MP_8723D_PHY_REG[] = {
|
||||
0x800, 0x80046C00,
|
||||
0x804, 0x00000003,
|
||||
0x808, 0x0000FC00,
|
||||
0x80C, 0x0000000A,
|
||||
0x810, 0x10001331,
|
||||
0x814, 0x020C3D10,
|
||||
0x818, 0x00200385,
|
||||
0x81C, 0x00000000,
|
||||
0x820, 0x01000100,
|
||||
0x824, 0x00390204,
|
||||
0x828, 0x00000000,
|
||||
0x82C, 0x00000000,
|
||||
0x830, 0x00000000,
|
||||
0x834, 0x00000000,
|
||||
0x838, 0x00000000,
|
||||
0x83C, 0x00000000,
|
||||
0x840, 0x00010000,
|
||||
0x844, 0x00000000,
|
||||
0x848, 0x00000000,
|
||||
0x84C, 0x00000000,
|
||||
0x850, 0x00000000,
|
||||
0x854, 0x00000000,
|
||||
0x858, 0x569A11A9,
|
||||
0x85C, 0x01000014,
|
||||
0x860, 0x66F60110,
|
||||
0x864, 0x461F0641,
|
||||
0x868, 0x00000000,
|
||||
0x86C, 0x27272700,
|
||||
0x870, 0x07000460,
|
||||
0x874, 0x25004000,
|
||||
0x878, 0x00000808,
|
||||
0x87C, 0x004F0201,
|
||||
0x880, 0xB2002E12,
|
||||
0x884, 0x00000007,
|
||||
0x888, 0x00000000,
|
||||
0x88C, 0xCCC000C0,
|
||||
0x890, 0x00000800,
|
||||
0x894, 0xFFFFFFFE,
|
||||
0x898, 0x40302010,
|
||||
0x89C, 0x00706050,
|
||||
0x900, 0x00000000,
|
||||
0x904, 0x00000023,
|
||||
0x908, 0x00000000,
|
||||
0x90C, 0x81121111,
|
||||
0x910, 0x00000402,
|
||||
0x914, 0x00000300,
|
||||
0x920, 0x18C6318C,
|
||||
0x924, 0x0000018C,
|
||||
0x948, 0x99000000,
|
||||
0x94C, 0x00000010,
|
||||
0x950, 0x00003800,
|
||||
0x954, 0x5A380000,
|
||||
0x958, 0x4BC6D87A,
|
||||
0x95C, 0x04EB9B79,
|
||||
0x96C, 0x00000003,
|
||||
0x970, 0x00000000,
|
||||
0x974, 0x00000000,
|
||||
0x978, 0x00000000,
|
||||
0x97C, 0x13000000,
|
||||
0x980, 0x00000000,
|
||||
0xA00, 0x00D047C8,
|
||||
0xA04, 0x80FF800C,
|
||||
0xA08, 0x8C838300,
|
||||
0xA0C, 0x2E20100F,
|
||||
0xA10, 0x9500BB78,
|
||||
0xA14, 0x1114D028,
|
||||
0xA18, 0x00881117,
|
||||
0xA1C, 0x89140F00,
|
||||
0xA20, 0xE82C0001,
|
||||
0xA24, 0x64B80C1C,
|
||||
0xA28, 0x00008810,
|
||||
0xA2C, 0x00D30000,
|
||||
0xA70, 0x101FBF00,
|
||||
0xA74, 0x00000007,
|
||||
0xA78, 0x00008900,
|
||||
0xA7C, 0x225B0606,
|
||||
0xA80, 0x2180FA74,
|
||||
0xA84, 0x00200000,
|
||||
0xA88, 0x040C0000,
|
||||
0xA8C, 0x12345678,
|
||||
0xA90, 0xABCDEF00,
|
||||
0xA94, 0x001B1B89,
|
||||
0xA98, 0x00000000,
|
||||
0xA9C, 0x00020000,
|
||||
0xAA0, 0x00000000,
|
||||
0xAA4, 0x0000000C,
|
||||
0xAA8, 0xCA100008,
|
||||
0xAAC, 0x01235667,
|
||||
0xAB0, 0x00000000,
|
||||
0xAB4, 0x20201402,
|
||||
0xB2C, 0x00000000,
|
||||
0xC00, 0x48071D40,
|
||||
0xC04, 0x03A05611,
|
||||
0xC08, 0x000000E4,
|
||||
0xC0C, 0x6C6C6C6C,
|
||||
0xC10, 0x28800000,
|
||||
0xC14, 0x40000100,
|
||||
0xC18, 0x08800000,
|
||||
0xC1C, 0x40000100,
|
||||
0xC20, 0x00000000,
|
||||
0xC24, 0x00000000,
|
||||
0xC28, 0x00000000,
|
||||
0xC2C, 0x00000000,
|
||||
0xC30, 0x69E9AC48,
|
||||
0xC34, 0x31000040,
|
||||
0xC38, 0x21688080,
|
||||
0xC3C, 0x000016D4,
|
||||
0xC40, 0x1F78403F,
|
||||
0xC44, 0x00010036,
|
||||
0xC48, 0xEC020107,
|
||||
0xC4C, 0x007F037F,
|
||||
0xC50, 0x69553420,
|
||||
0xC54, 0x43BC0094,
|
||||
0xC58, 0x00015969,
|
||||
0xC5C, 0x00310492,
|
||||
0xC60, 0x00280A00,
|
||||
0xC64, 0x7112848B,
|
||||
0xC68, 0x47C074FF,
|
||||
0xC6C, 0x00000036,
|
||||
0xC70, 0x2C7F000D,
|
||||
0xC74, 0x020600DB,
|
||||
0xC78, 0x0000001F,
|
||||
0xC7C, 0x00B91612,
|
||||
0xC80, 0x390000E4,
|
||||
0xC84, 0x11F60000,
|
||||
0xC88, 0x40000100,
|
||||
0xC8C, 0x20200000,
|
||||
0xC90, 0x00091521,
|
||||
0xC94, 0x00000000,
|
||||
0xC98, 0x00121820,
|
||||
0xC9C, 0x00007F7F,
|
||||
0xCA0, 0x00012000,
|
||||
0xCA4, 0xA00000A0,
|
||||
0xCA8, 0x85E7C606,
|
||||
0xCAC, 0x00000060,
|
||||
0xCB0, 0x00000000,
|
||||
0xCB4, 0x00000000,
|
||||
0xCB8, 0x00000000,
|
||||
0xCBC, 0x28000000,
|
||||
0xCC0, 0x0010A3D0,
|
||||
0xCC4, 0x00000F7D,
|
||||
0xCC8, 0x000442D6,
|
||||
0xCCC, 0x00000000,
|
||||
0xCD0, 0x000001C8,
|
||||
0xCD4, 0x001C8000,
|
||||
0xCD8, 0x00000100,
|
||||
0xCDC, 0x40100000,
|
||||
0xCE0, 0x00222220,
|
||||
0xCE4, 0x20000000,
|
||||
0xCE8, 0x37644302,
|
||||
0xCEC, 0x2F97D40C,
|
||||
0xD00, 0x00030740,
|
||||
0xD04, 0x40020401,
|
||||
0xD08, 0x0000907F,
|
||||
0xD0C, 0x20010201,
|
||||
0xD10, 0xA0633333,
|
||||
0xD14, 0x3333BC53,
|
||||
0xD18, 0x7A8F5B6F,
|
||||
0xD2C, 0xCC979975,
|
||||
0xD30, 0x00000000,
|
||||
0xD34, 0x80608000,
|
||||
0xD38, 0x88000000,
|
||||
0xD3C, 0xC0127343,
|
||||
0xD40, 0x00000000,
|
||||
0xD44, 0x00000000,
|
||||
0xD48, 0x00000000,
|
||||
0xD4C, 0x00000000,
|
||||
0xD50, 0x00000038,
|
||||
0xD54, 0x00000000,
|
||||
0xD58, 0x00000282,
|
||||
0xD5C, 0x30032064,
|
||||
0xD60, 0x4653DE68,
|
||||
0xD64, 0x04518A3C,
|
||||
0xD68, 0x00002101,
|
||||
0xE00, 0x2D2D2D2D,
|
||||
0xE04, 0x2D2D2D2D,
|
||||
0xE08, 0x0390272D,
|
||||
0xE10, 0x2D2D2D2D,
|
||||
0xE14, 0x2D2D2D2D,
|
||||
0xE18, 0x2D2D2D2D,
|
||||
0xE1C, 0x2D2D2D2D,
|
||||
0xE28, 0x00000000,
|
||||
0xE30, 0x1000DC1F,
|
||||
0xE34, 0x10008C1F,
|
||||
0xE38, 0x02140102,
|
||||
0xE3C, 0x681604C2,
|
||||
0xE40, 0x01007C00,
|
||||
0xE44, 0x01004800,
|
||||
0xE48, 0xFB000000,
|
||||
0xE4C, 0x000028D1,
|
||||
0xE50, 0x1000DC1F,
|
||||
0xE54, 0x10008C1F,
|
||||
0xE58, 0x02140102,
|
||||
0xE5C, 0x28160D05,
|
||||
0xE60, 0x00000008,
|
||||
0xE68, 0x001B25A4,
|
||||
0xE6C, 0x01C00014,
|
||||
0xE70, 0x01C00016,
|
||||
0xE74, 0x02000014,
|
||||
0xE78, 0x02000014,
|
||||
0xE7C, 0x02000014,
|
||||
0xE80, 0x02000014,
|
||||
0xE84, 0x01C00014,
|
||||
0xE88, 0x02000014,
|
||||
0xE8C, 0x01C00014,
|
||||
0xED0, 0x01C00014,
|
||||
0xED4, 0x01C00014,
|
||||
0xED8, 0x01C00014,
|
||||
0xEDC, 0x00000014,
|
||||
0xEE0, 0x00000014,
|
||||
0xEE8, 0x21555448,
|
||||
0xEEC, 0x03C00014,
|
||||
0xF14, 0x00000003,
|
||||
0xF00, 0x00100300,
|
||||
0xF08, 0x0000800B,
|
||||
0xF0C, 0x0000F007,
|
||||
0xF10, 0x0000A487,
|
||||
0xF1C, 0x80000064,
|
||||
0xF38, 0x00030155,
|
||||
0xF3C, 0x0000003A,
|
||||
0xF4C, 0x13000000,
|
||||
0xF50, 0x00000000,
|
||||
0xF18, 0x00000000,
|
||||
|
||||
};
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_PHY_REG(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
u4Byte i = 0;
|
||||
u1Byte cCond;
|
||||
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
|
||||
u4Byte ArrayLen = sizeof(Array_MP_8723D_PHY_REG)/sizeof(u4Byte);
|
||||
pu4Byte Array = Array_MP_8723D_PHY_REG;
|
||||
|
||||
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_PHY_REG\n"));
|
||||
|
||||
while ((i + 1) < ArrayLen) {
|
||||
v1 = Array[i];
|
||||
v2 = Array[i + 1];
|
||||
|
||||
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
|
||||
if (v1 & BIT31) {/* positive condition*/
|
||||
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
|
||||
if (cCond == COND_ENDIF) {/*end*/
|
||||
bMatched = TRUE;
|
||||
bSkipped = FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
|
||||
} else if (cCond == COND_ELSE) { /*else*/
|
||||
bMatched = bSkipped?FALSE:TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
|
||||
} else {/*if , else if*/
|
||||
pre_v1 = v1;
|
||||
pre_v2 = v2;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
|
||||
}
|
||||
} else if (v1 & BIT30) { /*negative condition*/
|
||||
if (bSkipped == FALSE) {
|
||||
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
|
||||
bMatched = TRUE;
|
||||
bSkipped = TRUE;
|
||||
} else {
|
||||
bMatched = FALSE;
|
||||
bSkipped = FALSE;
|
||||
}
|
||||
} else
|
||||
bMatched = FALSE;
|
||||
}
|
||||
} else {
|
||||
if (bMatched)
|
||||
odm_ConfigBB_PHY_8723D(pDM_Odm, v1, bMaskDWord, v2);
|
||||
}
|
||||
i = i + 2;
|
||||
}
|
||||
}
|
||||
|
||||
u4Byte
|
||||
ODM_GetVersion_MP_8723D_PHY_REG(void)
|
||||
{
|
||||
return 31;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG_PG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
u4Byte Array_MP_8723D_PHY_REG_PG[] = {
|
||||
0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,
|
||||
0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,
|
||||
0, 0, 0, 0x00000e00, 0xffffffff, 0x32343434,
|
||||
0, 0, 0, 0x00000e04, 0xffffffff, 0x28303032,
|
||||
0, 0, 0, 0x00000e10, 0xffffffff, 0x30323234,
|
||||
0, 0, 0, 0x00000e14, 0xffffffff, 0x26282830
|
||||
};
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_PHY_REG_PG(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
u4Byte i = 0;
|
||||
u4Byte ArrayLen = sizeof(Array_MP_8723D_PHY_REG_PG)/sizeof(u4Byte);
|
||||
pu4Byte Array = Array_MP_8723D_PHY_REG_PG;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT);
|
||||
pHalData->nLinesReadPwrByRate = ArrayLen/6;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_PHY_REG_PG\n"));
|
||||
|
||||
pDM_Odm->PhyRegPgVersion = 1;
|
||||
pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE;
|
||||
|
||||
for (i = 0; i < ArrayLen; i += 6) {
|
||||
u4Byte v1 = Array[i];
|
||||
u4Byte v2 = Array[i+1];
|
||||
u4Byte v3 = Array[i+2];
|
||||
u4Byte v4 = Array[i+3];
|
||||
u4Byte v5 = Array[i+4];
|
||||
u4Byte v6 = Array[i+5];
|
||||
|
||||
odm_ConfigBB_PHY_REG_PG_8723D(pDM_Odm, v1, v2, v3, v4, v5, v6);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
|
||||
(v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
@@ -0,0 +1,59 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.26*/
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
#ifndef __INC_MP_BB_HW_IMG_8723D_H
|
||||
#define __INC_MP_BB_HW_IMG_8723D_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* AGC_TAB.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_AGC_TAB(void);
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_PHY_REG(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_PHY_REG(void);
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG_PG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_PHY_REG_PG(void);
|
||||
|
||||
#endif
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,62 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.16*/
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
#ifndef __INC_MP_FW_HW_IMG_8723D_H
|
||||
#define __INC_MP_FW_HW_IMG_8723D_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* FW_AP.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadFirmware_MP_8723D_FW_AP(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT u1Byte *pFirmware,
|
||||
OUT u4Byte *pFirmwareSize
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* FW_NIC.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadFirmware_MP_8723D_FW_NIC(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT u1Byte *pFirmware,
|
||||
OUT u4Byte *pFirmwareSize
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* FW_WoWLAN.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadFirmware_MP_8723D_FW_WoWLAN(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
OUT u1Byte *pFirmware,
|
||||
OUT u4Byte *pFirmwareSize
|
||||
);
|
||||
|
||||
#endif
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
@@ -0,0 +1,301 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.26*/
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
static BOOLEAN
|
||||
CheckPositive(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN const u4Byte Condition1,
|
||||
IN const u4Byte Condition2,
|
||||
IN const u4Byte Condition3,
|
||||
IN const u4Byte Condition4
|
||||
)
|
||||
{
|
||||
u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/
|
||||
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/
|
||||
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/
|
||||
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
|
||||
((pDM_Odm->BoardType & BIT2) >> 2) << 4 | /* _BT*/
|
||||
((pDM_Odm->BoardType & BIT1) >> 1) << 5; /* _NGFF*/
|
||||
|
||||
u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4;
|
||||
|
||||
u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion;
|
||||
u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType;
|
||||
|
||||
u4Byte driver1 = cut_version_for_para << 24 |
|
||||
(pDM_Odm->SupportInterface & 0xF0) << 16 |
|
||||
pDM_Odm->SupportPlatform << 16 |
|
||||
pkg_type_for_para << 12 |
|
||||
(pDM_Odm->SupportInterface & 0x0F) << 8 |
|
||||
_BoardType;
|
||||
|
||||
u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 |
|
||||
(pDM_Odm->TypeGPA & 0xFF) << 8 |
|
||||
(pDM_Odm->TypeALNA & 0xFF) << 16 |
|
||||
(pDM_Odm->TypeAPA & 0xFF) << 24;
|
||||
|
||||
u4Byte driver3 = 0;
|
||||
|
||||
u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 |
|
||||
(pDM_Odm->TypeGPA & 0xFF00) |
|
||||
(pDM_Odm->TypeALNA & 0xFF00) << 8 |
|
||||
(pDM_Odm->TypeAPA & 0xFF00) << 16;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
(" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
(" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType));
|
||||
|
||||
|
||||
/*============== Value Defined Check ===============*/
|
||||
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
|
||||
|
||||
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
|
||||
return FALSE;
|
||||
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
|
||||
return FALSE;
|
||||
|
||||
/*=============== Bit Defined Check ================*/
|
||||
/* We don't care [31:28] */
|
||||
|
||||
cond1 &= 0x00FF0FFF;
|
||||
driver1 &= 0x00FF0FFF;
|
||||
|
||||
if ((cond1 & driver1) == cond1) {
|
||||
u4Byte bitMask = 0;
|
||||
|
||||
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
|
||||
return TRUE;
|
||||
|
||||
if ((cond1 & BIT0) != 0) /*GLNA*/
|
||||
bitMask |= 0x000000FF;
|
||||
if ((cond1 & BIT1) != 0) /*GPA*/
|
||||
bitMask |= 0x0000FF00;
|
||||
if ((cond1 & BIT2) != 0) /*ALNA*/
|
||||
bitMask |= 0x00FF0000;
|
||||
if ((cond1 & BIT3) != 0) /*APA*/
|
||||
bitMask |= 0xFF000000;
|
||||
|
||||
if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
} else
|
||||
return FALSE;
|
||||
}
|
||||
static BOOLEAN
|
||||
CheckNegative(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN const u4Byte Condition1,
|
||||
IN const u4Byte Condition2
|
||||
)
|
||||
{
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* MAC_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
u4Byte Array_MP_8723D_MAC_REG[] = {
|
||||
0x020, 0x00000013,
|
||||
0x02F, 0x00000010,
|
||||
0x077, 0x00000007,
|
||||
0x421, 0x0000000F,
|
||||
0x428, 0x0000000A,
|
||||
0x429, 0x00000010,
|
||||
0x430, 0x00000000,
|
||||
0x431, 0x00000000,
|
||||
0x432, 0x00000000,
|
||||
0x433, 0x00000001,
|
||||
0x434, 0x00000004,
|
||||
0x435, 0x00000005,
|
||||
0x436, 0x00000007,
|
||||
0x437, 0x00000008,
|
||||
0x43C, 0x00000004,
|
||||
0x43D, 0x00000005,
|
||||
0x43E, 0x00000007,
|
||||
0x43F, 0x00000008,
|
||||
0x440, 0x0000005D,
|
||||
0x441, 0x00000001,
|
||||
0x442, 0x00000000,
|
||||
0x444, 0x00000010,
|
||||
0x445, 0x00000000,
|
||||
0x446, 0x00000000,
|
||||
0x447, 0x00000000,
|
||||
0x448, 0x00000000,
|
||||
0x449, 0x000000F0,
|
||||
0x44A, 0x0000000F,
|
||||
0x44B, 0x0000003E,
|
||||
0x44C, 0x00000010,
|
||||
0x44D, 0x00000000,
|
||||
0x44E, 0x00000000,
|
||||
0x44F, 0x00000000,
|
||||
0x450, 0x00000000,
|
||||
0x451, 0x000000F0,
|
||||
0x452, 0x0000000F,
|
||||
0x453, 0x00000000,
|
||||
0x456, 0x0000005E,
|
||||
0x460, 0x00000066,
|
||||
0x461, 0x00000066,
|
||||
0x4C8, 0x000000FF,
|
||||
0x4C9, 0x00000008,
|
||||
0x4CC, 0x000000FF,
|
||||
0x4CD, 0x000000FF,
|
||||
0x4CE, 0x00000001,
|
||||
0x500, 0x00000026,
|
||||
0x501, 0x000000A2,
|
||||
0x502, 0x0000002F,
|
||||
0x503, 0x00000000,
|
||||
0x504, 0x00000028,
|
||||
0x505, 0x000000A3,
|
||||
0x506, 0x0000005E,
|
||||
0x507, 0x00000000,
|
||||
0x508, 0x0000002B,
|
||||
0x509, 0x000000A4,
|
||||
0x50A, 0x0000005E,
|
||||
0x50B, 0x00000000,
|
||||
0x50C, 0x0000004F,
|
||||
0x50D, 0x000000A4,
|
||||
0x50E, 0x00000000,
|
||||
0x50F, 0x00000000,
|
||||
0x512, 0x0000001C,
|
||||
0x514, 0x0000000A,
|
||||
0x516, 0x0000000A,
|
||||
0x525, 0x0000004F,
|
||||
0x550, 0x00000010,
|
||||
0x551, 0x00000010,
|
||||
0x559, 0x00000002,
|
||||
0x55C, 0x00000028,
|
||||
0x55D, 0x000000FF,
|
||||
0x605, 0x00000030,
|
||||
0x608, 0x0000000E,
|
||||
0x609, 0x0000002A,
|
||||
0x620, 0x000000FF,
|
||||
0x621, 0x000000FF,
|
||||
0x622, 0x000000FF,
|
||||
0x623, 0x000000FF,
|
||||
0x624, 0x000000FF,
|
||||
0x625, 0x000000FF,
|
||||
0x626, 0x000000FF,
|
||||
0x627, 0x000000FF,
|
||||
0x638, 0x00000028,
|
||||
0x63C, 0x0000000A,
|
||||
0x63D, 0x0000000A,
|
||||
0x63E, 0x0000000C,
|
||||
0x63F, 0x0000000C,
|
||||
0x640, 0x00000040,
|
||||
0x642, 0x00000040,
|
||||
0x643, 0x00000000,
|
||||
0x652, 0x000000C8,
|
||||
0x66A, 0x000000B0,
|
||||
0x66E, 0x00000005,
|
||||
0x700, 0x00000021,
|
||||
0x701, 0x00000043,
|
||||
0x702, 0x00000065,
|
||||
0x703, 0x00000087,
|
||||
0x708, 0x00000021,
|
||||
0x709, 0x00000043,
|
||||
0x70A, 0x00000065,
|
||||
0x70B, 0x00000087,
|
||||
0x765, 0x00000018,
|
||||
0x76E, 0x00000004,
|
||||
0x7C0, 0x00000038,
|
||||
0x7C2, 0x0000000F,
|
||||
0x7C3, 0x000000C0,
|
||||
0x073, 0x00000004,
|
||||
0x7C4, 0x00000077,
|
||||
0x07C, 0x00000003,
|
||||
0x016, 0x000000B3,
|
||||
|
||||
};
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_MAC_REG(
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
u4Byte i = 0;
|
||||
u1Byte cCond;
|
||||
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
|
||||
u4Byte ArrayLen = sizeof(Array_MP_8723D_MAC_REG)/sizeof(u4Byte);
|
||||
pu4Byte Array = Array_MP_8723D_MAC_REG;
|
||||
|
||||
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_MAC_REG\n"));
|
||||
|
||||
while ((i + 1) < ArrayLen) {
|
||||
v1 = Array[i];
|
||||
v2 = Array[i + 1];
|
||||
|
||||
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
|
||||
if (v1 & BIT31) {/* positive condition*/
|
||||
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
|
||||
if (cCond == COND_ENDIF) {/*end*/
|
||||
bMatched = TRUE;
|
||||
bSkipped = FALSE;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
|
||||
} else if (cCond == COND_ELSE) { /*else*/
|
||||
bMatched = bSkipped?FALSE:TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
|
||||
} else {/*if , else if*/
|
||||
pre_v1 = v1;
|
||||
pre_v2 = v2;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
|
||||
}
|
||||
} else if (v1 & BIT30) { /*negative condition*/
|
||||
if (bSkipped == FALSE) {
|
||||
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
|
||||
bMatched = TRUE;
|
||||
bSkipped = TRUE;
|
||||
} else {
|
||||
bMatched = FALSE;
|
||||
bSkipped = FALSE;
|
||||
}
|
||||
} else
|
||||
bMatched = FALSE;
|
||||
}
|
||||
} else {
|
||||
if (bMatched)
|
||||
odm_ConfigMAC_8723D(pDM_Odm, v1, (u1Byte)v2);
|
||||
}
|
||||
i = i + 2;
|
||||
}
|
||||
}
|
||||
|
||||
u4Byte
|
||||
ODM_GetVersion_MP_8723D_MAC_REG(void)
|
||||
{
|
||||
return 31;
|
||||
}
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.26*/
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
#ifndef __INC_MP_MAC_HW_IMG_8723D_H
|
||||
#define __INC_MP_MAC_HW_IMG_8723D_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* MAC_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_MAC_REG(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_MAC_REG(void);
|
||||
|
||||
#endif
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,89 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.26*/
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
#ifndef __INC_MP_RF_HW_IMG_8723D_H
|
||||
#define __INC_MP_RF_HW_IMG_8723D_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* RadioA.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_RadioA(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_RadioA(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_PCIE.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_PCIE(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_SDIO.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_SDIO(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_USB.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_USB(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TXPWR_LMT.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_TXPWR_LMT(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxXtalTrack.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723D_TxXtalTrack(/* TC: Test Chip, MP: MP Chip*/
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u4Byte ODM_GetVersion_MP_8723D_TxXtalTrack(void);
|
||||
|
||||
#endif
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,153 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_8723D_H__
|
||||
#define __HAL_PHY_RF_8723D_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define IQK_DELAY_TIME_8723D 10 //ms
|
||||
#define index_mapping_NUM_8723D 15
|
||||
#define AVG_THERMAL_NUM_8723D 4
|
||||
#define RF_T_METER_8723D 0x42
|
||||
|
||||
void ConfigureTxpowerTrack_8723D(
|
||||
PTXPWRTRACK_CFG pConfig
|
||||
);
|
||||
|
||||
VOID
|
||||
GetDeltaSwingTable_8723D(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PVOID pDM_VOID,
|
||||
#else
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
#endif
|
||||
OUT pu1Byte *TemperatureUP_A,
|
||||
OUT pu1Byte *TemperatureDOWN_A,
|
||||
OUT pu1Byte *TemperatureUP_B,
|
||||
OUT pu1Byte *TemperatureDOWN_B
|
||||
);
|
||||
|
||||
VOID
|
||||
setCCKFilterCoefficient_8723D(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u1Byte CCKSwingIndex
|
||||
);
|
||||
|
||||
void DoIQK_8723D(
|
||||
PVOID pDM_VOID,
|
||||
u1Byte DeltaThermalIndex,
|
||||
u1Byte ThermalValue,
|
||||
u1Byte Threshold
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_TxPwrTrackSetPwr_8723D(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PVOID pDM_VOID,
|
||||
#else
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
#endif
|
||||
PWRTRACK_METHOD Method,
|
||||
u1Byte RFPath,
|
||||
u1Byte ChannelMappedIndex
|
||||
);
|
||||
|
||||
VOID
|
||||
ODM_TxXtalTrackSetXtal_8723D(
|
||||
PVOID pDM_VOID
|
||||
);
|
||||
|
||||
//1 7. IQK
|
||||
|
||||
void
|
||||
PHY_IQCalibrate_8723D(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
#else
|
||||
IN PADAPTER Adapter,
|
||||
#endif
|
||||
IN BOOLEAN bReCovery);
|
||||
|
||||
|
||||
//
|
||||
// LC calibrate
|
||||
//
|
||||
void
|
||||
PHY_LCCalibrate_8723D(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PVOID pDM_VOID
|
||||
#else
|
||||
IN PDM_ODM_T pDM_Odm
|
||||
#endif
|
||||
);
|
||||
|
||||
//
|
||||
// AP calibrate
|
||||
//
|
||||
void
|
||||
PHY_APCalibrate_8723D(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
#else
|
||||
IN PADAPTER pAdapter,
|
||||
#endif
|
||||
IN s1Byte delta);
|
||||
void
|
||||
PHY_DigitalPredistortion_8723D( IN PADAPTER pAdapter);
|
||||
|
||||
|
||||
VOID
|
||||
_PHY_SaveADDARegisters_8723D(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
#else
|
||||
IN PADAPTER pAdapter,
|
||||
#endif
|
||||
IN pu4Byte ADDAReg,
|
||||
IN pu4Byte ADDABackup,
|
||||
IN u4Byte RegisterNum
|
||||
);
|
||||
|
||||
VOID
|
||||
_PHY_PathADDAOn_8723D(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
#else
|
||||
IN PADAPTER pAdapter,
|
||||
#endif
|
||||
IN pu4Byte ADDAReg,
|
||||
IN BOOLEAN isPathAOn,
|
||||
IN BOOLEAN is2T
|
||||
);
|
||||
|
||||
VOID
|
||||
_PHY_MACSettingCalibration_8723D(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
#else
|
||||
IN PADAPTER pAdapter,
|
||||
#endif
|
||||
IN pu4Byte MACReg,
|
||||
IN pu4Byte MACBackup
|
||||
);
|
||||
|
||||
|
||||
#endif // #ifndef __HAL_PHY_RF_8723D_H__
|
||||
|
||||
@@ -0,0 +1,189 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "Mp_Precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
|
||||
void
|
||||
odm_ConfigRFReg_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Data,
|
||||
IN ODM_RF_RADIO_PATH_E RF_PATH,
|
||||
IN u4Byte RegAddr
|
||||
)
|
||||
{
|
||||
if(Addr == 0xfe || Addr == 0xffe)
|
||||
{
|
||||
#ifdef CONFIG_LONG_DELAY_ISSUE
|
||||
ODM_sleep_ms(50);
|
||||
#else
|
||||
ODM_delay_ms(50);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
|
||||
// Add 1us delay between BB/RF register setting.
|
||||
ODM_delay_us(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_ConfigRF_RadioA_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Data
|
||||
)
|
||||
{
|
||||
u4Byte content = 0x1000; // RF_Content: radioa_txt
|
||||
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
|
||||
|
||||
odm_ConfigRFReg_8723D(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
|
||||
}
|
||||
|
||||
void
|
||||
odm_ConfigRF_RadioB_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Data
|
||||
)
|
||||
{
|
||||
u4Byte content = 0x1001; // RF_Content: radiob_txt
|
||||
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
|
||||
|
||||
odm_ConfigRFReg_8723D(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_ConfigMAC_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u1Byte Data
|
||||
)
|
||||
{
|
||||
ODM_Write1Byte(pDM_Odm, Addr, Data);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
|
||||
}
|
||||
|
||||
void
|
||||
odm_ConfigBB_AGC_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Bitmask,
|
||||
IN u4Byte Data
|
||||
)
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
|
||||
// Add 1us delay between BB/RF register setting.
|
||||
ODM_delay_us(1);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
|
||||
}
|
||||
|
||||
void
|
||||
odm_ConfigBB_PHY_REG_PG_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Band,
|
||||
IN u4Byte RfPath,
|
||||
IN u4Byte TxNum,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Bitmask,
|
||||
IN u4Byte Data
|
||||
)
|
||||
{
|
||||
if (Addr == 0xfe || Addr == 0xffe)
|
||||
#ifdef CONFIG_LONG_DELAY_ISSUE
|
||||
ODM_sleep_ms(50);
|
||||
#else
|
||||
ODM_delay_ms(50);
|
||||
#endif
|
||||
else
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
|
||||
PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
|
||||
#endif
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
|
||||
}
|
||||
|
||||
void
|
||||
odm_ConfigBB_PHY_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Bitmask,
|
||||
IN u4Byte Data
|
||||
)
|
||||
{
|
||||
/*DbgPrint("odm_ConfigBB_PHY_8723D(), Addr = 0x%x, data = 0x%x\n", Addr, Data);*/
|
||||
if (Addr == 0xfe)
|
||||
#ifdef CONFIG_LONG_DELAY_ISSUE
|
||||
ODM_sleep_ms(50);
|
||||
#else
|
||||
ODM_delay_ms(50);
|
||||
#endif
|
||||
else if (Addr == 0xfd)
|
||||
ODM_delay_ms(5);
|
||||
else if (Addr == 0xfc)
|
||||
ODM_delay_ms(1);
|
||||
else if (Addr == 0xfb)
|
||||
ODM_delay_us(50);
|
||||
else if (Addr == 0xfa)
|
||||
ODM_delay_us(5);
|
||||
else if (Addr == 0xf9)
|
||||
ODM_delay_us(1);
|
||||
else
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
|
||||
}
|
||||
|
||||
// Add 1us delay between BB/RF register setting.
|
||||
ODM_delay_us(1);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
|
||||
}
|
||||
|
||||
void
|
||||
odm_ConfigBB_TXPWR_LMT_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN pu1Byte Regulation,
|
||||
IN pu1Byte Band,
|
||||
IN pu1Byte Bandwidth,
|
||||
IN pu1Byte RateSection,
|
||||
IN pu1Byte RfPath,
|
||||
IN pu1Byte Channel,
|
||||
IN pu1Byte PowerLimit
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
|
||||
Bandwidth, RateSection, RfPath, Channel, PowerLimit);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __INC_ODM_REGCONFIG_H_8723D
|
||||
#define __INC_ODM_REGCONFIG_H_8723D
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
|
||||
void
|
||||
odm_ConfigRFReg_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Data,
|
||||
IN ODM_RF_RADIO_PATH_E RF_PATH,
|
||||
IN u4Byte RegAddr
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigRF_RadioA_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Data
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigRF_RadioB_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Data
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigMAC_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u1Byte Data
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigBB_AGC_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Bitmask,
|
||||
IN u4Byte Data
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigBB_PHY_REG_PG_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Band,
|
||||
IN u4Byte RfPath,
|
||||
IN u4Byte TxNum,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Bitmask,
|
||||
IN u4Byte Data
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigBB_PHY_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u4Byte Addr,
|
||||
IN u4Byte Bitmask,
|
||||
IN u4Byte Data
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigBB_TXPWR_LMT_8723D(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN pu1Byte Regulation,
|
||||
IN pu1Byte Band,
|
||||
IN pu1Byte Bandwidth,
|
||||
IN pu1Byte RateSection,
|
||||
IN pu1Byte RfPath,
|
||||
IN pu1Byte Channel,
|
||||
IN pu1Byte PowerLimit
|
||||
);
|
||||
|
||||
|
||||
#endif
|
||||
#endif // end of SUPPORT
|
||||
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*============================================================
|
||||
include files
|
||||
============================================================*/
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
|
||||
s1Byte
|
||||
odm_CCKRSSI_8723D(
|
||||
IN u1Byte LNA_idx,
|
||||
IN u1Byte VGA_idx
|
||||
)
|
||||
{
|
||||
s1Byte rx_pwr_all = 0x00;
|
||||
|
||||
switch (LNA_idx) {
|
||||
|
||||
case 0xf:
|
||||
rx_pwr_all = -46 - (2 * VGA_idx);
|
||||
break;
|
||||
case 0xa:
|
||||
rx_pwr_all = -20 - (2 * VGA_idx);
|
||||
break;
|
||||
case 7:
|
||||
rx_pwr_all = -10 - (2 * VGA_idx);
|
||||
break;
|
||||
case 4:
|
||||
rx_pwr_all = 4 - (2 * VGA_idx);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return rx_pwr_all;
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __ODM_RTL8723D_H__
|
||||
#define __ODM_RTL8723D_H__
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
|
||||
s1Byte
|
||||
odm_CCKRSSI_8723D(
|
||||
IN u1Byte LNA_idx,
|
||||
IN u1Byte VGA_idx
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,5 @@
|
||||
/*RTL8723D PHY Parameters*/
|
||||
#define SVN_COMMIT_VERSION_8723D 22597
|
||||
#define RELEASE_DATE_8723D 20161209
|
||||
#define COMMIT_BY_8723D "BB_Jessica"
|
||||
#define RELEASE_VERSION_8723D 31
|
||||
@@ -0,0 +1,536 @@
|
||||
//============================================================
|
||||
// Description:
|
||||
//
|
||||
// This file is for TXBF mechanism
|
||||
//
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
/*Beamforming halcomtxbf API create by YuChen 2015/05*/
|
||||
|
||||
VOID
|
||||
halComTxbf_beamformInit(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8822B)
|
||||
HalTxbf8822B_Init(pDM_Odm);
|
||||
}
|
||||
|
||||
/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/
|
||||
VOID
|
||||
halComTxbf_ConfigGtab(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8822B)
|
||||
HalTxbf8822B_ConfigGtab(pDM_Odm);
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_beamformSetSoundingEnter(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_EnterWorkItem)) == FALSE)
|
||||
PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_EnterWorkItem));
|
||||
#else
|
||||
halComTxbf_EnterWorkItemCallback(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_beamformSetSoundingLeave(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_LeaveWorkItem)) == FALSE)
|
||||
PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_LeaveWorkItem));
|
||||
#else
|
||||
halComTxbf_LeaveWorkItemCallback(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_beamformSetSoundingRate(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_RateWorkItem)) == FALSE)
|
||||
PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_RateWorkItem));
|
||||
#else
|
||||
halComTxbf_RateWorkItemCallback(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_beamformSetSoundingStatus(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_StatusWorkItem)) == FALSE)
|
||||
PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_StatusWorkItem));
|
||||
#else
|
||||
halComTxbf_StatusWorkItemCallback(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_beamformSetSoundingFwNdpa(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
if (*pDM_Odm->pbFwDwRsvdPageInProgress)
|
||||
ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5);
|
||||
else
|
||||
PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem));
|
||||
#else
|
||||
halComTxbf_FwNdpaWorkItemCallback(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_beamformSetSoundingClk(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ClkWorkItem)) == FALSE)
|
||||
PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ClkWorkItem));
|
||||
#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
PADAPTER padapter = pDM_Odm->Adapter;
|
||||
|
||||
rtw_run_in_thread_cmd(padapter, halComTxbf_ClkWorkItemCallback, padapter);
|
||||
#else
|
||||
halComTxbf_ClkWorkItemCallback(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_beamformSetResetTxPath(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ResetTxPathWorkItem)) == FALSE)
|
||||
PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ResetTxPathWorkItem));
|
||||
#else
|
||||
halComTxbf_ResetTxPathWorkItemCallback(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
phydm_beamformSetGetTxRate(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_GetTxRateWorkItem)) == FALSE)
|
||||
PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_GetTxRateWorkItem));
|
||||
#else
|
||||
halComTxbf_GetTxRateWorkItemCallback(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
halComTxbf_EnterWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#else
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#endif
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
u1Byte Idx = pTxbfInfo->TXBFIdx;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821))
|
||||
HalTxbfJaguar_Enter(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8192E)
|
||||
HalTxbf8192E_Enter(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
HalTxbf8814A_Enter(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8822B)
|
||||
HalTxbf8822B_Enter(pDM_Odm, Idx);
|
||||
}
|
||||
|
||||
VOID
|
||||
halComTxbf_LeaveWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#else
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#endif
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
u1Byte Idx = pTxbfInfo->TXBFIdx;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821))
|
||||
HalTxbfJaguar_Leave(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8192E)
|
||||
HalTxbf8192E_Leave(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
HalTxbf8814A_Leave(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8822B)
|
||||
HalTxbf8822B_Leave(pDM_Odm, Idx);
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
halComTxbf_FwNdpaWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#else
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#endif
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
u1Byte Idx = pTxbfInfo->NdpaIdx;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821))
|
||||
HalTxbfJaguar_FwTxBF(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8192E)
|
||||
HalTxbf8192E_FwTxBF(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
HalTxbf8814A_FwTxBF(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8822B)
|
||||
HalTxbf8822B_FwTxBF(pDM_Odm, Idx);
|
||||
}
|
||||
|
||||
VOID
|
||||
halComTxbf_ClkWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#else
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8812)
|
||||
HalTxbfJaguar_Clk_8812A(pDM_Odm);
|
||||
}
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
halComTxbf_RateWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#else
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#endif
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
u1Byte BW = pTxbfInfo->BW;
|
||||
u1Byte Rate = pTxbfInfo->Rate;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8812)
|
||||
HalTxbf8812A_setNDPArate(pDM_Odm, BW, Rate);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8192E)
|
||||
HalTxbf8192E_setNDPArate(pDM_Odm, BW, Rate);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
HalTxbf8814A_setNDPArate(pDM_Odm, BW, Rate);
|
||||
|
||||
}
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
halComTxbf_FwNdpaTimerCallback(
|
||||
IN PRT_TIMER pTimer
|
||||
)
|
||||
{
|
||||
|
||||
PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (*pDM_Odm->pbFwDwRsvdPageInProgress)
|
||||
ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5);
|
||||
else
|
||||
PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
VOID
|
||||
halComTxbf_StatusWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#else
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#endif
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
u1Byte Idx = pTxbfInfo->TXBFIdx;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821))
|
||||
HalTxbfJaguar_Status(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8192E)
|
||||
HalTxbf8192E_Status(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
HalTxbf8814A_Status(pDM_Odm, Idx);
|
||||
else if (pDM_Odm->SupportICType & ODM_RTL8822B)
|
||||
HalTxbf8822B_Status(pDM_Odm, Idx);
|
||||
}
|
||||
|
||||
VOID
|
||||
halComTxbf_ResetTxPathWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#else
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#endif
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
u1Byte Idx = pTxbfInfo->TXBFIdx;
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
HalTxbf8814A_ResetTxPath(pDM_Odm, Idx);
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
halComTxbf_GetTxRateWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
#else
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#endif
|
||||
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
HalTxbf8814A_GetTxRate(pDM_Odm);
|
||||
}
|
||||
|
||||
|
||||
BOOLEAN
|
||||
HalComTxbf_Set(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte setType,
|
||||
IN PVOID pInBuf
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pu1Byte pU1Tmp=(pu1Byte)pInBuf;
|
||||
PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] setType = 0x%X\n", __func__, setType));
|
||||
|
||||
switch(setType){
|
||||
case TXBF_SET_SOUNDING_ENTER:
|
||||
pTxbfInfo->TXBFIdx = *pU1Tmp;
|
||||
phydm_beamformSetSoundingEnter(pDM_Odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_LEAVE:
|
||||
pTxbfInfo->TXBFIdx = *pU1Tmp;
|
||||
phydm_beamformSetSoundingLeave(pDM_Odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_RATE:
|
||||
pTxbfInfo->BW = pU1Tmp[0];
|
||||
pTxbfInfo->Rate = pU1Tmp[1];
|
||||
phydm_beamformSetSoundingRate(pDM_Odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_STATUS:
|
||||
pTxbfInfo->TXBFIdx = *pU1Tmp;
|
||||
phydm_beamformSetSoundingStatus(pDM_Odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_FW_NDPA:
|
||||
pTxbfInfo->NdpaIdx = *pU1Tmp;
|
||||
phydm_beamformSetSoundingFwNdpa(pDM_Odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_CLK:
|
||||
phydm_beamformSetSoundingClk(pDM_Odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_TX_PATH_RESET:
|
||||
pTxbfInfo->TXBFIdx = *pU1Tmp;
|
||||
phydm_beamformSetResetTxPath(pDM_Odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_GET_TX_RATE:
|
||||
phydm_beamformSetGetTxRate(pDM_Odm);
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
BOOLEAN
|
||||
HalComTxbf_Get(
|
||||
IN PADAPTER Adapter,
|
||||
IN u1Byte getType,
|
||||
OUT PVOID pOutBuf
|
||||
)
|
||||
{
|
||||
PHAL_DATA_TYPE pHalData=GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
|
||||
PBOOLEAN pBoolean=(PBOOLEAN)pOutBuf;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (getType == TXBF_GET_EXPLICIT_BEAMFORMEE) {
|
||||
if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter))
|
||||
*pBoolean = FALSE;
|
||||
else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/
|
||||
IS_HARDWARE_TYPE_8821B(Adapter) ||
|
||||
IS_HARDWARE_TYPE_8192E(Adapter) ||
|
||||
IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter))
|
||||
*pBoolean = TRUE;
|
||||
else
|
||||
*pBoolean = FALSE;
|
||||
} else if (getType == TXBF_GET_EXPLICIT_BEAMFORMER) {
|
||||
if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter))
|
||||
*pBoolean = FALSE;
|
||||
else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/
|
||||
IS_HARDWARE_TYPE_8821B(Adapter) ||
|
||||
IS_HARDWARE_TYPE_8192E(Adapter) ||
|
||||
IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) {
|
||||
if(pHalData->RF_Type == RF_2T2R || pHalData->RF_Type == RF_3T3R)
|
||||
*pBoolean = TRUE;
|
||||
else
|
||||
*pBoolean = FALSE;
|
||||
} else
|
||||
*pBoolean = FALSE;
|
||||
} else if (getType == TXBF_GET_MU_MIMO_STA) {
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
|
||||
if (IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter))
|
||||
*pBoolean = TRUE;
|
||||
else
|
||||
#endif
|
||||
*pBoolean = FALSE;
|
||||
|
||||
|
||||
} else if (getType == TXBF_GET_MU_MIMO_AP) {
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
if (IS_HARDWARE_TYPE_8822B(Adapter))
|
||||
*pBoolean = TRUE;
|
||||
else
|
||||
#endif
|
||||
*pBoolean = FALSE;
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
#ifndef __HAL_COM_TXBF_H__
|
||||
#define __HAL_COM_TXBF_H__
|
||||
|
||||
/*
|
||||
typedef BOOLEAN
|
||||
(*TXBF_GET)(
|
||||
IN PVOID pAdapter,
|
||||
IN u1Byte getType,
|
||||
OUT PVOID pOutBuf
|
||||
);
|
||||
|
||||
typedef BOOLEAN
|
||||
(*TXBF_SET)(
|
||||
IN PVOID pAdapter,
|
||||
IN u1Byte setType,
|
||||
OUT PVOID pInBuf
|
||||
);
|
||||
*/
|
||||
|
||||
typedef enum _TXBF_SET_TYPE{
|
||||
TXBF_SET_SOUNDING_ENTER,
|
||||
TXBF_SET_SOUNDING_LEAVE,
|
||||
TXBF_SET_SOUNDING_RATE,
|
||||
TXBF_SET_SOUNDING_STATUS,
|
||||
TXBF_SET_SOUNDING_FW_NDPA,
|
||||
TXBF_SET_SOUNDING_CLK,
|
||||
TXBF_SET_TX_PATH_RESET,
|
||||
TXBF_SET_GET_TX_RATE
|
||||
}TXBF_SET_TYPE,*PTXBF_SET_TYPE;
|
||||
|
||||
|
||||
typedef enum _TXBF_GET_TYPE{
|
||||
TXBF_GET_EXPLICIT_BEAMFORMEE,
|
||||
TXBF_GET_EXPLICIT_BEAMFORMER,
|
||||
TXBF_GET_MU_MIMO_STA,
|
||||
TXBF_GET_MU_MIMO_AP
|
||||
}TXBF_GET_TYPE,*PTXBF_GET_TYPE;
|
||||
|
||||
|
||||
|
||||
//2 HAL TXBF related
|
||||
typedef struct _HAL_TXBF_INFO {
|
||||
u1Byte TXBFIdx;
|
||||
u1Byte NdpaIdx;
|
||||
u1Byte BW;
|
||||
u1Byte Rate;
|
||||
|
||||
RT_TIMER Txbf_FwNdpaTimer;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_WORK_ITEM Txbf_EnterWorkItem;
|
||||
RT_WORK_ITEM Txbf_LeaveWorkItem;
|
||||
RT_WORK_ITEM Txbf_FwNdpaWorkItem;
|
||||
RT_WORK_ITEM Txbf_ClkWorkItem;
|
||||
RT_WORK_ITEM Txbf_StatusWorkItem;
|
||||
RT_WORK_ITEM Txbf_RateWorkItem;
|
||||
RT_WORK_ITEM Txbf_ResetTxPathWorkItem;
|
||||
RT_WORK_ITEM Txbf_GetTxRateWorkItem;
|
||||
#endif
|
||||
|
||||
} HAL_TXBF_INFO, *PHAL_TXBF_INFO;
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
VOID
|
||||
halComTxbf_beamformInit(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_ConfigGtab(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_EnterWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_LeaveWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_FwNdpaWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_ClkWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_ResetTxPathWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_GetTxRateWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_RateWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_FwNdpaTimerCallback(
|
||||
IN PRT_TIMER pTimer
|
||||
);
|
||||
|
||||
VOID
|
||||
halComTxbf_StatusWorkItemCallback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN PADAPTER Adapter
|
||||
#else
|
||||
IN PVOID pDM_VOID
|
||||
#endif
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
HalComTxbf_Set(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte setType,
|
||||
IN PVOID pInBuf
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
HalComTxbf_Get(
|
||||
IN PADAPTER Adapter,
|
||||
IN u1Byte getType,
|
||||
OUT PVOID pOutBuf
|
||||
);
|
||||
|
||||
#else
|
||||
#define halComTxbf_beamformInit(pDM_VOID) NULL
|
||||
#define halComTxbf_ConfigGtab(pDM_VOID) NULL
|
||||
#define halComTxbf_EnterWorkItemCallback(_Adapter) NULL
|
||||
#define halComTxbf_LeaveWorkItemCallback(_Adapter) NULL
|
||||
#define halComTxbf_FwNdpaWorkItemCallback(_Adapter) NULL
|
||||
#define halComTxbf_ClkWorkItemCallback(_Adapter) NULL
|
||||
#define halComTxbf_RateWorkItemCallback(_Adapter) NULL
|
||||
#define halComTxbf_FwNdpaTimerCallback(_Adapter) NULL
|
||||
#define halComTxbf_StatusWorkItemCallback(_Adapter) NULL
|
||||
#define HalComTxbf_Get(_Adapter, _getType, _pOutBuf)
|
||||
|
||||
#endif
|
||||
|
||||
#endif // #ifndef __HAL_COM_TXBF_H__
|
||||
|
||||
@@ -0,0 +1,392 @@
|
||||
//============================================================
|
||||
// Description:
|
||||
//
|
||||
// This file is for 8192E TXBF mechanism
|
||||
//
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
#if (RTL8192E_SUPPORT == 1)
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_setNDPArate(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte BW,
|
||||
IN u1Byte Rate
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8192E, (Rate << 2 | BW));
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
halTxbf8192E_RfMode(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PRT_BEAMFORMING_INFO pBeamInfo
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
BOOLEAN bSelfBeamformer = FALSE;
|
||||
BOOLEAN bSelfBeamformee = FALSE;
|
||||
BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pDM_Odm->RFType == ODM_1T1R)
|
||||
return;
|
||||
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/
|
||||
|
||||
if (pBeamInfo->beamformee_su_cnt > 0) {
|
||||
/*Path_A*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/
|
||||
/*Path_B*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/
|
||||
} else {
|
||||
/*Path_A*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/
|
||||
/*Path_B*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/
|
||||
}
|
||||
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/
|
||||
|
||||
if (pBeamInfo->beamformee_su_cnt > 0) {
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x83321333);
|
||||
ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskByte3, 0xc1);
|
||||
} else
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x81121313);
|
||||
}
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
halTxbf8192E_FwTxBFCmd(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte Idx, Period0 = 0, Period1 = 0;
|
||||
u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF;
|
||||
u1Byte u1TxBFParm[3] = {0};
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
|
||||
for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) {
|
||||
if (pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
|
||||
if (Idx == 0) {
|
||||
if (pBeamInfo->BeamformeeEntry[Idx].bSound)
|
||||
PageNum0 = 0xFE;
|
||||
else
|
||||
PageNum0 = 0xFF; //stop sounding
|
||||
Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
|
||||
} else if (Idx == 1) {
|
||||
if (pBeamInfo->BeamformeeEntry[Idx].bSound)
|
||||
PageNum1 = 0xFE;
|
||||
else
|
||||
PageNum1 = 0xFF; //stop sounding
|
||||
Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
u1TxBFParm[0] = PageNum0;
|
||||
u1TxBFParm[1] = PageNum1;
|
||||
u1TxBFParm[2] = (Period1 << 4) | Period0;
|
||||
ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
|
||||
("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
halTxbf8192E_DownloadNDPA(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page;
|
||||
u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0;
|
||||
BOOLEAN bSendBeacon = FALSE;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
|
||||
/*default reseved 1 page for the IC type which is undefined.*/
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*pDM_Odm->pbFwDwRsvdPageInProgress = TRUE;
|
||||
#endif
|
||||
if (Idx == 0)
|
||||
Head_Page = 0xFE;
|
||||
else
|
||||
Head_Page = 0xFE;
|
||||
|
||||
Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy);
|
||||
|
||||
/*Set REG_CR bit 8. DMA beacon by SW.*/
|
||||
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1);
|
||||
ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp | BIT0));
|
||||
|
||||
/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
|
||||
tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2);
|
||||
ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422 & (~BIT6));
|
||||
|
||||
if (tmpReg422 & BIT6) {
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an Adapter is sending beacon.\n", __func__));
|
||||
bSendBeacon = TRUE;
|
||||
}
|
||||
|
||||
/*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, Head_Page);
|
||||
|
||||
do {
|
||||
/*Clear beacon valid check bit.*/
|
||||
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);
|
||||
ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2, (BcnValidReg | BIT0));
|
||||
|
||||
// download NDPA rsvd page.
|
||||
Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);
|
||||
|
||||
#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)
|
||||
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3);
|
||||
count = 0;
|
||||
while ((count < 20) && (u1bTmp & BIT4)) {
|
||||
count++;
|
||||
ODM_delay_us(10);
|
||||
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3);
|
||||
}
|
||||
ODM_Write1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3, u1bTmp | BIT4);
|
||||
#endif
|
||||
|
||||
/*check rsvd page download OK.*/
|
||||
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);
|
||||
count = 0;
|
||||
while (!(BcnValidReg & BIT0) && count < 20) {
|
||||
count++;
|
||||
ODM_delay_us(10);
|
||||
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);
|
||||
}
|
||||
DLBcnCount++;
|
||||
} while (!(BcnValidReg & BIT0) && DLBcnCount < 5);
|
||||
|
||||
if (!(BcnValidReg & BIT0))
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__));
|
||||
|
||||
/*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, TxPageBndy);
|
||||
|
||||
/*To make sure that if there exists an adapter which would like to send beacon.*/
|
||||
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
|
||||
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
|
||||
/*the beacon cannot be sent by HW.*/
|
||||
/*2010.06.23. Added by tynli.*/
|
||||
if (bSendBeacon)
|
||||
ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422);
|
||||
|
||||
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
|
||||
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
|
||||
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1);
|
||||
ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp & (~BIT0)));
|
||||
|
||||
pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*pDM_Odm->pbFwDwRsvdPageInProgress = FALSE;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_Enter(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte BFerBFeeIdx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte i = 0;
|
||||
u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;
|
||||
u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);
|
||||
u4Byte CSI_Param;
|
||||
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
|
||||
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
|
||||
RT_BEAMFORMER_ENTRY BeamformerEntry;
|
||||
u2Byte STAid = 0;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
halTxbf8192E_RfMode(pDM_Odm, pBeamformingInfo);
|
||||
|
||||
if (pDM_Odm->RFType == ODM_2T2R)
|
||||
ODM_Write4Byte(pDM_Odm, 0xd80, 0x00000000); /*Nc =2*/
|
||||
|
||||
if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {
|
||||
BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];
|
||||
|
||||
/*Sounding protocol control*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xCB);
|
||||
|
||||
/*MAC address/Partial AID of Beamformer*/
|
||||
if (BFerIdx == 0) {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), BeamformerEntry.MacAddr[i]);
|
||||
} else {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), BeamformerEntry.MacAddr[i]);
|
||||
}
|
||||
|
||||
/*CSI report parameters of Beamformer Default use Nc = 2*/
|
||||
CSI_Param = 0x03090309;
|
||||
|
||||
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8192E, CSI_Param);
|
||||
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8192E, CSI_Param);
|
||||
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8192E, CSI_Param);
|
||||
|
||||
/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E+3, 0x50);
|
||||
|
||||
}
|
||||
|
||||
if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {
|
||||
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];
|
||||
|
||||
if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
|
||||
STAid = BeamformeeEntry.MacId;
|
||||
else
|
||||
STAid = BeamformeeEntry.P_AID;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], STAid=0x%X\n", __func__, STAid));
|
||||
|
||||
/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
|
||||
if (BFeeIdx == 0) {
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, STAid);
|
||||
ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3) | BIT4 | BIT6 | BIT7);
|
||||
} else
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, STAid | BIT12 | BIT14 | BIT15);
|
||||
|
||||
/*CSI report parameters of Beamformee*/
|
||||
if (BFeeIdx == 0) {
|
||||
/*Get BIT24 & BIT25*/
|
||||
u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3;
|
||||
|
||||
ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60);
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, STAid | BIT9);
|
||||
} else {
|
||||
/*Set BIT25*/
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, STAid | 0xE200);
|
||||
}
|
||||
phydm_Beamforming_Notify(pDM_Odm);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_Leave(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
|
||||
halTxbf8192E_RfMode(pDM_Odm, pBeamInfo);
|
||||
|
||||
/* Clear P_AID of Beamformee
|
||||
* Clear MAC addresss of Beamformer
|
||||
* Clear Associated Bfmee Sel
|
||||
*/
|
||||
if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE)
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xC8);
|
||||
|
||||
if (Idx == 0) {
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, 0);
|
||||
ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
|
||||
} else {
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2) & 0xF000);
|
||||
ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60);
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d\n", __func__, Idx));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_Status(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u2Byte BeamCtrlVal;
|
||||
u4Byte BeamCtrlReg;
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx];
|
||||
|
||||
if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
|
||||
BeamCtrlVal = BeamformEntry.MacId;
|
||||
else
|
||||
BeamCtrlVal = BeamformEntry.P_AID;
|
||||
|
||||
if (Idx == 0)
|
||||
BeamCtrlReg = REG_TXBF_CTRL_8192E;
|
||||
else {
|
||||
BeamCtrlReg = REG_TXBF_CTRL_8192E+2;
|
||||
BeamCtrlVal |= BIT12 | BIT14 | BIT15;
|
||||
}
|
||||
|
||||
if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) {
|
||||
if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20)
|
||||
BeamCtrlVal |= BIT9;
|
||||
else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40)
|
||||
BeamCtrlVal |= BIT10;
|
||||
} else
|
||||
BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11);
|
||||
|
||||
ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d BeamCtrlReg %x BeamCtrlVal %x\n", __func__, Idx, BeamCtrlReg, BeamCtrlVal));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_FwTxBF(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING)
|
||||
halTxbf8192E_DownloadNDPA(pDM_Odm, Idx);
|
||||
|
||||
halTxbf8192E_FwTxBFCmd(pDM_Odm);
|
||||
}
|
||||
|
||||
#endif /* #if (RTL8192E_SUPPORT == 1)*/
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
#ifndef __HAL_TXBF_8192E_H__
|
||||
#define __HAL_TXBF_8192E_H__
|
||||
|
||||
#if (RTL8192E_SUPPORT == 1)
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_setNDPArate(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte BW,
|
||||
IN u1Byte Rate
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_Enter(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_Leave(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_Status(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8192E_FwTxBF(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
#else
|
||||
|
||||
#define HalTxbf8192E_setNDPArate(pDM_VOID, BW, Rate)
|
||||
#define HalTxbf8192E_Enter(pDM_VOID, Idx)
|
||||
#define HalTxbf8192E_Leave(pDM_VOID, Idx)
|
||||
#define HalTxbf8192E_Status(pDM_VOID, Idx)
|
||||
#define HalTxbf8192E_FwTxBF(pDM_VOID, Idx)
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define HalTxbf8192E_setNDPArate(pDM_VOID, BW, Rate)
|
||||
#define HalTxbf8192E_Enter(pDM_VOID, Idx)
|
||||
#define HalTxbf8192E_Leave(pDM_VOID, Idx)
|
||||
#define HalTxbf8192E_Status(pDM_VOID, Idx)
|
||||
#define HalTxbf8192E_FwTxBF(pDM_VOID, Idx)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,677 @@
|
||||
//============================================================
|
||||
// Description:
|
||||
//
|
||||
// This file is for 8814A TXBF mechanism
|
||||
//
|
||||
//============================================================
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_setNDPArate(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte BW,
|
||||
IN u1Byte Rate
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8814A, BW);
|
||||
ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8814A, (u1Byte) Rate);
|
||||
|
||||
}
|
||||
|
||||
#define PHYDM_MEMORY_MAP_BUF_READ 0x8000
|
||||
#define PHYDM_CTRL_INFO_PAGE 0x660
|
||||
|
||||
VOID
|
||||
phydm_DataRate_8814A(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
IN u1Byte macId,
|
||||
OUT pu4Byte data,
|
||||
IN u1Byte dataLen
|
||||
)
|
||||
{
|
||||
u1Byte i = 0;
|
||||
u2Byte XReadDataAddr = 0;
|
||||
|
||||
ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);
|
||||
XReadDataAddr = PHYDM_MEMORY_MAP_BUF_READ + macId*32; /*Ctrl Info: 32Bytes for each macid(n)*/
|
||||
|
||||
if ((XReadDataAddr < PHYDM_MEMORY_MAP_BUF_READ) || (XReadDataAddr > 0x8FFF)) {
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("XReadDataAddr(0x%x) is not correct!\n", XReadDataAddr));
|
||||
return;
|
||||
}
|
||||
|
||||
/* Read data */
|
||||
for (i = 0; i < dataLen; i++)
|
||||
*(data+i) = ODM_Read2Byte(pDM_Odm, XReadDataAddr+i);
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_GetTxRate(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
PRT_BEAMFORMEE_ENTRY pEntry;
|
||||
u4Byte TxRptData = 0;
|
||||
u1Byte DataRate = 0xFF;
|
||||
|
||||
pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]);
|
||||
|
||||
phydm_DataRate_8814A(pDM_Odm, (u1Byte)pEntry->MacId, &TxRptData, 1);
|
||||
DataRate = (u1Byte)TxRptData;
|
||||
DataRate &= bMask7bits; /*Bit7 indicates SGI*/
|
||||
|
||||
pDM_Odm->TxBfDataRate = DataRate;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] pDM_Odm->TxBfDataRate = 0x%x\n", __func__, pDM_Odm->TxBfDataRate));
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_ResetTxPath(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
||||
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
|
||||
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
|
||||
u1Byte Nr_index = 0, txSS = 0;
|
||||
|
||||
if (idx < BEAMFORMEE_ENTRY_NUM)
|
||||
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx];
|
||||
else
|
||||
return;
|
||||
|
||||
if ((pDM_Odm->LastUSBHub) != (*pDM_Odm->HubUsbMode)) {
|
||||
Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer);
|
||||
|
||||
if (*pDM_Odm->HubUsbMode == 2) {
|
||||
if (pDM_Odm->RFType == ODM_4T4R)
|
||||
txSS = 0xf;
|
||||
else if (pDM_Odm->RFType == ODM_3T3R)
|
||||
txSS = 0xe;
|
||||
else
|
||||
txSS = 0x6;
|
||||
} else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/
|
||||
txSS = 0x6;
|
||||
else
|
||||
txSS = 0x6;
|
||||
|
||||
if (txSS == 0xf) {
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f);
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0);
|
||||
} else if (txSS == 0xe) {
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e);
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0);
|
||||
} else if (txSS == 0x6) {
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936);
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360);
|
||||
}
|
||||
|
||||
if (idx == 0) {
|
||||
switch (Nr_index) {
|
||||
case 0:
|
||||
break;
|
||||
|
||||
case 1: /*Nsts = 2 BC*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/
|
||||
break;
|
||||
|
||||
case 2: /*Nsts = 3 BCD*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/
|
||||
break;
|
||||
|
||||
default: /*Nr>3, same as Case 3*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (Nr_index) {
|
||||
case 0:
|
||||
break;
|
||||
|
||||
case 1: /*Nsts = 2 BC*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/
|
||||
break;
|
||||
|
||||
case 2: /*Nsts = 3 BCD*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/
|
||||
break;
|
||||
|
||||
default: /*Nr>3, same as Case 3*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode;
|
||||
} else
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
u1Byte
|
||||
halTxbf8814A_GetNtx(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte Ntx = 0, txSS = 3;
|
||||
|
||||
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
||||
txSS = *pDM_Odm->HubUsbMode;
|
||||
#endif
|
||||
if (txSS == 3 || txSS == 2) {
|
||||
if (pDM_Odm->RFType == ODM_4T4R)
|
||||
Ntx = 3;
|
||||
else if (pDM_Odm->RFType == ODM_3T3R)
|
||||
Ntx = 2;
|
||||
else
|
||||
Ntx = 1;
|
||||
} else if (txSS == 1) /*USB 2.0 always 2Tx*/
|
||||
Ntx = 1;
|
||||
else
|
||||
Ntx = 1;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Ntx = %d\n", __func__, Ntx));
|
||||
return Ntx;
|
||||
}
|
||||
|
||||
u1Byte
|
||||
halTxbf8814A_GetNrx(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte Nrx = 0;
|
||||
|
||||
if (pDM_Odm->RFType == ODM_4T4R)
|
||||
Nrx = 3;
|
||||
else if (pDM_Odm->RFType == ODM_3T3R)
|
||||
Nrx = 2;
|
||||
else if (pDM_Odm->RFType == ODM_2T2R)
|
||||
Nrx = 1;
|
||||
else if (pDM_Odm->RFType == ODM_2T3R)
|
||||
Nrx = 2;
|
||||
else if (pDM_Odm->RFType == ODM_2T4R)
|
||||
Nrx = 3;
|
||||
else if (pDM_Odm->RFType == ODM_1T1R)
|
||||
Nrx = 0;
|
||||
else if (pDM_Odm->RFType == ODM_1T2R)
|
||||
Nrx = 1;
|
||||
else
|
||||
Nrx = 0;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Nrx = %d\n", __func__, Nrx));
|
||||
return Nrx;
|
||||
}
|
||||
|
||||
VOID
|
||||
halTxbf8814A_RfMode(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PRT_BEAMFORMING_INFO pBeamformingInfo,
|
||||
IN u1Byte idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte i, Nr_index = 0;
|
||||
u1Byte txSS = 3; /*default use 3 Tx*/
|
||||
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
|
||||
|
||||
if (idx < BEAMFORMEE_ENTRY_NUM)
|
||||
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx];
|
||||
else
|
||||
return;
|
||||
|
||||
Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer);
|
||||
|
||||
if (pDM_Odm->RFType == ODM_1T1R)
|
||||
return;
|
||||
|
||||
for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) {
|
||||
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x1);
|
||||
/*RF Mode table write enable*/
|
||||
}
|
||||
|
||||
if (pBeamformingInfo->beamformee_su_cnt > 0) {
|
||||
for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) {
|
||||
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableAddr, 0xfffff, 0x18000);
|
||||
/*Select RX mode*/
|
||||
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData0, 0xfffff, 0xBE77F);
|
||||
/*Set Table data*/
|
||||
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData1, 0xfffff, 0x226BF);
|
||||
/*Enable TXIQGEN in RX mode*/
|
||||
}
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF);
|
||||
/*Enable TXIQGEN in RX mode*/
|
||||
}
|
||||
|
||||
for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) {
|
||||
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x0);
|
||||
/*RF Mode table write disable*/
|
||||
}
|
||||
|
||||
if (pBeamformingInfo->beamformee_su_cnt > 0) {
|
||||
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
||||
pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode;
|
||||
txSS = *pDM_Odm->HubUsbMode;
|
||||
#endif
|
||||
if (txSS == 3 || txSS == 2) {
|
||||
if (pDM_Odm->RFType == ODM_4T4R)
|
||||
txSS = 0xf;
|
||||
else if (pDM_Odm->RFType == ODM_3T3R)
|
||||
txSS = 0xe;
|
||||
else
|
||||
txSS = 0x6;
|
||||
} else if (txSS == 1) /*USB 2.0 always 2Tx*/
|
||||
txSS = 0x6;
|
||||
else
|
||||
txSS = 0x6;
|
||||
|
||||
if (txSS == 0xf) {
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f);
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0);
|
||||
} else if (txSS == 0xe) {
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e);
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0);
|
||||
} else if (txSS == 0x6) {
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936);
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360);
|
||||
}
|
||||
|
||||
/*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT28 | BIT29, 0x2); /*enable BB TxBF ant mapping register*/
|
||||
|
||||
if (idx == 0) {
|
||||
switch (Nr_index) {
|
||||
case 0:
|
||||
break;
|
||||
|
||||
case 1: /*Nsts = 2 BC*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/
|
||||
break;
|
||||
|
||||
case 2: /*Nsts = 3 BCD*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/
|
||||
break;
|
||||
|
||||
default: /*Nr>3, same as Case 3*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/
|
||||
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (Nr_index) {
|
||||
case 0:
|
||||
break;
|
||||
|
||||
case 1: /*Nsts = 2 BC*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/
|
||||
break;
|
||||
|
||||
case 2: /*Nsts = 3 BCD*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/
|
||||
break;
|
||||
|
||||
default: /*Nr>3, same as Case 3*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if ((pBeamformingInfo->beamformee_su_cnt == 0) && (pBeamformingInfo->beamformer_su_cnt == 0)) {
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x932); /*set TxPath selection for 8814a BFer bug refine*/
|
||||
ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e9360);
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
VOID
|
||||
halTxbf8814A_DownloadNDPA(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte u1bTmp = 0, tmpReg422 = 0;
|
||||
u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0;
|
||||
u2Byte Head_Page = 0x7FE;
|
||||
BOOLEAN bSendBeacon = FALSE;
|
||||
u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*pDM_Odm->pbFwDwRsvdPageInProgress = TRUE;
|
||||
#endif
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy);
|
||||
|
||||
/*Set REG_CR bit 8. DMA beacon by SW.*/
|
||||
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1);
|
||||
ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp | BIT0));
|
||||
|
||||
|
||||
/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
|
||||
tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2);
|
||||
ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422 & (~BIT6));
|
||||
|
||||
if (tmpReg422 & BIT6) {
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an Adapter is sending beacon.\n", __func__));
|
||||
bSendBeacon = TRUE;
|
||||
}
|
||||
|
||||
/*0x204[11:0] Beacon Head for TXDMA*/
|
||||
ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, Head_Page);
|
||||
|
||||
do {
|
||||
/*Clear beacon valid check bit.*/
|
||||
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1);
|
||||
ODM_Write1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (BcnValidReg | BIT7));
|
||||
|
||||
/*download NDPA rsvd page.*/
|
||||
if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)
|
||||
Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE);
|
||||
else
|
||||
Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);
|
||||
|
||||
/*check rsvd page download OK.*/
|
||||
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1);
|
||||
count = 0;
|
||||
while (!(BcnValidReg & BIT7) && count < 20) {
|
||||
count++;
|
||||
ODM_delay_ms(10);
|
||||
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 2);
|
||||
}
|
||||
DLBcnCount++;
|
||||
} while (!(BcnValidReg & BIT7) && DLBcnCount < 5);
|
||||
|
||||
if (!(BcnValidReg & BIT7))
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__));
|
||||
|
||||
/*0x204[11:0] Beacon Head for TXDMA*/
|
||||
ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy);
|
||||
|
||||
/*To make sure that if there exists an adapter which would like to send beacon.*/
|
||||
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
|
||||
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
|
||||
/*the beacon cannot be sent by HW.*/
|
||||
/*2010.06.23. Added by tynli.*/
|
||||
if (bSendBeacon)
|
||||
ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422);
|
||||
|
||||
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
|
||||
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
|
||||
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1);
|
||||
ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp & (~BIT0)));
|
||||
|
||||
pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*pDM_Odm->pbFwDwRsvdPageInProgress = FALSE;
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
halTxbf8814A_FwTxBFCmd(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte Idx, Period = 0;
|
||||
u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF;
|
||||
u1Byte u1TxBFParm[3] = {0};
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
|
||||
for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) {
|
||||
if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
|
||||
if (pBeamInfo->BeamformeeEntry[Idx].bSound) {
|
||||
PageNum0 = 0xFE;
|
||||
PageNum1 = 0x07;
|
||||
Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
|
||||
} else if (PageNum0 == 0xFF) {
|
||||
PageNum0 = 0xFF; /*stop sounding*/
|
||||
PageNum1 = 0x0F;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
u1TxBFParm[0] = PageNum0;
|
||||
u1TxBFParm[1] = PageNum1;
|
||||
u1TxBFParm[2] = Period;
|
||||
ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
|
||||
("[%s] PageNum0 = %d, PageNum1 = %d Period = %d\n", __func__, PageNum0, PageNum1, Period));
|
||||
}
|
||||
#endif
|
||||
VOID
|
||||
HalTxbf8814A_Enter(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte BFerBFeeIdx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte i = 0;
|
||||
u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;
|
||||
u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);
|
||||
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
|
||||
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
|
||||
RT_BEAMFORMER_ENTRY BeamformerEntry;
|
||||
u2Byte STAid = 0, CSI_Param = 0;
|
||||
u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerIdx, BFeeIdx));
|
||||
ODM_SetMACReg(pDM_Odm, REG_SND_PTCL_CTRL_8814A, bMaskByte1 | bMaskByte2, 0x0202);
|
||||
|
||||
if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {
|
||||
BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];
|
||||
/*Sounding protocol control*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xDB);
|
||||
|
||||
/*MAC address/Partial AID of Beamformer*/
|
||||
if (BFerIdx == 0) {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), BeamformerEntry.MacAddr[i]);
|
||||
} else {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), BeamformerEntry.MacAddr[i]);
|
||||
}
|
||||
|
||||
/*CSI report parameters of Beamformer*/
|
||||
Nc_index = halTxbf8814A_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/
|
||||
Nr_index = BeamformerEntry.NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/
|
||||
|
||||
grouping = 0;
|
||||
|
||||
/*for ac = 1, for n = 3*/
|
||||
if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU)
|
||||
codebookinfo = 1;
|
||||
else if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT)
|
||||
codebookinfo = 3;
|
||||
|
||||
coefficientsize = 3;
|
||||
|
||||
CSI_Param = (u2Byte)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (Nr_index << 3) | (Nc_index));
|
||||
|
||||
if (BFerIdx == 0)
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, CSI_Param);
|
||||
else
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, CSI_Param);
|
||||
/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);
|
||||
|
||||
}
|
||||
|
||||
if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {
|
||||
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];
|
||||
|
||||
halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx);
|
||||
|
||||
if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
|
||||
STAid = BeamformeeEntry.MacId;
|
||||
else
|
||||
STAid = BeamformeeEntry.P_AID;
|
||||
|
||||
/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
|
||||
if (BFeeIdx == 0) {
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, STAid);
|
||||
ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7);
|
||||
} else
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, STAid | BIT14 | BIT15 | BIT12);
|
||||
|
||||
/*CSI report parameters of Beamformee*/
|
||||
if (BFeeIdx == 0) {
|
||||
/*Get BIT24 & BIT25*/
|
||||
u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
|
||||
|
||||
ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, STAid | BIT9);
|
||||
} else
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, STAid | 0xE200); /*Set BIT25*/
|
||||
|
||||
phydm_Beamforming_Notify(pDM_Odm);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_Leave(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
|
||||
RT_BEAMFORMER_ENTRY BeamformerEntry;
|
||||
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
|
||||
|
||||
if (Idx < BEAMFORMER_ENTRY_NUM) {
|
||||
BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx];
|
||||
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx];
|
||||
} else
|
||||
return;
|
||||
|
||||
/*Clear P_AID of Beamformee*/
|
||||
/*Clear MAC address of Beamformer*/
|
||||
/*Clear Associated Bfmee Sel*/
|
||||
|
||||
if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xD8);
|
||||
if (Idx == 0) {
|
||||
ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, 0);
|
||||
} else {
|
||||
ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);
|
||||
}
|
||||
}
|
||||
|
||||
if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
|
||||
halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, Idx);
|
||||
if (Idx == 0) {
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, 0x0);
|
||||
ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7);
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);
|
||||
} else {
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT14 | BIT15 | BIT12);
|
||||
|
||||
ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_Status(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u2Byte BeamCtrlVal, tmpVal;
|
||||
u4Byte BeamCtrlReg;
|
||||
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
|
||||
RT_BEAMFORMEE_ENTRY BeamformEntry;
|
||||
|
||||
if (Idx < BEAMFORMEE_ENTRY_NUM)
|
||||
BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx];
|
||||
else
|
||||
return;
|
||||
|
||||
if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
|
||||
BeamCtrlVal = BeamformEntry.MacId;
|
||||
else
|
||||
BeamCtrlVal = BeamformEntry.P_AID;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, BeamformEntry.BeamformEntryState));
|
||||
|
||||
if (Idx == 0)
|
||||
BeamCtrlReg = REG_TXBF_CTRL_8814A;
|
||||
else {
|
||||
BeamCtrlReg = REG_TXBF_CTRL_8814A + 2;
|
||||
BeamCtrlVal |= BIT12 | BIT14 | BIT15;
|
||||
}
|
||||
|
||||
if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamformingInfo->applyVmatrix == TRUE)) {
|
||||
if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20)
|
||||
BeamCtrlVal |= BIT9;
|
||||
else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40)
|
||||
BeamCtrlVal |= (BIT9 | BIT10);
|
||||
else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80)
|
||||
BeamCtrlVal |= (BIT9 | BIT10 | BIT11);
|
||||
} else {
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__));
|
||||
BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11);
|
||||
}
|
||||
|
||||
ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal);
|
||||
/*disable NDP packet use beamforming */
|
||||
tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8814A);
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, tmpVal | BIT15);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_FwTxBF(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
#if 0
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING)
|
||||
halTxbf8814A_DownloadNDPA(pDM_Odm, Idx);
|
||||
|
||||
halTxbf8814A_FwTxBFCmd(pDM_Odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (RTL8814A_SUPPORT == 1)*/
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,83 @@
|
||||
#ifndef __HAL_TXBF_8814A_H__
|
||||
#define __HAL_TXBF_8814A_H__
|
||||
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_setNDPArate(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte BW,
|
||||
IN u1Byte Rate
|
||||
);
|
||||
|
||||
u1Byte
|
||||
halTxbf8814A_GetNtx(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_Enter(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_Leave(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_Status(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_ResetTxPath(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_GetTxRate(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTxbf8814A_FwTxBF(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
#else
|
||||
|
||||
#define HalTxbf8814A_setNDPArate(pDM_VOID, BW, Rate)
|
||||
#define halTxbf8814A_GetNtx(pDM_VOID) 0
|
||||
#define HalTxbf8814A_Enter(pDM_VOID, Idx)
|
||||
#define HalTxbf8814A_Leave(pDM_VOID, Idx)
|
||||
#define HalTxbf8814A_Status(pDM_VOID, Idx)
|
||||
#define HalTxbf8814A_ResetTxPath(pDM_VOID, Idx)
|
||||
#define HalTxbf8814A_GetTxRate(pDM_VOID)
|
||||
#define HalTxbf8814A_FwTxBF(pDM_VOID, Idx)
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define HalTxbf8814A_setNDPArate(pDM_VOID, BW, Rate)
|
||||
#define halTxbf8814A_GetNtx(pDM_VOID) 0
|
||||
#define HalTxbf8814A_Enter(pDM_VOID, Idx)
|
||||
#define HalTxbf8814A_Leave(pDM_VOID, Idx)
|
||||
#define HalTxbf8814A_Status(pDM_VOID, Idx)
|
||||
#define HalTxbf8814A_ResetTxPath(pDM_VOID, Idx)
|
||||
#define HalTxbf8814A_GetTxRate(pDM_VOID)
|
||||
#define HalTxbf8814A_FwTxBF(pDM_VOID, Idx)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,87 @@
|
||||
#ifndef __HAL_TXBF_8822B_H__
|
||||
#define __HAL_TXBF_8822B_H__
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
VOID
|
||||
HalTxbf8822B_Init(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTxbf8822B_Enter(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8822B_Leave(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbf8822B_Status(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTxbf8822B_ConfigGtab(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTxbf8822B_FwTxBF(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
#else
|
||||
#define HalTxbf8822B_Init(pDM_VOID)
|
||||
#define HalTxbf8822B_Enter(pDM_VOID, Idx)
|
||||
#define HalTxbf8822B_Leave(pDM_VOID, Idx)
|
||||
#define HalTxbf8822B_Status(pDM_VOID, Idx)
|
||||
#define HalTxbf8822B_FwTxBF(pDM_VOID, Idx)
|
||||
#define HalTxbf8822B_ConfigGtab(pDM_VOID)
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_BB_TXBF_API))
|
||||
VOID
|
||||
phydm_8822btxbf_rfmode(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte SUBFeeCnt,
|
||||
IN u1Byte MUBFeeCnt
|
||||
);
|
||||
|
||||
VOID
|
||||
phydm_8822b_sutxbfer_workaroud(
|
||||
IN PVOID pDM_VOID,
|
||||
IN BOOLEAN EnableSUBfer,
|
||||
IN u1Byte Nc,
|
||||
IN u1Byte Nr,
|
||||
IN u1Byte Ng,
|
||||
IN u1Byte CB,
|
||||
IN u1Byte BW,
|
||||
IN BOOLEAN isVHT
|
||||
);
|
||||
|
||||
#else
|
||||
#define phydm_8822btxbf_rfmode(pDM_VOID, SUBFeeCnt, MUBFeeCnt)
|
||||
#define phydm_8822b_sutxbfer_workaroud(pDM_VOID, EnableSUBfer, Nc, Nr, Ng, CB, BW, isVHT)
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define HalTxbf8822B_Init(pDM_VOID)
|
||||
#define HalTxbf8822B_Enter(pDM_VOID, Idx)
|
||||
#define HalTxbf8822B_Leave(pDM_VOID, Idx)
|
||||
#define HalTxbf8822B_Status(pDM_VOID, Idx)
|
||||
#define HalTxbf8822B_FwTxBF(pDM_VOID, Idx)
|
||||
#define HalTxbf8822B_ConfigGtab(pDM_VOID)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
||||
#ifndef __HAL_TXBF_INTERFACE_H__
|
||||
#define __HAL_TXBF_INTERFACE_H__
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
VOID
|
||||
Beamforming_GidPAid(
|
||||
PADAPTER Adapter,
|
||||
PRT_TCB pTcb
|
||||
);
|
||||
|
||||
RT_STATUS
|
||||
Beamforming_GetReportFrame(
|
||||
IN PADAPTER Adapter,
|
||||
IN PRT_RFD pRfd,
|
||||
IN POCTET_STRING pPduOS
|
||||
);
|
||||
|
||||
VOID
|
||||
Beamforming_GetNDPAFrame(
|
||||
IN PVOID pDM_VOID,
|
||||
IN OCTET_STRING pduOS
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendFWHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendFWVHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN u2Byte AID,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendSWVHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN u2Byte AID,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendSWHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
#if (SUPPORT_MU_BF == 1)
|
||||
RT_STATUS
|
||||
Beamforming_GetVHTGIDMgntFrame(
|
||||
IN PADAPTER Adapter,
|
||||
IN PRT_RFD pRfd,
|
||||
IN POCTET_STRING pPduOS
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendSWVHTGIDMgntFrame(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendSWVHTBFReportPoll(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN BOOLEAN bFinalPoll
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendSWVHTMUNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
#else
|
||||
#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE
|
||||
#define SendSWVHTGIDMgntFrame(pDM_VOID, RA)
|
||||
#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll)
|
||||
#define SendSWVHTMUNDPAPacket(pDM_VOID, BW)
|
||||
#endif
|
||||
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
u4Byte
|
||||
Beamforming_GetReportFrame(
|
||||
IN PVOID pDM_VOID,
|
||||
union recv_frame *precv_frame
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendFWHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendSWHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendFWVHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN u2Byte AID,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
SendSWVHTNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu1Byte RA,
|
||||
IN u2Byte AID,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
#endif
|
||||
|
||||
VOID
|
||||
Beamforming_GetNDPAFrame(
|
||||
IN PVOID pDM_VOID,
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
IN OCTET_STRING pduOS
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
union recv_frame *precv_frame
|
||||
#endif
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
DBG_SendSWVHTMUNDPAPacket(
|
||||
IN PVOID pDM_VOID,
|
||||
IN CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
#else
|
||||
#define Beamforming_GetNDPAFrame(pDM_Odm, _PduOS)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define Beamforming_GetReportFrame(Adapter, precv_frame) RT_STATUS_FAILURE
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define Beamforming_GetReportFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE
|
||||
#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE
|
||||
#endif
|
||||
#define SendFWHTNDPAPacket(pDM_VOID, RA, BW)
|
||||
#define SendSWHTNDPAPacket(pDM_VOID, RA, BW)
|
||||
#define SendFWVHTNDPAPacket(pDM_VOID, RA, AID, BW)
|
||||
#define SendSWVHTNDPAPacket(pDM_VOID, RA, AID, BW)
|
||||
#define SendSWVHTGIDMgntFrame(pDM_VOID, RA, idx)
|
||||
#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll)
|
||||
#define SendSWVHTMUNDPAPacket(pDM_VOID, BW)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,527 @@
|
||||
//============================================================
|
||||
// Description:
|
||||
//
|
||||
// This file is for 8812/8821/8811 TXBF mechanism
|
||||
//
|
||||
//============================================================
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
|
||||
VOID
|
||||
HalTxbf8812A_setNDPArate(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte BW,
|
||||
IN u1Byte Rate
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8812A, (Rate << 2 | BW));
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
halTxbfJaguar_RfMode(
|
||||
IN PVOID pDM_VOID,
|
||||
IN PRT_BEAMFORMING_INFO pBeamInfo
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
if (pDM_Odm->RFType == ODM_1T1R)
|
||||
return;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__));
|
||||
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/
|
||||
|
||||
if (pBeamInfo->beamformee_su_cnt > 0) {
|
||||
// Paath_A
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/
|
||||
// Path_B
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/
|
||||
} else {
|
||||
// Paath_A
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/
|
||||
// Path_B
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/
|
||||
}
|
||||
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/
|
||||
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/
|
||||
|
||||
if (pBeamInfo->beamformee_su_cnt > 0)
|
||||
ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x33);
|
||||
else
|
||||
ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x11);
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
halTxbfJaguar_DownloadNDPA(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page;
|
||||
u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0;
|
||||
BOOLEAN bSendBeacon = FALSE;
|
||||
u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*pDM_Odm->pbFwDwRsvdPageInProgress = TRUE;
|
||||
#endif
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (Idx == 0)
|
||||
Head_Page = 0xFE;
|
||||
else
|
||||
Head_Page = 0xFE;
|
||||
|
||||
Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy);
|
||||
|
||||
/*Set REG_CR bit 8. DMA beacon by SW.*/
|
||||
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1);
|
||||
ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp | BIT0));
|
||||
|
||||
|
||||
/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
|
||||
tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2);
|
||||
ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422 & (~BIT6));
|
||||
|
||||
if (tmpReg422 & BIT6) {
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an Adapter is sending beacon.\n"));
|
||||
bSendBeacon = TRUE;
|
||||
}
|
||||
|
||||
/*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, Head_Page);
|
||||
|
||||
do {
|
||||
/*Clear beacon valid check bit.*/
|
||||
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2);
|
||||
ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 2, (BcnValidReg | BIT0));
|
||||
|
||||
/*download NDPA rsvd page.*/
|
||||
if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)
|
||||
Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE);
|
||||
else
|
||||
Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);
|
||||
|
||||
/*check rsvd page download OK.*/
|
||||
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2);
|
||||
count = 0;
|
||||
while (!(BcnValidReg & BIT0) && count < 20) {
|
||||
count++;
|
||||
ODM_delay_ms(10);
|
||||
BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2);
|
||||
}
|
||||
DLBcnCount++;
|
||||
} while (!(BcnValidReg & BIT0) && DLBcnCount < 5);
|
||||
|
||||
if (!(BcnValidReg & BIT0))
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__));
|
||||
|
||||
/*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, TxPageBndy);
|
||||
|
||||
/*To make sure that if there exists an adapter which would like to send beacon.*/
|
||||
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
|
||||
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
|
||||
/*the beacon cannot be sent by HW.*/
|
||||
/*2010.06.23. Added by tynli.*/
|
||||
if (bSendBeacon)
|
||||
ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422);
|
||||
|
||||
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
|
||||
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
|
||||
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1);
|
||||
ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp & (~BIT0)));
|
||||
|
||||
pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*pDM_Odm->pbFwDwRsvdPageInProgress = FALSE;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
halTxbfJaguar_FwTxBFCmd(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte Idx, Period0 = 0, Period1 = 0;
|
||||
u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF;
|
||||
u1Byte u1TxBFParm[3] = {0};
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
|
||||
for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) {
|
||||
/*Modified by David*/
|
||||
if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
|
||||
if (Idx == 0) {
|
||||
if (pBeamInfo->BeamformeeEntry[Idx].bSound)
|
||||
PageNum0 = 0xFE;
|
||||
else
|
||||
PageNum0 = 0xFF; /*stop sounding*/
|
||||
Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
|
||||
} else if (Idx == 1) {
|
||||
if (pBeamInfo->BeamformeeEntry[Idx].bSound)
|
||||
PageNum1 = 0xFE;
|
||||
else
|
||||
PageNum1 = 0xFF; /*stop sounding*/
|
||||
Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
u1TxBFParm[0] = PageNum0;
|
||||
u1TxBFParm[1] = PageNum1;
|
||||
u1TxBFParm[2] = (Period1 << 4) | Period0;
|
||||
ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
|
||||
("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Enter(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte BFerBFeeIdx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte i = 0;
|
||||
u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;
|
||||
u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);
|
||||
u4Byte CSI_Param;
|
||||
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
|
||||
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
|
||||
RT_BEAMFORMER_ENTRY BeamformerEntry;
|
||||
u2Byte STAid = 0;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__));
|
||||
|
||||
halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo);
|
||||
|
||||
if (pDM_Odm->RFType == ODM_2T2R)
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x00000000); /*Nc =2*/
|
||||
else
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x01081008); /*Nc =1*/
|
||||
|
||||
if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {
|
||||
BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];
|
||||
|
||||
/*Sounding protocol control*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB);
|
||||
|
||||
/*MAC address/Partial AID of Beamformer*/
|
||||
if (BFerIdx == 0) {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
ODM_Write1Byte(pDM_Odm, (REG_BFMER0_INFO_8812A + i), BeamformerEntry.MacAddr[i]);
|
||||
/*CSI report use legacy ofdm so don't need to fill P_AID. */
|
||||
/*PlatformEFIOWrite2Byte(Adapter, REG_BFMER0_INFO_8812A+6, BeamformEntry.P_AID); */
|
||||
} else {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
ODM_Write1Byte(pDM_Odm, (REG_BFMER1_INFO_8812A + i), BeamformerEntry.MacAddr[i]);
|
||||
/*CSI report use legacy ofdm so don't need to fill P_AID.*/
|
||||
/*PlatformEFIOWrite2Byte(Adapter, REG_BFMER1_INFO_8812A+6, BeamformEntry.P_AID);*/
|
||||
}
|
||||
|
||||
/*CSI report parameters of Beamformee*/
|
||||
if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) {
|
||||
if (pDM_Odm->RFType == ODM_2T2R)
|
||||
CSI_Param = 0x01090109;
|
||||
else
|
||||
CSI_Param = 0x01080108;
|
||||
} else {
|
||||
if (pDM_Odm->RFType == ODM_2T2R)
|
||||
CSI_Param = 0x03090309;
|
||||
else
|
||||
CSI_Param = 0x03080308;
|
||||
}
|
||||
|
||||
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, CSI_Param);
|
||||
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, CSI_Param);
|
||||
ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, CSI_Param);
|
||||
|
||||
/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50);
|
||||
}
|
||||
|
||||
|
||||
if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {
|
||||
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];
|
||||
|
||||
if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
|
||||
STAid = BeamformeeEntry.MacId;
|
||||
else
|
||||
STAid = BeamformeeEntry.P_AID;
|
||||
|
||||
/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
|
||||
if (BFeeIdx == 0) {
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, STAid);
|
||||
ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3) | BIT4 | BIT6 | BIT7);
|
||||
} else
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, STAid | BIT12 | BIT14 | BIT15);
|
||||
|
||||
/*CSI report parameters of Beamformee*/
|
||||
if (BFeeIdx == 0) {
|
||||
/*Get BIT24 & BIT25*/
|
||||
u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3) & 0x3;
|
||||
|
||||
ODM_Write1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);
|
||||
ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, STAid | BIT9);
|
||||
} else {
|
||||
/*Set BIT25*/
|
||||
ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, STAid | 0xE200);
|
||||
}
|
||||
phydm_Beamforming_Notify(pDM_Odm);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Leave(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
|
||||
RT_BEAMFORMER_ENTRY BeamformerEntry;
|
||||
RT_BEAMFORMEE_ENTRY BeamformeeEntry;
|
||||
|
||||
if (Idx < BEAMFORMER_ENTRY_NUM) {
|
||||
BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx];
|
||||
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx];
|
||||
} else
|
||||
return;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, Idx));
|
||||
|
||||
/*Clear P_AID of Beamformee*/
|
||||
/*Clear MAC address of Beamformer*/
|
||||
/*Clear Associated Bfmee Sel*/
|
||||
|
||||
if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8);
|
||||
if (Idx == 0) {
|
||||
ODM_Write4Byte(pDM_Odm, REG_BFMER0_INFO_8812A, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_BFMER0_INFO_8812A + 4, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
|
||||
} else {
|
||||
ODM_Write4Byte(pDM_Odm, REG_BFMER1_INFO_8812A, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_BFMER1_INFO_8812A + 4, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
|
||||
}
|
||||
}
|
||||
|
||||
if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
|
||||
halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo);
|
||||
if (Idx == 0) {
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, 0x0);
|
||||
ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, 0);
|
||||
} else {
|
||||
ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2) & 0xF000);
|
||||
ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2) & 0x60);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Status(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u2Byte BeamCtrlVal;
|
||||
u4Byte BeamCtrlReg;
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx];
|
||||
|
||||
if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
|
||||
BeamCtrlVal = BeamformEntry.MacId;
|
||||
else
|
||||
BeamCtrlVal = BeamformEntry.P_AID;
|
||||
|
||||
if (Idx == 0)
|
||||
BeamCtrlReg = REG_TXBF_CTRL_8812A;
|
||||
else {
|
||||
BeamCtrlReg = REG_TXBF_CTRL_8812A + 2;
|
||||
BeamCtrlVal |= BIT12 | BIT14 | BIT15;
|
||||
}
|
||||
|
||||
if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) {
|
||||
if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20)
|
||||
BeamCtrlVal |= BIT9;
|
||||
else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40)
|
||||
BeamCtrlVal |= (BIT9 | BIT10);
|
||||
else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80)
|
||||
BeamCtrlVal |= (BIT9 | BIT10 | BIT11);
|
||||
} else
|
||||
BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamCtrlVal = 0x%x!\n", __func__, BeamCtrlVal));
|
||||
|
||||
ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal);
|
||||
}
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_FwTxBF(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING)
|
||||
halTxbfJaguar_DownloadNDPA(pDM_Odm, Idx);
|
||||
|
||||
halTxbfJaguar_FwTxBFCmd(pDM_Odm);
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Patch(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Operation
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE)
|
||||
return;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (Operation == SCAN_OPT_BACKUP_BAND0)
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8);
|
||||
else if (Operation == SCAN_OPT_RESTORE)
|
||||
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Clk_8812A(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u2Byte u2btmp;
|
||||
u1Byte Count = 0, u1btmp;
|
||||
PADAPTER Adapter = pDM_Odm->Adapter;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (*(pDM_Odm->pbScanInProcess)) {
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__));
|
||||
return;
|
||||
}
|
||||
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
|
||||
/*Stop PCIe TxDMA*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);
|
||||
#endif
|
||||
|
||||
/*Stop Usb TxDMA*/
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_DISABLE_FUNC(Adapter, DF_TX_BIT);
|
||||
PlatformReturnAllPendingTxPackets(Adapter);
|
||||
#else
|
||||
rtw_write_port_cancel(Adapter);
|
||||
#endif
|
||||
|
||||
/*Wait TXFF empty*/
|
||||
for (Count = 0; Count < 100; Count++) {
|
||||
u2btmp = ODM_Read2Byte(pDM_Odm, REG_TXPKT_EMPTY_8812A);
|
||||
u2btmp = u2btmp & 0xfff;
|
||||
if (u2btmp != 0xfff) {
|
||||
ODM_delay_ms(10);
|
||||
continue;
|
||||
} else
|
||||
break;
|
||||
}
|
||||
|
||||
/*TX pause*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF);
|
||||
|
||||
/*Wait TX State Machine OK*/
|
||||
for (Count = 0; Count < 100; Count++) {
|
||||
if (ODM_Read4Byte(pDM_Odm, REG_SCH_TXCMD_8812A) != 0)
|
||||
continue;
|
||||
else
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/*Stop RX DMA path*/
|
||||
u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A);
|
||||
ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT2);
|
||||
|
||||
for (Count = 0; Count < 100; Count++) {
|
||||
u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A);
|
||||
if (u1btmp & BIT1)
|
||||
break;
|
||||
else
|
||||
ODM_delay_ms(10);
|
||||
}
|
||||
|
||||
/*Disable clock*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xf0);
|
||||
/*Disable 320M*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8);
|
||||
/*Enable 320M*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa);
|
||||
/*Enable clock*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xfc);
|
||||
|
||||
|
||||
/*Release Tx pause*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0);
|
||||
|
||||
/*Enable RX DMA path*/
|
||||
u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A);
|
||||
ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT2));
|
||||
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
|
||||
/*Enable PCIe TxDMA*/
|
||||
ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0);
|
||||
#endif
|
||||
/*Start Usb TxDMA*/
|
||||
RT_ENABLE_FUNC(Adapter, DF_TX_BIT);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,75 @@
|
||||
#ifndef __HAL_TXBF_JAGUAR_H__
|
||||
#define __HAL_TXBF_JAGUAR_H__
|
||||
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
VOID
|
||||
HalTxbf8812A_setNDPArate(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte BW,
|
||||
IN u1Byte Rate
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Enter(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Leave(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Status(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_FwTxBF(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Idx
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Patch(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u1Byte Operation
|
||||
);
|
||||
|
||||
|
||||
VOID
|
||||
HalTxbfJaguar_Clk_8812A(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
#else
|
||||
|
||||
#define HalTxbf8812A_setNDPArate(pDM_VOID, BW, Rate)
|
||||
#define HalTxbfJaguar_Enter(pDM_VOID, Idx)
|
||||
#define HalTxbfJaguar_Leave(pDM_VOID, Idx)
|
||||
#define HalTxbfJaguar_Status(pDM_VOID, Idx)
|
||||
#define HalTxbfJaguar_FwTxBF(pDM_VOID, Idx)
|
||||
#define HalTxbfJaguar_Patch(pDM_VOID, Operation)
|
||||
#define HalTxbfJaguar_Clk_8812A(pDM_VOID)
|
||||
#endif
|
||||
#else
|
||||
|
||||
#define HalTxbf8812A_setNDPArate(pDM_VOID, BW, Rate)
|
||||
#define HalTxbfJaguar_Enter(pDM_VOID, Idx)
|
||||
#define HalTxbfJaguar_Leave(pDM_VOID, Idx)
|
||||
#define HalTxbfJaguar_Status(pDM_VOID, Idx)
|
||||
#define HalTxbfJaguar_FwTxBF(pDM_VOID, Idx)
|
||||
#define HalTxbfJaguar_Patch(pDM_VOID, Operation)
|
||||
#define HalTxbfJaguar_Clk_8812A(pDM_VOID)
|
||||
#endif
|
||||
|
||||
#endif // #ifndef __HAL_TXBF_JAGUAR_H__
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (defined(CONFIG_BB_TXBF_API))
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
/*Add by YuChen for 8822B MU-MIMO API*/
|
||||
|
||||
/*this function is only used for BFer*/
|
||||
u1Byte
|
||||
phydm_get_ndpa_rate(
|
||||
IN PVOID pDM_VOID
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte NDPARate = ODM_RATE6M;
|
||||
|
||||
if (pDM_Odm->RSSI_Min >= 30) /*link RSSI > 30%*/
|
||||
NDPARate = ODM_RATE24M;
|
||||
else if (pDM_Odm->RSSI_Min <= 25)
|
||||
NDPARate = ODM_RATE6M;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] NDPARate = 0x%x\n", __func__, NDPARate));
|
||||
|
||||
return NDPARate;
|
||||
|
||||
}
|
||||
|
||||
/*this function is only used for BFer*/
|
||||
u1Byte
|
||||
phydm_get_beamforming_sounding_info(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu2Byte Troughput,
|
||||
IN u1Byte Total_BFee_Num,
|
||||
IN pu1Byte TxRate
|
||||
)
|
||||
{
|
||||
u1Byte idx = 0;
|
||||
u1Byte soundingdecision = 0xff;
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
for (idx = 0; idx < Total_BFee_Num; idx++) {
|
||||
if (((TxRate[idx] >= ODM_RATEVHTSS3MCS7) && (TxRate[idx] <= ODM_RATEVHTSS3MCS9)))
|
||||
soundingdecision = soundingdecision & ~(1<<idx);
|
||||
}
|
||||
|
||||
for (idx = 0; idx < Total_BFee_Num; idx++) {
|
||||
if (Troughput[idx] <= 10)
|
||||
soundingdecision = soundingdecision & ~(1<<idx);
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] soundingdecision = 0x%x\n", __func__, soundingdecision));
|
||||
|
||||
return soundingdecision;
|
||||
|
||||
}
|
||||
|
||||
/*this function is only used for BFer*/
|
||||
u1Byte
|
||||
phydm_get_mu_bfee_snding_decision(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u2Byte Throughput
|
||||
)
|
||||
{
|
||||
u1Byte snding_score = 0;
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
/*Throughput unit is Mbps*/
|
||||
if (Throughput >= 500)
|
||||
snding_score = 100;
|
||||
else if (Throughput >= 450)
|
||||
snding_score = 90;
|
||||
else if (Throughput >= 400)
|
||||
snding_score = 80;
|
||||
else if (Throughput >= 350)
|
||||
snding_score = 70;
|
||||
else if (Throughput >= 300)
|
||||
snding_score = 60;
|
||||
else if (Throughput >= 250)
|
||||
snding_score = 50;
|
||||
else if (Throughput >= 200)
|
||||
snding_score = 40;
|
||||
else if (Throughput >= 150)
|
||||
snding_score = 30;
|
||||
else if (Throughput >= 100)
|
||||
snding_score = 20;
|
||||
else if (Throughput >= 50)
|
||||
snding_score = 10;
|
||||
else
|
||||
snding_score = 0;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] snding_score = 0x%d\n", __func__, snding_score));
|
||||
|
||||
return snding_score;
|
||||
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
u1Byte
|
||||
Beamforming_GetHTNDPTxRate(
|
||||
IN PVOID pDM_VOID,
|
||||
u1Byte CompSteeringNumofBFer
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte Nr_index = 0;
|
||||
u1Byte NDPTxRate;
|
||||
/*Find Nr*/
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer);
|
||||
else
|
||||
#endif
|
||||
Nr_index = TxBF_Nr(1, CompSteeringNumofBFer);
|
||||
|
||||
switch (Nr_index) {
|
||||
case 1:
|
||||
NDPTxRate = ODM_MGN_MCS8;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
NDPTxRate = ODM_MGN_MCS16;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
NDPTxRate = ODM_MGN_MCS24;
|
||||
break;
|
||||
|
||||
default:
|
||||
NDPTxRate = ODM_MGN_MCS8;
|
||||
break;
|
||||
}
|
||||
|
||||
return NDPTxRate;
|
||||
|
||||
}
|
||||
|
||||
u1Byte
|
||||
Beamforming_GetVHTNDPTxRate(
|
||||
IN PVOID pDM_VOID,
|
||||
u1Byte CompSteeringNumofBFer
|
||||
)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u1Byte Nr_index = 0;
|
||||
u1Byte NDPTxRate;
|
||||
/*Find Nr*/
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (pDM_Odm->SupportICType & ODM_RTL8814A)
|
||||
Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer);
|
||||
else
|
||||
#endif
|
||||
Nr_index = TxBF_Nr(1, CompSteeringNumofBFer);
|
||||
|
||||
switch (Nr_index) {
|
||||
case 1:
|
||||
NDPTxRate = ODM_MGN_VHT2SS_MCS0;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
NDPTxRate = ODM_MGN_VHT3SS_MCS0;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
NDPTxRate = ODM_MGN_VHT4SS_MCS0;
|
||||
break;
|
||||
|
||||
default:
|
||||
NDPTxRate = ODM_MGN_VHT2SS_MCS0;
|
||||
break;
|
||||
}
|
||||
|
||||
return NDPTxRate;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
/********************************************************************************/
|
||||
/**/
|
||||
/*Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.*/
|
||||
/**/
|
||||
/*This program is free software; you can redistribute it and/or modify it*/
|
||||
/*under the terms of version 2 of the GNU General Public License as*/
|
||||
/*published by the Free Software Foundation.*/
|
||||
/**/
|
||||
/*This program is distributed in the hope that it will be useful, but WITHOUT*/
|
||||
/*ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or*/
|
||||
/*FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for*/
|
||||
/*more details.*/
|
||||
/*You should have received a copy of the GNU General Public License along with*/
|
||||
/*this program; if not, write to the Free Software Foundation, Inc.,*/
|
||||
/*51 Franklin Street, Fifth Floor, Boston, MA 02110, USA*/
|
||||
/**/
|
||||
/**/
|
||||
/********************************************************************************/
|
||||
#ifndef __PHYDM_HAL_TXBF_API_H__
|
||||
#define __PHYDM_HAL_TXBF_API_H__
|
||||
|
||||
#if (defined(CONFIG_BB_TXBF_API))
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
#define TxBF_Nr(a, b) ((a > b) ? (b) : (a))
|
||||
|
||||
u1Byte
|
||||
Beamforming_GetHTNDPTxRate(
|
||||
IN PVOID pDM_VOID,
|
||||
u1Byte CompSteeringNumofBFer
|
||||
);
|
||||
|
||||
u1Byte
|
||||
Beamforming_GetVHTNDPTxRate(
|
||||
IN PVOID pDM_VOID,
|
||||
u1Byte CompSteeringNumofBFer
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
u1Byte
|
||||
phydm_get_beamforming_sounding_info(
|
||||
IN PVOID pDM_VOID,
|
||||
IN pu2Byte Troughput,
|
||||
IN u1Byte Total_BFee_Num,
|
||||
IN pu1Byte TxRate
|
||||
);
|
||||
|
||||
u1Byte
|
||||
phydm_get_ndpa_rate(
|
||||
IN PVOID pDM_VOID
|
||||
);
|
||||
|
||||
u1Byte
|
||||
phydm_get_mu_bfee_snding_decision(
|
||||
IN PVOID pDM_VOID,
|
||||
IN u2Byte Throughput
|
||||
);
|
||||
|
||||
#else
|
||||
#define phydm_get_beamforming_sounding_info(pDM_VOID, Troughput, Total_BFee_Num, TxRate)
|
||||
#define phydm_get_ndpa_rate(pDM_VOID)
|
||||
#define phydm_get_mu_bfee_snding_decision(pDM_VOID, Troughput)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user