random-mirrors/amazingfate-rtl8723ds
1
0
Fork 0
mirror of https://github.com/amazingfate/rtl8723ds.git synced 2026-06-18 18:29:01 +01:00
Code Issues Packages Projects Releases Wiki Activity

rtl8723ds: Initial commit of files

Browse Source 
This repository contains the Realtek driver V5.1.1.5_20523.20161209_BTCOEX20161208-1212.

At inclusion, the only changes from the Realtek version were to fix any compile
warnings or errors. With these changes, the driver builds on kernels through
4.11.

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
2017-04-25 09:56:34 -05:00
parent 76ab2438bb
commit e87533e664
469 changed files with 410449 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hal/phydm/rtl8723d/hal8723dreg.h
+927
View File
@@ -0,0 +1,927 @@
/*****************************************************************************
* Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved.
*
* Module: __INC_HAL8723DREG_H
*
*
* Note: 1. Define Mac register address and corresponding bit mask map
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
*
* History:
* Data Who Remark
*
*****************************************************************************/
#ifndef __INC_HAL8723DREG_H
#define __INC_HAL8723DREG_H
//============================================================
//
//============================================================
//-----------------------------------------------------
//
// 0x0000h ~ 0x00FFh System Configuration
//
//-----------------------------------------------------
#define REG_SYS_ISO_CTRL_8723D 0x0000 // 2 Byte
#define REG_SYS_FUNC_EN_8723D 0x0002 // 2 Byte
#define REG_SYS_PW_CTRL_8723D 0x0004 // 4 Byte
#define REG_SYS_CLKR_8723D 0x0008 // 2 Byte
#define REG_SYS_EEPROM_CTRL_8723D 0x000A // 2 Byte
#define REG_EE_VPD_8723D 0x000C // 2 Byte
#define REG_SYS_SWR_CTRL1_8723D 0x0010 // 1 Byte
#define REG_SYS_SWR_CTRL2_8723D 0x0014 // 1 Byte
#define REG_SYS_SWR_CTRL3_8723D 0x0018 // 4 Byte
#define REG_RSV_CTRL_8723D 0x001C // 3 Byte
#define REG_RF_CTRL_8723D 0x001F // 1 Byte
#define REG_AFE_CTRL1_8723D 0x0024 // 4 Byte
#define REG_AFE_CTRL2_8723D 0x0028 // 4 Byte
#define REG_AFE_CTRL3_8723D 0x002c // 4 Byte
#define REG_EFUSE_CTRL_8723D 0x0030
#define REG_LDO_EFUSE_CTRL_8723D 0x0034
#define REG_PWR_DATA_8723D 0x0038
#define REG_CAL_TIMER_8723D 0x003C
#define REG_ACLK_MON_8723D 0x003E
#define REG_GPIO_MUXCFG_8723D 0x0040
#define REG_GPIO_IO_SEL_8723D 0x0042
#define REG_MAC_PINMUX_CFG_8723D 0x0043 // ??????
#define REG_GPIO_PIN_CTRL_8723D 0x0044
#define REG_GPIO_INTM_8723D 0x0048
#define BIT_REG_LED_CFG_8723D 0x004C
#define REG_LEDCFG2_8723D 0x004E // ??????
#define REG_FSIMR_8723D 0x0050
#define REG_FSISR_8723D 0x0054
#define REG_HSIMR_8723D 0x0058
#define REG_HSISR_8723D 0x005c
#define REG_GPIO_EXT_CTRL_8723D 0x0060
#define REG_MULTI_FUNC_CTRL_8723D 0x0068
#define REG_GPIO_STATUS_8723D 0x006C
#define REG_SDIO_CTRL_8723D 0x0070
#define REG_HCI_OPT_CTRL_8723D 0x0074
#define REG_AFE_CTRL4_8723D 0x0078
#define REG_LDO_SWR_CTRL_8723D 0x007C
#define REG_8051FW_CTRL_8723D 0x0080
#define REG_FW_DBG_STATUS_8723D 0x0088
#define REG_FW_DBG_CTRL_8723D 0x008F
#define REG_WLLPS_CTRL_8723D 0x0090
#define REG_HIMR0_8723D 0x00B0
#define REG_HISR0_8723D 0x00B4
#define REG_HIMR1_8723D 0x00B8
#define REG_HISR1_8723D 0x00BC
#define REG_PMC_DBG_CTRL2_8723D 0x00CC
#define REG_EFUSE_BURN_GNT_8723D 0x00CF
#define REG_XTAL_AAC_8723D 0x00EC
#define REG_SYS_CFG1_8723D 0x00F0
#define REG_SYS_CFG2_8723D 0x00FC
#define REG_ROM_VERSION 0x00FD
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
#define REG_CR_8723D 0x0100
#define REG_PBP_8723D 0x0104 // ??????
#define REG_PKT_BUFF_ACCESS_CTRL_8723D 0x0106 // ??????
#define REG_TRXDMA_CTRL_8723D 0x010C
#define REG_TRXFF_BNDY_8723D 0x0114
#define REG_RXFF_PTR_8723D 0x011C
#define REG_CPWM_8723D 0x012C
#define REG_FWIMR_8723D 0x0130
#define REG_FWISR_8723D 0x0134
#define REG_FTIMR_8723D 0x0138
#define REG_PKTBUF_DBG_CTRL_8723D 0x0140
#define REG_RXPKTBUF_CTRL_8723D 0x0142 // ??????
#define REG_PKTBUF_DBG_DATA_L_8723D 0x0144
#define REG_PKTBUF_DBG_DATA_H_8723D 0x0148
#define REG_TC0_CTRL_8723D 0x0150
#define REG_TC1_CTRL_8723D 0x0154
#define REG_TC2_CTRL_8723D 0x0158
#define REG_TC3_CTRL_8723D 0x015C
#define REG_TC4_CTRL_8723D 0x0160
#define REG_TCUNIT_BASE_8723D 0x0164
#define REG_RSVD3_8723D 0x0168 // ?????
#define REG_C2HEVT_MSG_NORMAL_8723D 0x01A0 // ??????
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 // ??????
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 // ??????
#define REG_C2HEVT_CMD_LEN_88XX 0x01AE // ??????
#define REG_C2HEVT_CLEAR_8723D 0x01AF // ??????
#define REG_MCUTST_1_8723D 0x01C0
#define REG_MCUTST_2_8723D 0x01C4
#define REG_MCUTST_WOWLAN_8723D 0x01C7 // ??????
#define REG_FMETHR_8723D 0x01C8
#define REG_HMETFR_8723D 0x01CC
#define REG_HMEBOX_0_8723D 0x01D0
#define REG_HMEBOX_1_8723D 0x01D4
#define REG_HMEBOX_2_8723D 0x01D8
#define REG_HMEBOX_3_8723D 0x01DC
#define REG_LLT_INIT_8723D 0x01E0
#define REG_HMEBOX_EXT0_8723D 0x01F0 // ??????
#define REG_HMEBOX_EXT1_8723D 0x01F4 // ??????
#define REG_HMEBOX_EXT2_8723D 0x01F8 // ??????
#define REG_HMEBOX_EXT3_8723D 0x01FC // ??????
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
#define REG_RQPN_8723D 0x0200
#define REG_FIFOPAGE_8723D 0x0204
#define REG_TDECTRL_8723D 0x0208
#define REG_TXDMA_OFFSET_CHK_8723D 0x020C
#define REG_TXDMA_STATUS_8723D 0x0210
#define REG_RQPN_NPQ_8723D 0x0214
#define REG_AUTO_LLT_8723D 0x0224
#define REG_DWBCN1_CTRL_8723D 0x0228
//-----------------------------------------------------
//
// 0x0280h ~ 0x02FFh RXDMA Configuration
//
//-----------------------------------------------------
#define REG_RXDMA_AGG_PG_TH_8723D 0x0280
#define REG_RXPKT_NUM_8723D 0x0284 // The number of packets in RXPKTBUF.
#define REG_RXDMA_CONTROL_8723D 0x0286 // ?????? Control the RX DMA.
#define REG_RXDMA_STATUS_8723D 0x0288
#define REG_RXDMA_PRO_8723D 0x0290 // ??????
#define REG_EARLY_MODE_CONTROL_8723D 0x02BC // ??????
#define REG_RSVD5_8723D 0x02F0 // ??????
//-----------------------------------------------------
//
// 0x0300h ~ 0x03FFh PCIe
//
//-----------------------------------------------------
#define REG_PCIE_CTRL_REG_8723D 0x0300
#define REG_INT_MIG_8723D 0x0304 // Interrupt Migration
#define REG_BCNQ_TXBD_DESA_8723D 0x0308 // TX Beacon Descriptor Address
#define REG_MGQ_TXBD_DESA_8723D 0x0310 // TX Manage Queue Descriptor Address
#define REG_VOQ_TXBD_DESA_8723D 0x0318 // TX VO Queue Descriptor Address
#define REG_VIQ_TXBD_DESA_8723D 0x0320 // TX VI Queue Descriptor Address
#define REG_BEQ_TXBD_DESA_8723D 0x0328 // TX BE Queue Descriptor Address
#define REG_BKQ_TXBD_DESA_8723D 0x0330 // TX BK Queue Descriptor Address
#define REG_RXQ_RXBD_DESA_8723D 0x0338 // RX Queue Descriptor Address
#define REG_HI0Q_TXBD_DESA_8723D 0x0340
#define REG_HI1Q_TXBD_DESA_8723D 0x0348
#define REG_HI2Q_TXBD_DESA_8723D 0x0350
#define REG_HI3Q_TXBD_DESA_8723D 0x0358
#define REG_HI4Q_TXBD_DESA_8723D 0x0360
#define REG_HI5Q_TXBD_DESA_8723D 0x0368
#define REG_HI6Q_TXBD_DESA_8723D 0x0370
#define REG_HI7Q_TXBD_DESA_8723D 0x0378
#define REG_MGQ_TXBD_NUM_8723D 0x0380
#define REG_RX_RXBD_NUM_8723D 0x0382
#define REG_VOQ_TXBD_NUM_8723D 0x0384
#define REG_VIQ_TXBD_NUM_8723D 0x0386
#define REG_BEQ_TXBD_NUM_8723D 0x0388
#define REG_BKQ_TXBD_NUM_8723D 0x038A
#define REG_HI0Q_TXBD_NUM_8723D 0x038C
#define REG_HI1Q_TXBD_NUM_8723D 0x038E
#define REG_HI2Q_TXBD_NUM_8723D 0x0390
#define REG_HI3Q_TXBD_NUM_8723D 0x0392
#define REG_HI4Q_TXBD_NUM_8723D 0x0394
#define REG_HI5Q_TXBD_NUM_8723D 0x0396
#define REG_HI6Q_TXBD_NUM_8723D 0x0398
#define REG_HI7Q_TXBD_NUM_8723D 0x039A
#define REG_TSFTIMER_HCI_8723D 0x039C
//Read Write Point
#define REG_VOQ_TXBD_IDX_8723D 0x03A0
#define REG_VIQ_TXBD_IDX_8723D 0x03A4
#define REG_BEQ_TXBD_IDX_8723D 0x03A8
#define REG_BKQ_TXBD_IDX_8723D 0x03AC
#define REG_MGQ_TXBD_IDX_8723D 0x03B0
#define REG_RXQ_TXBD_IDX_8723D 0x03B4
#define REG_HI0Q_TXBD_IDX_8723D 0x03B8
#define REG_HI1Q_TXBD_IDX_8723D 0x03BC
#define REG_HI2Q_TXBD_IDX_8723D 0x03C0
#define REG_HI3Q_TXBD_IDX_8723D 0x03C4
#define REG_HI4Q_TXBD_IDX_8723D 0x03C8
#define REG_HI5Q_TXBD_IDX_8723D 0x03CC
#define REG_HI6Q_TXBD_IDX_8723D 0x03D0
#define REG_HI7Q_TXBD_IDX_8723D 0x03D4
#define REG_PCIE_HCPWM_8723DE 0x03D8 // ??????
#define REG_PCIE_HRPWM_8723DE 0x03DC //PCIe RPWM // ??????
#define REG_DBI_WDATA_V1_8723D 0x03E8
#define REG_DBI_RDATA_V1_8723D 0x03EC
#define REG_DBI_FLAG_V1_8723D 0x03F0
#define REG_MDIO_V1_8723D 0x03F4
#define REG_PCIE_MIX_CFG_8723D 0x03F8
#define REG_HCI_MIX_CFG_8723D 0x03FC
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
#define REG_TXPKT_EMPTY_8723D 0x041A
#define REG_PTCL_POLL_MGN_8723D 0x041F
#define REG_FWHW_TXQ_CTRL_8723D 0x0420
#define REG_HWSEQ_CTRL_8723D 0x0423
#define REG_BCNQ_BDNY_8723D 0x0424
#define REG_MGQ_BDNY_8723D 0x0425
#define REG_LIFETIME_EN_8723D 0x0426
#define REG_FW_FREE_TAIL_8723D 0x0427
#define REG_SPEC_SIFS_8723D 0x0428
#define REG_RETRY_LIMIT_8723D 0x042A
#define REG_TXBF_CTRL_8723D 0x042C
#define REG_DARFRC_8723D 0x0430
#define REG_RARFRC_8723D 0x0438
#define REG_RRSR_8723D 0x0440
#define REG_ARFR0_8723D 0x0444
#define REG_ARFR1_8723D 0x044C
#define REG_CCK_CHECK_8723D 0x0454
#define REG_BCNQ2_BDNY_8723D 0x0455
#define REG_AMPDU_MAX_TIME_8723D 0x0456
#define REG_BCNQ1_BDNY_8723D 0x0457
#define REG_AMPDU_MAX_LENGTH_8723D 0x0458
#define REG_WMAC_LBK_BUF_HD_8723D 0x045D
#define REG_NDPA_OPT_CTRL_8723D 0x045F
#define REG_FAST_EDCA_CTRL_8723D 0x0460
#define REG_RD_RESP_PKT_TH_8723D 0x0463
#define REG_DATA_SC_8723D 0x0483
#define REG_TXRPT_START_OFFSET 0x04AC
#define REG_POWER_STAGE1_8723D 0x04B4
#define REG_PTCL_SDF_STATUS_8723D 0x04BB
#define REG_SW_AMPDU_BURST_MODE_CTRL_8723D 0x04BC
#define REG_EVTQ_BNDY_8723D 0x04BF
#define REG_PKT_LIFE_TIME_8723D 0x04C0
#define REG_PKT_BE_BK_LIFE_TIME_8723D 0x04C2 // ??????
#define REG_STBC_SETTING_8723D 0x04C4
#define REG_HT_SINGLE_AMPDU_8723D 0x04C7
#define REG_PROT_MODE_CTRL_8723D 0x04C8
#define REG_MAX_AGGR_NUM_8723D 0x04CA
#define REG_RTS_MAX_AGGR_NUM_8723D 0x04CB
#define REG_BAR_MODE_CTRL_8723D 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT_8723D 0x04CF
#define REG_MACID_SLEEP2_8723D 0x04D0
#define REG_PTCL_HWSSN0_8723D 0x04D8
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D 0x045D // ??????
/************* 0x1480~0x14A7 is for NAN ***************/
//Own Master Rank, 8Bytes
#define REG_NAN_INTERFACE_ADDR_8723D 0x2480 // 6 bytes
#define REG_NAN_RANDOM_FACTOR_8723D 0x2486 // 1 byte
#define REG_NAN_MASTER_PREF_8723D 0x2487 // 1 byte
//0x5dc[25:24] NAN role
//Current Anchor Master Record
#define REG_NAN_CAMR_L_8723D 0x2488 // 4 bytes
#define REG_NAN_CAMR_H_8723D 0x248C // 4 byte
//#define REG_HOP_CNT_8723D 0x05DC
#define REG_NAN_CAMR_AMBTT_8723D 0x2490 // 4 bytes
//Last Anchor Master Record
#define REG_NAN_LAMR_L_8723D 0x2494 // 4 bytes
#define REG_NAN_LAMR_H_8723D 0x2498 // 4 byte
#define REG_NAN_LAMR_AMBTT_8723D 0x249C // 4 bytes
//TSF Synced:bit 0
//Anchor Master: bit 7
#define REG_NAN_STATUS_8723D 0x24A0 //BIT0
/***************************************************/
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
// gogogo
#define REG_EDCA_VO_PARAM_8723D 0x0500
#define REG_EDCA_VI_PARAM_8723D 0x0504
#define REG_EDCA_BE_PARAM_8723D 0x0508
#define REG_EDCA_BK_PARAM_8723D 0x050C
#define REG_BCNTCFG_8723D 0x0510
#define REG_PIFS_8723D 0x0512
#define REG_RDG_PIFS_8723D 0x0513
#define REG_SIFS_CTX_8723D 0x0514
#define REG_SIFS_TRX_8723D 0x0516
#define REG_AGGR_BREAK_TIME_8723D 0x051A
#define REG_SLOT_8723D 0x051B
#define REG_TX_PTCL_CTRL_8723D 0x0520
#define REG_TXPAUSE_8723D 0x0522
#define REG_DIS_TXREQ_CLR_8723D 0x0523
#define REG_RD_CTRL_8723D 0x0524
//
// Format for offset 540h-542h:
// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
// [7:4]: Reserved.
// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
// [23:20]: Reserved
// Description:
// |
// |<--Setup--|--Hold------------>|
// --------------|----------------------
// |
// TBTT
// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
// Described by Designer Tim and Bruce, 2011-01-14.
//
#define REG_TBTT_PROHIBIT_8723D 0x0540
#define REG_RD_NAV_NXT_8723D 0x0544
#define REG_NAV_PROT_LEN_8723D 0x0546
#define REG_BCN_CTRL_8723D 0x0550
#define REG_EDCA_BCNCTRL1_IOREG_8723D 0x0551
#define REG_MBID_NUM_8723D 0x0552
#define REG_DUAL_TSF_RST_8723D 0x0553
#define REG_BCN_INTERVAL_8723D 0x0554
#define REG_DRVERLYINT_8723D 0x0558
#define REG_BCNDMATIM_8723D 0x0559
#define REG_ATIMWND_8723D 0x055A
#define REG_USTIME_TSF_8723D 0x055C
#define REG_BCN_MAX_ERR_8723D 0x055D
#define REG_RXTSF_OFFSET_CCK_8723D 0x055E
#define REG_RXTSF_OFFSET_OFDM_8723D 0x055F
#define REG_TSFTR_8723D 0x0560
#define REG_CTWND_8723D 0x0572
#define REG_SECONDARY_CCA_CTRL_8723D 0x0577 // ??????
#define REG_TSFTR2_8723D 0x0578
#define REG_PSTIMER_8723D 0x0580
#define REG_TIMER0_8723D 0x0584
#define REG_TIMER1_8723D 0x0588
#define REG_SCH_MULTI_BCN_8723D 0x05B2
#define REG_SCH_CURRENT_BCN_8723D 0x05B3
#define REG_ACMHWCTRL_8723D 0x05C0
#define REG_SCH_SDFX_EARLY_8723D 0x05CF
#define REG_SCH_PORT2_EARLY_8723D 0x05D0
#define REG_SCH_TSFT_DIFF_8723D 0x05D2
#define REG_EDCA_BCNCTRL2_IOREG_8723D 0x05D4
#define REG_EDCA_DRVERLYINT1_IOREG_8723D 0x05D4
#define REG_EDCA_BCNSPACE3_IOREG_8723D 0x05D8
#define REG_EDCA_BCNSPACE4_IOREG_8723D 0x05DA
#define REG_HOP_CNT_8723D 0x05DC
#define REG_SCH_M_DW_8723D 0x05DD
#define REG_SCH_M_SLOT_8723D 0x05DE
#define REG_SCH_EARLY_DWEND_8723D 0x05DF
#define REG_SCH_TXCMD_8723D 0x05F8
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
// gogogo
#define REG_MAC_CR_8723D 0x0600
#define REG_TCR_8723D 0x0604
#define REG_RCR_8723D 0x0608
#define REG_RX_PKT_LIMIT_8723D 0x060C
#define REG_RX_DLK_TIME_8723D 0x060D
#define REG_RX_DRVINFO_SZ_8723D 0x060F
#define REG_MACID_8723D 0x0610
#define REG_BSSID_8723D 0x0618
#define REG_MAR_8723D 0x0620
#define REG_MBIDCAMCFG_8723D 0x0628
#define REG_USTIME_EDCA_8723D 0x0638
#define REG_MAC_SPEC_SIFS_8723D 0x063A
#define REG_RESP_SIFP_CCK_8723D 0x063C
#define REG_RESP_SIFS_OFDM_8723D 0x063E
#define REG_ACKTO_8723D 0x0640
#define REG_CTS2TO_8723D 0x0641
#define REG_EIFS_8723D 0x0642
#define REG_NAV_UPPER_8723D 0x0652 // ??????
#define REG_TRXPTCL_CTL_8723D 0x0668
// Security
#define REG_CAMCMD_8723D 0x0670
#define REG_CAMWRITE_8723D 0x0674
#define REG_CAMREAD_8723D 0x0678
#define REG_CAMDBG_8723D 0x067C
#define REG_SECCFG_8723D 0x0680
// Power
#define REG_WOW_CTRL_8723D 0x0690
#define REG_PS_RX_INFO_8723D 0x0692
#define REG_UAPSD_TID_8723D 0x0693
#define REG_WKFMCAM_NUM_8723D 0x0698
#define REG_RXFLTMAP0_8723D 0x06A0
#define REG_RXFLTMAP1_8723D 0x06A2
#define REG_RXFLTMAP2_8723D 0x06A4
#define REG_BCN_PSR_RPT_8723D 0x06A8
#define REG_BT_COEX_TABLE_8723D 0x06C0
#define REG_ASSOCIATED_BFMER0_INFO_8723D 0x06E4
#define REG_ASSOCIATED_BFMER1_INFO_8723D 0x06EC
#define REG_CSI_RPT_PARAM_BW20_8723D 0x06F4
#define REG_CSI_RPT_PARAM_BW40_8723D 0x06F8
#define REG_CSI_RPT_PARAM_BW80_8723D 0x06FC
// Hardware Port 2
#define REG_MACID1_8723D 0x0700
#define REG_BSSID1_8723D 0x0708
#define REG_ASSOCIATED_BFMEE_SEL_8723D 0x0714
#define REG_SND_PTCL_CTRL_8723D 0x0718
//-----------------------------------------------------
//
// Redifine 8192C register definition for compatibility
//
//-----------------------------------------------------
// TODO: use these definition when using REG_xxx naming rule.
// NOTE: DO NOT Remove these definition. Use later.
#define EFUSE_CTRL_8723D REG_EFUSE_CTRL_8723D // E-Fuse Control.
#define EFUSE_TEST_8723D REG_LDO_EFUSE_CTRL_8723D // E-Fuse Test.
#define MSR_8723D (REG_CR_8723D + 2) // Media Status register
#define ISR_8723D REG_HISR0_8723D
#define TSFR_8723D REG_TSFTR_8723D // Timing Sync Function Timer Register.
// Redifine MACID register, to compatible prior ICs.
#define IDR0_8723D REG_MACID_8723D // MAC ID Register, Offset 0x0050-0x0053
#define IDR4_8723D (REG_MACID_8723D + 4) // MAC ID Register, Offset 0x0054-0x0055
//
// 9. Security Control Registers (Offset: )
//
#define RWCAM_8723D REG_CAMCMD_8723D //IN 8190 Data Sheet is called CAMcmd
#define WCAMI_8723D REG_CAMWRITE_8723D // Software write CAM input content
#define RCAMO_8723D REG_CAMREAD_8723D // Software read/write CAM config
#define CAMDBG_8723D REG_CAMDBG_8723D
#define SECR_8723D REG_SECCFG_8723D //Security Configuration Register
//----------------------------------------------------------------------------
// 8195 IMR/ISR bits (offset 0xB0, 8bits)
//----------------------------------------------------------------------------
#define IMR_DISABLED_8723D 0
// IMR DW0(0x00B0-00B3) Bit 0-31
#define IMR_TIMER2_8723D BIT31 // Timeout interrupt 2
#define IMR_TIMER1_8723D BIT30 // Timeout interrupt 1
#define IMR_PSTIMEOUT_8723D BIT29 // Power Save Time Out Interrupt
#define IMR_GTINT4_8723D BIT28 // When GTIMER4 expires, this bit is set to 1
#define IMR_GTINT3_8723D BIT27 // When GTIMER3 expires, this bit is set to 1
#define IMR_TXBCN0ERR_8723D BIT26 // Transmit Beacon0 Error
#define IMR_TXBCN0OK_8723D BIT25 // Transmit Beacon0 OK
#define IMR_TSF_BIT32_TOGGLE_8723D BIT24 // TSF Timer BIT32 toggle indication interrupt
#define IMR_BCNDMAINT0_8723D BIT20 // Beacon DMA Interrupt 0
#define IMR_BCNDERR0_8723D BIT16 // Beacon Queue DMA OK0
#define IMR_HSISR_IND_ON_INT_8723D BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
#define IMR_BCNDMAINT_E_8723D BIT14 // Beacon DMA Interrupt Extension for Win7
#define IMR_ATIMEND_8723D BIT12 // CTWidnow End or ATIM Window End
#define IMR_C2HCMD_8723D BIT10 // CPU to Host Command INT Status, Write 1 clear
#define IMR_CPWM2_8723D BIT9 // CPU power Mode exchange INT Status, Write 1 clear
#define IMR_CPWM_8723D BIT8 // CPU power Mode exchange INT Status, Write 1 clear
#define IMR_HIGHDOK_8723D BIT7 // High Queue DMA OK
#define IMR_MGNTDOK_8723D BIT6 // Management Queue DMA OK
#define IMR_BKDOK_8723D BIT5 // AC_BK DMA OK
#define IMR_BEDOK_8723D BIT4 // AC_BE DMA OK
#define IMR_VIDOK_8723D BIT3 // AC_VI DMA OK
#define IMR_VODOK_8723D BIT2 // AC_VO DMA OK
#define IMR_RDU_8723D BIT1 // Rx Descriptor Unavailable
#define IMR_ROK_8723D BIT0 // Receive DMA OK
// IMR DW1(0x00B4-00B7) Bit 0-31
#define IMR_BCNDMAINT7_8723D BIT27 // Beacon DMA Interrupt 7
#define IMR_BCNDMAINT6_8723D BIT26 // Beacon DMA Interrupt 6
#define IMR_BCNDMAINT5_8723D BIT25 // Beacon DMA Interrupt 5
#define IMR_BCNDMAINT4_8723D BIT24 // Beacon DMA Interrupt 4
#define IMR_BCNDMAINT3_8723D BIT23 // Beacon DMA Interrupt 3
#define IMR_BCNDMAINT2_8723D BIT22 // Beacon DMA Interrupt 2
#define IMR_BCNDMAINT1_8723D BIT21 // Beacon DMA Interrupt 1
#define IMR_BCNDOK7_8723D BIT20 // Beacon Queue DMA OK Interrup 7
#define IMR_BCNDOK6_8723D BIT19 // Beacon Queue DMA OK Interrup 6
#define IMR_BCNDOK5_8723D BIT18 // Beacon Queue DMA OK Interrup 5
#define IMR_BCNDOK4_8723D BIT17 // Beacon Queue DMA OK Interrup 4
#define IMR_BCNDOK3_8723D BIT16 // Beacon Queue DMA OK Interrup 3
#define IMR_BCNDOK2_8723D BIT15 // Beacon Queue DMA OK Interrup 2
#define IMR_BCNDOK1_8723D BIT14 // Beacon Queue DMA OK Interrup 1
#define IMR_ATIMEND_E_8723D BIT13 // ATIM Window End Extension for Win7
#define IMR_TXERR_8723D BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
#define IMR_RXERR_8723D BIT10 // Rx Error Flag INT Status, Write 1 clear
#define IMR_TXFOVW_8723D BIT9 // Transmit FIFO Overflow
#define IMR_RXFOVW_8723D BIT8 // Receive FIFO Overflow
#define IMR_MCUERR_8723D BIT28 // Beacon DMA Interrupt 7
/*===================================================================
=====================================================================
Here the register defines are for 92C. When the define is as same with 92C,
we will use the 92C's define for the consistency
So the following defines for 92C is not entire!!!!!!
=====================================================================
=====================================================================*/
/*
Based on Datasheet V33---090401
Register Summary
Current IOREG MAP
0x0000h ~ 0x00FFh System Configuration (256 Bytes)
0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
*/
//----------------------------------------------------------------------------
// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits)
//----------------------------------------------------------------------------
/*
#define StopBecon BIT6
#define StopHigh BIT5
#define StopMgt BIT4
#define StopVO BIT3
#define StopVI BIT2
#define StopBE BIT1
#define StopBK BIT0
*/
//============================================================================
// 8192C Regsiter Bit and Content definition
//============================================================================
//-----------------------------------------------------
//
// 0x0000h ~ 0x00FFh System Configuration
//
//-----------------------------------------------------
/*
//2 SYS_ISO_CTRL
#define ISO_MD2PP BIT(0)
#define ISO_UA2USB BIT(1)
#define ISO_UD2CORE BIT(2)
#define ISO_PA2PCIE BIT(3)
#define ISO_PD2CORE BIT(4)
#define ISO_IP2MAC BIT(5)
#define ISO_DIOP BIT(6)
#define ISO_DIOE BIT(7)
#define ISO_EB2CORE BIT(8)
#define ISO_DIOR BIT(9)
#define PWC_EV12V BIT(15)
//2 SYS_FUNC_EN
#define FEN_BBRSTB BIT(0)
#define FEN_BB_GLB_RSTn BIT(1)
#define FEN_USBA BIT(2)
#define FEN_UPLL BIT(3)
#define FEN_USBD BIT(4)
#define FEN_DIO_PCIE BIT(5)
#define FEN_PCIEA BIT(6)
#define FEN_PPLL BIT(7)
#define FEN_PCIED BIT(8)
#define FEN_DIOE BIT(9)
#define FEN_CPUEN BIT(10)
#define FEN_DCORE BIT(11)
#define FEN_ELDR BIT(12)
#define FEN_DIO_RF BIT(13)
#define FEN_HWPDN BIT(14)
#define FEN_MREGEN BIT(15)
//2 APS_FSMCO
#define PFM_LDALL BIT(0)
#define PFM_ALDN BIT(1)
#define PFM_LDKP BIT(2)
#define PFM_WOWL BIT(3)
#define EnPDN BIT(4)
#define PDN_PL BIT(5)
#define APFM_ONMAC BIT(8)
#define APFM_OFF BIT(9)
#define APFM_RSM BIT(10)
#define AFSM_HSUS BIT(11)
#define AFSM_PCIE BIT(12)
#define APDM_MAC BIT(13)
#define APDM_HOST BIT(14)
#define APDM_HPDN BIT(15)
#define RDY_MACON BIT(16)
#define SUS_HOST BIT(17)
#define ROP_ALD BIT(20)
#define ROP_PWR BIT(21)
#define ROP_SPS BIT(22)
#define SOP_MRST BIT(25)
#define SOP_FUSE BIT(26)
#define SOP_ABG BIT(27)
#define SOP_AMB BIT(28)
#define SOP_RCK BIT(29)
#define SOP_A8M BIT(30)
#define XOP_BTCK BIT(31)
//2 SYS_CLKR
#define ANAD16V_EN BIT(0)
#define ANA8M BIT(1)
#define MACSLP BIT(4)
#define LOADER_CLK_EN BIT(5)
//2 9346CR
#define BOOT_FROM_EEPROM BIT(4)
#define EEPROM_EN BIT(5)
//2 RF_CTRL
#define RF_EN BIT(0)
#define RF_RSTB BIT(1)
#define RF_SDMRSTB BIT(2)
//2 LDOV12D_CTRL
#define LDV12_EN BIT(0)
#define LDV12_SDBY BIT(1)
#define LPLDO_HSM BIT(2)
#define LPLDO_LSM_DIS BIT(3)
#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
//2 EFUSE_TEST (For RTL8723 partially)
#define EF_TRPT BIT(7)
#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2
#define LDOE25_EN BIT(31)
#define EFUSE_SEL(x) (((x) & 0x3) << 8)
#define EFUSE_SEL_MASK 0x300
#define EFUSE_WIFI_SEL_0 0x0
#define EFUSE_BT_SEL_0 0x1
#define EFUSE_BT_SEL_1 0x2
#define EFUSE_BT_SEL_2 0x3
//2 8051FWDL
//2 MCUFWDL
#define MCUFWDL_EN BIT(0)
#define MCUFWDL_RDY BIT(1)
#define FWDL_ChkSum_rpt BIT(2)
#define MACINI_RDY BIT(3)
#define BBINI_RDY BIT(4)
#define RFINI_RDY BIT(5)
#define WINTINI_RDY BIT(6)
#define RAM_DL_SEL BIT(7)
#define ROM_DLEN BIT(19)
#define CPRST BIT(23)
//2 REG_SYS_CFG
#define XCLK_VLD BIT(0)
#define ACLK_VLD BIT(1)
#define UCLK_VLD BIT(2)
#define PCLK_VLD BIT(3)
#define PCIRSTB BIT(4)
#define V15_VLD BIT(5)
#define TRP_B15V_EN BIT(7)
#define SIC_IDLE BIT(8)
#define BD_MAC2 BIT(9)
#define BD_MAC1 BIT(10)
#define IC_MACPHY_MODE BIT(11)
#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15))
#define BT_FUNC BIT(16)
#define VENDOR_ID BIT(19)
#define PAD_HWPD_IDN BIT(22)
#define TRP_VAUX_EN BIT(23) // RTL ID
#define TRP_BT_EN BIT(24)
#define BD_PKG_SEL BIT(25)
#define BD_HCI_SEL BIT(26)
#define TYPE_ID BIT(27)
#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15
#define CHIP_VER_RTL_SHIFT 12
*/
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
/*
//2 Function Enable Registers
//2 CR 0x0100-0x0103
#define HCI_TXDMA_EN BIT(0)
#define HCI_RXDMA_EN BIT(1)
#define TXDMA_EN BIT(2)
#define RXDMA_EN BIT(3)
#define PROTOCOL_EN BIT(4)
#define SCHEDULE_EN BIT(5)
#define MACTXEN BIT(6)
#define MACRXEN BIT(7)
#define ENSWBCN BIT(8)
#define ENSEC BIT(9)
#define CALTMR_EN BIT(10) // 32k CAL TMR enable
// Network type
#define _NETTYPE(x) (((x) & 0x3) << 16)
#define MASK_NETTYPE 0x30000
#define NT_NO_LINK 0x0
#define NT_LINK_AD_HOC 0x1
#define NT_LINK_AP 0x2
#define NT_AS_AP 0x3
//2 PBP - Page Size Register 0x0104
#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
#define _PSRX_MASK 0xF
#define _PSTX_MASK 0xF0
#define _PSRX(x) (x)
#define _PSTX(x) ((x) << 4)
#define PBP_64 0x0
#define PBP_128 0x1
#define PBP_256 0x2
#define PBP_512 0x3
#define PBP_1024 0x4
//2 TX/RXDMA 0x010C
#define RXDMA_ARBBW_EN BIT(0)
#define RXSHFT_EN BIT(1)
#define RXDMA_AGG_EN BIT(2)
#define QS_VO_QUEUE BIT(8)
#define QS_VI_QUEUE BIT(9)
#define QS_BE_QUEUE BIT(10)
#define QS_BK_QUEUE BIT(11)
#define QS_MANAGER_QUEUE BIT(12)
#define QS_HIGH_QUEUE BIT(13)
#define HQSEL_VOQ BIT(0)
#define HQSEL_VIQ BIT(1)
#define HQSEL_BEQ BIT(2)
#define HQSEL_BKQ BIT(3)
#define HQSEL_MGTQ BIT(4)
#define HQSEL_HIQ BIT(5)
// For normal driver, 0x10C
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
#define QUEUE_LOW 1
#define QUEUE_NORMAL 2
#define QUEUE_HIGH 3
//2 REG_C2HEVT_CLEAR 0x01AF
#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message
#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver.
//2 LLT_INIT 0x01E0
#define _LLT_NO_ACTIVE 0x0
#define _LLT_WRITE_ACCESS 0x1
#define _LLT_READ_ACCESS 0x2
#define _LLT_INIT_DATA(x) ((x) & 0xFF)
#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
#define _LLT_OP(x) (((x) & 0x3) << 30)
#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
*/
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
/*
//2 TDECTL 0x0208
#define BLK_DESC_NUM_SHIFT 4
#define BLK_DESC_NUM_MASK 0xF
//2 TXDMA_OFFSET_CHK 0x020C
#define DROP_DATA_EN BIT(9)
*/
//-----------------------------------------------------
//
// 0x0280h ~ 0x028Bh RX DMA Configuration
//
//-----------------------------------------------------
/*
//2 REG_RXDMA_CONTROL, 0x0286h
// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before
// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear.
#define RXPKT_RELEASE_POLL BIT(0)
// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in
// this bit. FW can start releasing packets after RXDMA entering idle mode.
#define RXDMA_IDLE BIT(1)
// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host
// completed, and stop DMA packet to host. RXDMA will then report Default: 0;
#define RW_RELEASE_EN BIT(2)
*/
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
/*
//2 FWHW_TXQ_CTRL 0x0420
#define EN_AMPDU_RTY_NEW BIT(7)
//2 REG_LIFECTRL_CTRL 0x0426
#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3
#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2
#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1
#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0
#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim.
//2 SPEC SIFS 0x0428
#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
//2 RL 0x042A
#define RETRY_LIMIT_SHORT_SHIFT 8
#define RETRY_LIMIT_LONG_SHIFT 0
#define _LRL(x) ((x) & 0x3F)
#define _SRL(x) (((x) & 0x3F) << 8)
*/
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
/*
//2 EDCA setting 0x050C
#define AC_PARAM_TXOP_LIMIT_OFFSET 16
#define AC_PARAM_ECW_MAX_OFFSET 12
#define AC_PARAM_ECW_MIN_OFFSET 8
#define AC_PARAM_AIFS_OFFSET 0
//2 BCN_CTRL 0x0550
#define EN_TXBCN_RPT BIT(2)
#define EN_BCN_FUNCTION BIT(3)
//2 TxPause 0x0522
#define STOP_BCNQ BIT(6)
*/
//2 ACMHWCTRL 0x05C0
#define AcmHw_HwEn_8723D BIT(0)
#define AcmHw_VoqEn_8723D BIT(1)
#define AcmHw_ViqEn_8723D BIT(2)
#define AcmHw_BeqEn_8723D BIT(3)
#define AcmHw_VoqStatus_8723D BIT(5)
#define AcmHw_ViqStatus_8723D BIT(6)
#define AcmHw_BeqStatus_8723D BIT(7)
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
/*
//2 TCR 0x0604
#define DIS_GCLK BIT(1)
#define PAD_SEL BIT(2)
#define PWR_ST BIT(6)
#define PWRBIT_OW_EN BIT(7)
#define ACRC BIT(8)
#define CFENDFORM BIT(9)
#define ICV BIT(10)
*/
//----------------------------------------------------------------------------
// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits)
//----------------------------------------------------------------------------
/*
#define RCR_APPFCS BIT31 // WMAC append FCS after pauload
#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet.
#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet.
#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF
#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC.
#define RCR_RSVD_BIT26 BIT26 // Reserved
*/
#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload
/*#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries.
#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set.
#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response.
*/
#endif // #ifndef __INC_HAL8723DREG_H
hal/phydm/rtl8723d/halhwimg8723d_bb.c
+923
View File
@@ -0,0 +1,923 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.26*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8723D_SUPPORT == 1)
static BOOLEAN
CheckPositive(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2,
IN const u4Byte Condition3,
IN const u4Byte Condition4
)
{
u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
((pDM_Odm->BoardType & BIT2) >> 2) << 4 | /* _BT*/
((pDM_Odm->BoardType & BIT1) >> 1) << 5; /* _NGFF*/
u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4;
u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion;
u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType;
u4Byte driver1 = cut_version_for_para << 24 |
(pDM_Odm->SupportInterface & 0xF0) << 16 |
pDM_Odm->SupportPlatform << 16 |
pkg_type_for_para << 12 |
(pDM_Odm->SupportInterface & 0x0F) << 8 |
_BoardType;
u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 |
(pDM_Odm->TypeGPA & 0xFF) << 8 |
(pDM_Odm->TypeALNA & 0xFF) << 16 |
(pDM_Odm->TypeAPA & 0xFF) << 24;
u4Byte driver3 = 0;
u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 |
(pDM_Odm->TypeGPA & 0xFF00) |
(pDM_Odm->TypeALNA & 0xFF00) << 8 |
(pDM_Odm->TypeAPA & 0xFF00) << 16;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType));
/*============== Value Defined Check ===============*/
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return FALSE;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return FALSE;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u4Byte bitMask = 0;
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
return TRUE;
if ((cond1 & BIT0) != 0) /*GLNA*/
bitMask |= 0x000000FF;
if ((cond1 & BIT1) != 0) /*GPA*/
bitMask |= 0x0000FF00;
if ((cond1 & BIT2) != 0) /*ALNA*/
bitMask |= 0x00FF0000;
if ((cond1 & BIT3) != 0) /*APA*/
bitMask |= 0xFF000000;
if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/
return TRUE;
else
return FALSE;
} else
return FALSE;
}
static BOOLEAN
CheckNegative(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2
)
{
return TRUE;
}
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
u4Byte Array_MP_8723D_AGC_TAB[] = {
0xC78, 0xFE000101,
0xC78, 0xFD010101,
0xC78, 0xFC020101,
0xC78, 0xFB030101,
0xC78, 0xFA040101,
0xC78, 0xF9050101,
0xC78, 0xF8060101,
0xC78, 0xF7070101,
0xC78, 0xF6080101,
0xC78, 0xF5090101,
0xC78, 0xF40A0101,
0xC78, 0xF30B0101,
0xC78, 0xF20C0101,
0xC78, 0xF10D0101,
0xC78, 0xF00E0101,
0xC78, 0xEF0F0101,
0xC78, 0xEE100101,
0xC78, 0xED110101,
0xC78, 0xEC120101,
0xC78, 0xEB130101,
0xC78, 0xEA140101,
0xC78, 0xE9150101,
0xC78, 0xE8160101,
0xC78, 0xE7170101,
0xC78, 0xE6180101,
0xC78, 0xE5190101,
0xC78, 0xE41A0101,
0xC78, 0xE31B0101,
0xC78, 0xE21C0101,
0xC78, 0xE11D0101,
0xC78, 0xE01E0101,
0xC78, 0x861F0101,
0xC78, 0x85200101,
0xC78, 0x84210101,
0xC78, 0x83220101,
0xC78, 0x82230101,
0xC78, 0x81240101,
0xC78, 0x80250101,
0xC78, 0x44260101,
0xC78, 0x43270101,
0xC78, 0x42280101,
0xC78, 0x41290101,
0xC78, 0x402A0101,
0xC78, 0x022B0101,
0xC78, 0x012C0101,
0xC78, 0x002D0101,
0xC78, 0xC52E0001,
0xC78, 0xC42F0001,
0xC78, 0xC3300001,
0xC78, 0xC2310001,
0xC78, 0xC1320001,
0xC78, 0xC0330001,
0xC78, 0x04340001,
0xC78, 0x03350001,
0xC78, 0x02360001,
0xC78, 0x01370001,
0xC78, 0x00380001,
0xC78, 0x00390001,
0xC78, 0x003A0001,
0xC78, 0x003B0001,
0xC78, 0x003C0001,
0xC78, 0x003D0001,
0xC78, 0x003E0001,
0xC78, 0x003F0001,
0xC78, 0x6F002001,
0xC78, 0x6F012001,
0xC78, 0x6F022001,
0xC78, 0x6F032001,
0xC78, 0x6F042001,
0xC78, 0x6F052001,
0xC78, 0x6F062001,
0xC78, 0x6F072001,
0xC78, 0x6F082001,
0xC78, 0x6F092001,
0xC78, 0x6F0A2001,
0xC78, 0x6F0B2001,
0xC78, 0x6F0C2001,
0xC78, 0x6F0D2001,
0xC78, 0x6F0E2001,
0xC78, 0x6F0F2001,
0xC78, 0x6F102001,
0xC78, 0x6F112001,
0xC78, 0x6F122001,
0xC78, 0x6F132001,
0xC78, 0x6F142001,
0xC78, 0x6F152001,
0xC78, 0x6F162001,
0xC78, 0x6F172001,
0xC78, 0x6F182001,
0xC78, 0x6F192001,
0xC78, 0x6F1A2001,
0xC78, 0x6F1B2001,
0xC78, 0x6F1C2001,
0xC78, 0x6F1D2001,
0xC78, 0x6F1E2001,
0xC78, 0x6F1F2001,
0xC78, 0x6F202001,
0xC78, 0x6F212001,
0xC78, 0x6F222001,
0xC78, 0x6F232001,
0xC78, 0x6E242001,
0xC78, 0x6D252001,
0xC78, 0x6C262001,
0xC78, 0x6B272001,
0xC78, 0x6A282001,
0xC78, 0x69292001,
0xC78, 0x4B2A2001,
0xC78, 0x4A2B2001,
0xC78, 0x492C2001,
0xC78, 0x482D2001,
0xC78, 0x472E2001,
0xC78, 0x462F2001,
0xC78, 0x45302001,
0xC78, 0x44312001,
0xC78, 0x43322001,
0xC78, 0x42332001,
0xC78, 0x41342001,
0xC78, 0x40352001,
0xC78, 0x02362001,
0xC78, 0x01372001,
0xC78, 0x00382001,
0xC78, 0x00392001,
0xC78, 0x003A2001,
0xC78, 0x003B2001,
0xC78, 0x003C2001,
0xC78, 0x003D2001,
0xC78, 0x003E2001,
0xC78, 0x003F2001,
0xC78, 0x7F003101,
0xC78, 0x7F013101,
0xC78, 0x7F023101,
0xC78, 0x7F033101,
0xC78, 0x7F043101,
0xC78, 0x7F053101,
0xC78, 0x7F063101,
0xC78, 0x7F073101,
0xC78, 0x7E083101,
0xC78, 0x7D093101,
0xC78, 0x7C0A3101,
0xC78, 0x7B0B3101,
0xC78, 0x7A0C3101,
0xC78, 0x790D3101,
0xC78, 0x780E3101,
0xC78, 0x770F3101,
0xC78, 0x76103101,
0xC78, 0x75113101,
0xC78, 0x74123101,
0xC78, 0x73133101,
0xC78, 0x72143101,
0xC78, 0x71153101,
0xC78, 0x70163101,
0xC78, 0x6F173101,
0xC78, 0x6E183101,
0xC78, 0x6D193101,
0xC78, 0x6C1A3101,
0xC78, 0x6B1B3101,
0xC78, 0x6A1C3101,
0xC78, 0x691D3101,
0xC78, 0x681E3101,
0xC78, 0x4B1F3101,
0xC78, 0x4A203101,
0xC78, 0x49213101,
0xC78, 0x48223101,
0xC78, 0x47233101,
0xC78, 0x46243101,
0xC78, 0x45253101,
0xC78, 0x44263101,
0xC78, 0x43273101,
0xC78, 0x42283101,
0xC78, 0x41293101,
0xC78, 0x402A3101,
0xC78, 0x022B3101,
0xC78, 0x012C3101,
0xC78, 0x002D3101,
0xC78, 0x002E3101,
0xC78, 0x002F3101,
0xC78, 0x00303101,
0xC78, 0x00313101,
0xC78, 0x00323101,
0xC78, 0x00333101,
0xC78, 0x00343101,
0xC78, 0x00353101,
0xC78, 0x00363101,
0xC78, 0x00373101,
0xC78, 0x00383101,
0xC78, 0x00393101,
0xC78, 0x003A3101,
0xC78, 0x003B3101,
0xC78, 0x003C3101,
0xC78, 0x003D3101,
0xC78, 0x003E3101,
0xC78, 0x003F3101,
0xC78, 0xFE403101,
0xC78, 0xFD413101,
0xC78, 0xFC423101,
0xC78, 0xFB433101,
0xC78, 0xFA443101,
0xC78, 0xF9453101,
0xC78, 0xF8463101,
0xC78, 0xF7473101,
0xC78, 0xF6483101,
0xC78, 0xF5493101,
0xC78, 0xF44A3101,
0xC78, 0xF34B3101,
0xC78, 0xF24C3101,
0xC78, 0xF14D3101,
0xC78, 0xF04E3101,
0xC78, 0xEF4F3101,
0xC78, 0xEE503101,
0xC78, 0xED513101,
0xC78, 0xEC523101,
0xC78, 0xEB533101,
0xC78, 0xEA543101,
0xC78, 0xE9553101,
0xC78, 0xE8563101,
0xC78, 0xE7573101,
0xC78, 0xE6583101,
0xC78, 0xE5593101,
0xC78, 0xE45A3101,
0xC78, 0xE35B3101,
0xC78, 0xE25C3101,
0xC78, 0xE15D3101,
0xC78, 0xE05E3101,
0xC78, 0x865F3101,
0xC78, 0x85603101,
0xC78, 0x84613101,
0xC78, 0x83623101,
0xC78, 0x82633101,
0xC78, 0x81643101,
0xC78, 0x80653101,
0xC78, 0x80663101,
0xC78, 0x80673101,
0xC78, 0x80683101,
0xC78, 0x80693101,
0xC78, 0x806A3101,
0xC78, 0x806B3101,
0xC78, 0x806C3101,
0xC78, 0x806D3101,
0xC78, 0x806E3101,
0xC78, 0x806F3101,
0xC78, 0x80703101,
0xC78, 0x80713101,
0xC78, 0x80723101,
0xC78, 0x80733101,
0xC78, 0x80743101,
0xC78, 0x80753101,
0xC78, 0x80763101,
0xC78, 0x80773101,
0xC78, 0x80783101,
0xC78, 0x80793101,
0xC78, 0x807A3101,
0xC78, 0x807B3101,
0xC78, 0x807C3101,
0xC78, 0x807D3101,
0xC78, 0x807E3101,
0xC78, 0x807F3101,
0xC78, 0xEF402001,
0xC78, 0xEF412001,
0xC78, 0xEF422001,
0xC78, 0xEF432001,
0xC78, 0xEF442001,
0xC78, 0xEF452001,
0xC78, 0xEF462001,
0xC78, 0xEF472001,
0xC78, 0xEF482001,
0xC78, 0xEF492001,
0xC78, 0xEF4A2001,
0xC78, 0xEF4B2001,
0xC78, 0xEF4C2001,
0xC78, 0xEF4D2001,
0xC78, 0xEF4E2001,
0xC78, 0xEF4F2001,
0xC78, 0xEF502001,
0xC78, 0xEF512001,
0xC78, 0xEF522001,
0xC78, 0xEF532001,
0xC78, 0xEF542001,
0xC78, 0xEF552001,
0xC78, 0xEF562001,
0xC78, 0xEF572001,
0xC78, 0xEF582001,
0xC78, 0xEF592001,
0xC78, 0xEF5A2001,
0xC78, 0xEF5B2001,
0xC78, 0xEF5C2001,
0xC78, 0xEF5D2001,
0xC78, 0xEF5E2001,
0xC78, 0xEF5F2001,
0xC78, 0xEF602001,
0xC78, 0xEE612001,
0xC78, 0xED622001,
0xC78, 0xEC632001,
0xC78, 0xEB642001,
0xC78, 0xEA652001,
0xC78, 0xE9662001,
0xC78, 0xE8672001,
0xC78, 0xCB682001,
0xC78, 0xCA692001,
0xC78, 0xC96A2001,
0xC78, 0xC86B2001,
0xC78, 0xC76C2001,
0xC78, 0xC66D2001,
0xC78, 0xC56E2001,
0xC78, 0xC46F2001,
0xC78, 0xC3702001,
0xC78, 0xC2712001,
0xC78, 0xC1722001,
0xC78, 0xC0732001,
0xC78, 0x82742001,
0xC78, 0x81752001,
0xC78, 0x80762001,
0xC78, 0x80772001,
0xC78, 0x80782001,
0xC78, 0x80792001,
0xC78, 0x807A2001,
0xC78, 0x807B2001,
0xC78, 0x807C2001,
0xC78, 0x807D2001,
0xC78, 0x807E2001,
0xC78, 0x807F2001,
0xC78, 0xFA001101,
0xC78, 0xF9011101,
0xC78, 0xF8021101,
0xC78, 0xF7031101,
0xC78, 0xF6041101,
0xC78, 0xF5051101,
0xC78, 0xF4061101,
0xC78, 0xD7071101,
0xC78, 0xD6081101,
0xC78, 0xD5091101,
0xC78, 0xD40A1101,
0xC78, 0x970B1101,
0xC78, 0x960C1101,
0xC78, 0x950D1101,
0xC78, 0x940E1101,
0xC78, 0x930F1101,
0xC78, 0x92101101,
0xC78, 0x91111101,
0xC78, 0x90121101,
0xC78, 0x8F131101,
0xC78, 0x8E141101,
0xC78, 0x8D151101,
0xC78, 0x8C161101,
0xC78, 0x8B171101,
0xC78, 0x8A181101,
0xC78, 0x89191101,
0xC78, 0x881A1101,
0xC78, 0x871B1101,
0xC78, 0x861C1101,
0xC78, 0x851D1101,
0xC78, 0x841E1101,
0xC78, 0x831F1101,
0xC78, 0x82201101,
0xC78, 0x81211101,
0xC78, 0x80221101,
0xC78, 0x43231101,
0xC78, 0x42241101,
0xC78, 0x41251101,
0xC78, 0x04261101,
0xC78, 0x03271101,
0xC78, 0x02281101,
0xC78, 0x01291101,
0xC78, 0x002A1101,
0xC78, 0xC42B1001,
0xC78, 0xC32C1001,
0xC78, 0xC22D1001,
0xC78, 0xC12E1001,
0xC78, 0xC02F1001,
0xC78, 0x85301001,
0xC78, 0x84311001,
0xC78, 0x83321001,
0xC78, 0x82331001,
0xC78, 0x81341001,
0xC78, 0x80351001,
0xC78, 0x05361001,
0xC78, 0x04371001,
0xC78, 0x03381001,
0xC78, 0x02391001,
0xC78, 0x013A1001,
0xC78, 0x003B1001,
0xC78, 0x003C1001,
0xC78, 0x003D1001,
0xC78, 0x003E1001,
0xC78, 0x003F1001,
0xC50, 0x69553422,
0xC50, 0x69553420,
};
void
ODM_ReadAndConfig_MP_8723D_AGC_TAB(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte i = 0;
u1Byte cCond;
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
u4Byte ArrayLen = sizeof(Array_MP_8723D_AGC_TAB)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8723D_AGC_TAB;
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_AGC_TAB\n"));
while ((i + 1) < ArrayLen) {
v1 = Array[i];
v2 = Array[i + 1];
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
if (v1 & BIT31) {/* positive condition*/
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
if (cCond == COND_ENDIF) {/*end*/
bMatched = TRUE;
bSkipped = FALSE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (cCond == COND_ELSE) { /*else*/
bMatched = bSkipped?FALSE:TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT30) { /*negative condition*/
if (bSkipped == FALSE) {
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
bMatched = TRUE;
bSkipped = TRUE;
} else {
bMatched = FALSE;
bSkipped = FALSE;
}
} else
bMatched = FALSE;
}
} else {
if (bMatched)
odm_ConfigBB_AGC_8723D(pDM_Odm, v1, bMaskDWord, v2);
}
i = i + 2;
}
}
u4Byte
ODM_GetVersion_MP_8723D_AGC_TAB(void)
{
return 31;
}
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
u4Byte Array_MP_8723D_PHY_REG[] = {
0x800, 0x80046C00,
0x804, 0x00000003,
0x808, 0x0000FC00,
0x80C, 0x0000000A,
0x810, 0x10001331,
0x814, 0x020C3D10,
0x818, 0x00200385,
0x81C, 0x00000000,
0x820, 0x01000100,
0x824, 0x00390204,
0x828, 0x00000000,
0x82C, 0x00000000,
0x830, 0x00000000,
0x834, 0x00000000,
0x838, 0x00000000,
0x83C, 0x00000000,
0x840, 0x00010000,
0x844, 0x00000000,
0x848, 0x00000000,
0x84C, 0x00000000,
0x850, 0x00000000,
0x854, 0x00000000,
0x858, 0x569A11A9,
0x85C, 0x01000014,
0x860, 0x66F60110,
0x864, 0x461F0641,
0x868, 0x00000000,
0x86C, 0x27272700,
0x870, 0x07000460,
0x874, 0x25004000,
0x878, 0x00000808,
0x87C, 0x004F0201,
0x880, 0xB2002E12,
0x884, 0x00000007,
0x888, 0x00000000,
0x88C, 0xCCC000C0,
0x890, 0x00000800,
0x894, 0xFFFFFFFE,
0x898, 0x40302010,
0x89C, 0x00706050,
0x900, 0x00000000,
0x904, 0x00000023,
0x908, 0x00000000,
0x90C, 0x81121111,
0x910, 0x00000402,
0x914, 0x00000300,
0x920, 0x18C6318C,
0x924, 0x0000018C,
0x948, 0x99000000,
0x94C, 0x00000010,
0x950, 0x00003800,
0x954, 0x5A380000,
0x958, 0x4BC6D87A,
0x95C, 0x04EB9B79,
0x96C, 0x00000003,
0x970, 0x00000000,
0x974, 0x00000000,
0x978, 0x00000000,
0x97C, 0x13000000,
0x980, 0x00000000,
0xA00, 0x00D047C8,
0xA04, 0x80FF800C,
0xA08, 0x8C838300,
0xA0C, 0x2E20100F,
0xA10, 0x9500BB78,
0xA14, 0x1114D028,
0xA18, 0x00881117,
0xA1C, 0x89140F00,
0xA20, 0xE82C0001,
0xA24, 0x64B80C1C,
0xA28, 0x00008810,
0xA2C, 0x00D30000,
0xA70, 0x101FBF00,
0xA74, 0x00000007,
0xA78, 0x00008900,
0xA7C, 0x225B0606,
0xA80, 0x2180FA74,
0xA84, 0x00200000,
0xA88, 0x040C0000,
0xA8C, 0x12345678,
0xA90, 0xABCDEF00,
0xA94, 0x001B1B89,
0xA98, 0x00000000,
0xA9C, 0x00020000,
0xAA0, 0x00000000,
0xAA4, 0x0000000C,
0xAA8, 0xCA100008,
0xAAC, 0x01235667,
0xAB0, 0x00000000,
0xAB4, 0x20201402,
0xB2C, 0x00000000,
0xC00, 0x48071D40,
0xC04, 0x03A05611,
0xC08, 0x000000E4,
0xC0C, 0x6C6C6C6C,
0xC10, 0x28800000,
0xC14, 0x40000100,
0xC18, 0x08800000,
0xC1C, 0x40000100,
0xC20, 0x00000000,
0xC24, 0x00000000,
0xC28, 0x00000000,
0xC2C, 0x00000000,
0xC30, 0x69E9AC48,
0xC34, 0x31000040,
0xC38, 0x21688080,
0xC3C, 0x000016D4,
0xC40, 0x1F78403F,
0xC44, 0x00010036,
0xC48, 0xEC020107,
0xC4C, 0x007F037F,
0xC50, 0x69553420,
0xC54, 0x43BC0094,
0xC58, 0x00015969,
0xC5C, 0x00310492,
0xC60, 0x00280A00,
0xC64, 0x7112848B,
0xC68, 0x47C074FF,
0xC6C, 0x00000036,
0xC70, 0x2C7F000D,
0xC74, 0x020600DB,
0xC78, 0x0000001F,
0xC7C, 0x00B91612,
0xC80, 0x390000E4,
0xC84, 0x11F60000,
0xC88, 0x40000100,
0xC8C, 0x20200000,
0xC90, 0x00091521,
0xC94, 0x00000000,
0xC98, 0x00121820,
0xC9C, 0x00007F7F,
0xCA0, 0x00012000,
0xCA4, 0xA00000A0,
0xCA8, 0x85E7C606,
0xCAC, 0x00000060,
0xCB0, 0x00000000,
0xCB4, 0x00000000,
0xCB8, 0x00000000,
0xCBC, 0x28000000,
0xCC0, 0x0010A3D0,
0xCC4, 0x00000F7D,
0xCC8, 0x000442D6,
0xCCC, 0x00000000,
0xCD0, 0x000001C8,
0xCD4, 0x001C8000,
0xCD8, 0x00000100,
0xCDC, 0x40100000,
0xCE0, 0x00222220,
0xCE4, 0x20000000,
0xCE8, 0x37644302,
0xCEC, 0x2F97D40C,
0xD00, 0x00030740,
0xD04, 0x40020401,
0xD08, 0x0000907F,
0xD0C, 0x20010201,
0xD10, 0xA0633333,
0xD14, 0x3333BC53,
0xD18, 0x7A8F5B6F,
0xD2C, 0xCC979975,
0xD30, 0x00000000,
0xD34, 0x80608000,
0xD38, 0x88000000,
0xD3C, 0xC0127343,
0xD40, 0x00000000,
0xD44, 0x00000000,
0xD48, 0x00000000,
0xD4C, 0x00000000,
0xD50, 0x00000038,
0xD54, 0x00000000,
0xD58, 0x00000282,
0xD5C, 0x30032064,
0xD60, 0x4653DE68,
0xD64, 0x04518A3C,
0xD68, 0x00002101,
0xE00, 0x2D2D2D2D,
0xE04, 0x2D2D2D2D,
0xE08, 0x0390272D,
0xE10, 0x2D2D2D2D,
0xE14, 0x2D2D2D2D,
0xE18, 0x2D2D2D2D,
0xE1C, 0x2D2D2D2D,
0xE28, 0x00000000,
0xE30, 0x1000DC1F,
0xE34, 0x10008C1F,
0xE38, 0x02140102,
0xE3C, 0x681604C2,
0xE40, 0x01007C00,
0xE44, 0x01004800,
0xE48, 0xFB000000,
0xE4C, 0x000028D1,
0xE50, 0x1000DC1F,
0xE54, 0x10008C1F,
0xE58, 0x02140102,
0xE5C, 0x28160D05,
0xE60, 0x00000008,
0xE68, 0x001B25A4,
0xE6C, 0x01C00014,
0xE70, 0x01C00016,
0xE74, 0x02000014,
0xE78, 0x02000014,
0xE7C, 0x02000014,
0xE80, 0x02000014,
0xE84, 0x01C00014,
0xE88, 0x02000014,
0xE8C, 0x01C00014,
0xED0, 0x01C00014,
0xED4, 0x01C00014,
0xED8, 0x01C00014,
0xEDC, 0x00000014,
0xEE0, 0x00000014,
0xEE8, 0x21555448,
0xEEC, 0x03C00014,
0xF14, 0x00000003,
0xF00, 0x00100300,
0xF08, 0x0000800B,
0xF0C, 0x0000F007,
0xF10, 0x0000A487,
0xF1C, 0x80000064,
0xF38, 0x00030155,
0xF3C, 0x0000003A,
0xF4C, 0x13000000,
0xF50, 0x00000000,
0xF18, 0x00000000,
};
void
ODM_ReadAndConfig_MP_8723D_PHY_REG(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte i = 0;
u1Byte cCond;
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
u4Byte ArrayLen = sizeof(Array_MP_8723D_PHY_REG)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8723D_PHY_REG;
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_PHY_REG\n"));
while ((i + 1) < ArrayLen) {
v1 = Array[i];
v2 = Array[i + 1];
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
if (v1 & BIT31) {/* positive condition*/
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
if (cCond == COND_ENDIF) {/*end*/
bMatched = TRUE;
bSkipped = FALSE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (cCond == COND_ELSE) { /*else*/
bMatched = bSkipped?FALSE:TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT30) { /*negative condition*/
if (bSkipped == FALSE) {
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
bMatched = TRUE;
bSkipped = TRUE;
} else {
bMatched = FALSE;
bSkipped = FALSE;
}
} else
bMatched = FALSE;
}
} else {
if (bMatched)
odm_ConfigBB_PHY_8723D(pDM_Odm, v1, bMaskDWord, v2);
}
i = i + 2;
}
}
u4Byte
ODM_GetVersion_MP_8723D_PHY_REG(void)
{
return 31;
}
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
u4Byte Array_MP_8723D_PHY_REG_PG[] = {
0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,
0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,
0, 0, 0, 0x00000e00, 0xffffffff, 0x32343434,
0, 0, 0, 0x00000e04, 0xffffffff, 0x28303032,
0, 0, 0, 0x00000e10, 0xffffffff, 0x30323234,
0, 0, 0, 0x00000e14, 0xffffffff, 0x26282830
};
void
ODM_ReadAndConfig_MP_8723D_PHY_REG_PG(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte i = 0;
u4Byte ArrayLen = sizeof(Array_MP_8723D_PHY_REG_PG)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8723D_PHY_REG_PG;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT);
pHalData->nLinesReadPwrByRate = ArrayLen/6;
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_PHY_REG_PG\n"));
pDM_Odm->PhyRegPgVersion = 1;
pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE;
for (i = 0; i < ArrayLen; i += 6) {
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u4Byte v3 = Array[i+2];
u4Byte v4 = Array[i+3];
u4Byte v5 = Array[i+4];
u4Byte v6 = Array[i+5];
odm_ConfigBB_PHY_REG_PG_8723D(pDM_Odm, v1, v2, v3, v4, v5, v6);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
(v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6);
#endif
}
}
#endif /* end of HWIMG_SUPPORT*/
hal/phydm/rtl8723d/halhwimg8723d_bb.h
+59
View File
@@ -0,0 +1,59 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.26*/
#if (RTL8723D_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8723D_H
#define __INC_MP_BB_HW_IMG_8723D_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_AGC_TAB(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_PHY_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_PHY_REG(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_PHY_REG_PG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
hal/phydm/rtl8723d/halhwimg8723d_fw.c
+4840
View File
File diff suppressed because it is too large Load Diff
hal/phydm/rtl8723d/halhwimg8723d_fw.h
+62
View File
@@ -0,0 +1,62 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.16*/
#if (RTL8723D_SUPPORT == 1)
#ifndef __INC_MP_FW_HW_IMG_8723D_H
#define __INC_MP_FW_HW_IMG_8723D_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8723D_FW_AP(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8723D_FW_NIC(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8723D_FW_WoWLAN(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
#endif
#endif /* end of HWIMG_SUPPORT*/
hal/phydm/rtl8723d/halhwimg8723d_mac.c
+301
View File
@@ -0,0 +1,301 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.26*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8723D_SUPPORT == 1)
static BOOLEAN
CheckPositive(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2,
IN const u4Byte Condition3,
IN const u4Byte Condition4
)
{
u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
((pDM_Odm->BoardType & BIT2) >> 2) << 4 | /* _BT*/
((pDM_Odm->BoardType & BIT1) >> 1) << 5; /* _NGFF*/
u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4;
u1Byte cut_version_for_para = (pDM_Odm->CutVersion == ODM_CUT_A) ? 15 : pDM_Odm->CutVersion;
u1Byte pkg_type_for_para = (pDM_Odm->PackageType == 0) ? 15 : pDM_Odm->PackageType;
u4Byte driver1 = cut_version_for_para << 24 |
(pDM_Odm->SupportInterface & 0xF0) << 16 |
pDM_Odm->SupportPlatform << 16 |
pkg_type_for_para << 12 |
(pDM_Odm->SupportInterface & 0x0F) << 8 |
_BoardType;
u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 |
(pDM_Odm->TypeGPA & 0xFF) << 8 |
(pDM_Odm->TypeALNA & 0xFF) << 16 |
(pDM_Odm->TypeAPA & 0xFF) << 24;
u4Byte driver3 = 0;
u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 |
(pDM_Odm->TypeGPA & 0xFF00) |
(pDM_Odm->TypeALNA & 0xFF00) << 8 |
(pDM_Odm->TypeAPA & 0xFF00) << 16;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType));
/*============== Value Defined Check ===============*/
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return FALSE;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return FALSE;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u4Byte bitMask = 0;
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
return TRUE;
if ((cond1 & BIT0) != 0) /*GLNA*/
bitMask |= 0x000000FF;
if ((cond1 & BIT1) != 0) /*GPA*/
bitMask |= 0x0000FF00;
if ((cond1 & BIT2) != 0) /*ALNA*/
bitMask |= 0x00FF0000;
if ((cond1 & BIT3) != 0) /*APA*/
bitMask |= 0xFF000000;
if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/
return TRUE;
else
return FALSE;
} else
return FALSE;
}
static BOOLEAN
CheckNegative(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2
)
{
return TRUE;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u4Byte Array_MP_8723D_MAC_REG[] = {
0x020, 0x00000013,
0x02F, 0x00000010,
0x077, 0x00000007,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x00000000,
0x446, 0x00000000,
0x447, 0x00000000,
0x448, 0x00000000,
0x449, 0x000000F0,
0x44A, 0x0000000F,
0x44B, 0x0000003E,
0x44C, 0x00000010,
0x44D, 0x00000000,
0x44E, 0x00000000,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x000000F0,
0x452, 0x0000000F,
0x453, 0x00000000,
0x456, 0x0000005E,
0x460, 0x00000066,
0x461, 0x00000066,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000028,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000028,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000C,
0x63F, 0x0000000C,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66A, 0x000000B0,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
0x765, 0x00000018,
0x76E, 0x00000004,
0x7C0, 0x00000038,
0x7C2, 0x0000000F,
0x7C3, 0x000000C0,
0x073, 0x00000004,
0x7C4, 0x00000077,
0x07C, 0x00000003,
0x016, 0x000000B3,
};
void
ODM_ReadAndConfig_MP_8723D_MAC_REG(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte i = 0;
u1Byte cCond;
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
u4Byte ArrayLen = sizeof(Array_MP_8723D_MAC_REG)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8723D_MAC_REG;
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8723D_MAC_REG\n"));
while ((i + 1) < ArrayLen) {
v1 = Array[i];
v2 = Array[i + 1];
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
if (v1 & BIT31) {/* positive condition*/
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
if (cCond == COND_ENDIF) {/*end*/
bMatched = TRUE;
bSkipped = FALSE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (cCond == COND_ELSE) { /*else*/
bMatched = bSkipped?FALSE:TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT30) { /*negative condition*/
if (bSkipped == FALSE) {
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
bMatched = TRUE;
bSkipped = TRUE;
} else {
bMatched = FALSE;
bSkipped = FALSE;
}
} else
bMatched = FALSE;
}
} else {
if (bMatched)
odm_ConfigMAC_8723D(pDM_Odm, v1, (u1Byte)v2);
}
i = i + 2;
}
}
u4Byte
ODM_GetVersion_MP_8723D_MAC_REG(void)
{
return 31;
}
#endif /* end of HWIMG_SUPPORT*/
hal/phydm/rtl8723d/halhwimg8723d_mac.h
+39
View File
@@ -0,0 +1,39 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.26*/
#if (RTL8723D_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8723D_H
#define __INC_MP_MAC_HW_IMG_8723D_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_MAC_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_MAC_REG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
hal/phydm/rtl8723d/halhwimg8723d_rf.c
+1199
View File
File diff suppressed because it is too large Load Diff
hal/phydm/rtl8723d/halhwimg8723d_rf.h
+89
View File
@@ -0,0 +1,89 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.26*/
#if (RTL8723D_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8723D_H
#define __INC_MP_RF_HW_IMG_8723D_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_RadioA(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_RadioA(void);
/******************************************************************************
* TxPowerTrack_PCIE.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_PCIE(void);
/******************************************************************************
* TxPowerTrack_SDIO.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_SDIO(void);
/******************************************************************************
* TxPowerTrack_USB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_TxPowerTrack_USB(void);
/******************************************************************************
* TXPWR_LMT.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_TXPWR_LMT(void);
/******************************************************************************
* TxXtalTrack.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8723D_TxXtalTrack(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8723D_TxXtalTrack(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
hal/phydm/rtl8723d/halphyrf_8723d.c
+4101
View File
File diff suppressed because it is too large Load Diff
hal/phydm/rtl8723d/halphyrf_8723d.h
+153
View File
@@ -0,0 +1,153 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8723D_H__
#define __HAL_PHY_RF_8723D_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_8723D 10 //ms
#define index_mapping_NUM_8723D 15
#define AVG_THERMAL_NUM_8723D 4
#define RF_T_METER_8723D 0x42
void ConfigureTxpowerTrack_8723D(
PTXPWRTRACK_CFG pConfig
);
VOID
GetDeltaSwingTable_8723D(
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
PVOID pDM_VOID,
#else
IN PDM_ODM_T pDM_Odm,
#endif
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
);
VOID
setCCKFilterCoefficient_8723D(
PDM_ODM_T pDM_Odm,
u1Byte CCKSwingIndex
);
void DoIQK_8723D(
PVOID pDM_VOID,
u1Byte DeltaThermalIndex,
u1Byte ThermalValue,
u1Byte Threshold
);
VOID
ODM_TxPwrTrackSetPwr_8723D(
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
PVOID pDM_VOID,
#else
IN PDM_ODM_T pDM_Odm,
#endif
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
);
VOID
ODM_TxXtalTrackSetXtal_8723D(
PVOID pDM_VOID
);
//1 7. IQK
void
PHY_IQCalibrate_8723D(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER Adapter,
#endif
IN BOOLEAN bReCovery);
//
// LC calibrate
//
void
PHY_LCCalibrate_8723D(
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
PVOID pDM_VOID
#else
IN PDM_ODM_T pDM_Odm
#endif
);
//
// AP calibrate
//
void
PHY_APCalibrate_8723D(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta);
void
PHY_DigitalPredistortion_8723D( IN PADAPTER pAdapter);
VOID
_PHY_SaveADDARegisters_8723D(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn_8723D(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
VOID
_PHY_MACSettingCalibration_8723D(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
#endif // #ifndef __HAL_PHY_RF_8723D_H__
hal/phydm/rtl8723d/phydm_regconfig8723d.c
+189
View File
@@ -0,0 +1,189 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8723D_SUPPORT == 1)
void
odm_ConfigRFReg_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
)
{
if(Addr == 0xfe || Addr == 0xffe)
{
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else
{
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
}
}
void
odm_ConfigRF_RadioA_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1000; // RF_Content: radioa_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8723D(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
}
void
odm_ConfigRF_RadioB_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8723D(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigMAC_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
)
{
ODM_Write1Byte(pDM_Odm, Addr, Data);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_AGC_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_PHY_REG_PG_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Band,
IN u4Byte RfPath,
IN u4Byte TxNum,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe || Addr == 0xffe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else
{
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
#endif
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
}
void
odm_ConfigBB_PHY_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
/*DbgPrint("odm_ConfigBB_PHY_8723D(), Addr = 0x%x, data = 0x%x\n", Addr, Data);*/
if (Addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (Addr == 0xfd)
ODM_delay_ms(5);
else if (Addr == 0xfc)
ODM_delay_ms(1);
else if (Addr == 0xfb)
ODM_delay_us(50);
else if (Addr == 0xfa)
ODM_delay_us(5);
else if (Addr == 0xf9)
ODM_delay_us(1);
else
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
}
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_TXPWR_LMT_8723D(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte Regulation,
IN pu1Byte Band,
IN pu1Byte Bandwidth,
IN pu1Byte RateSection,
IN pu1Byte RfPath,
IN pu1Byte Channel,
IN pu1Byte PowerLimit
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
Bandwidth, RateSection, RfPath, Channel, PowerLimit);
#endif
}
#endif
hal/phydm/rtl8723d/phydm_regconfig8723d.h
+98
View File
@@ -0,0 +1,98 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8723D
#define __INC_ODM_REGCONFIG_H_8723D
#if (RTL8723D_SUPPORT == 1)
void
odm_ConfigRFReg_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
);
void
odm_ConfigRF_RadioA_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
odm_ConfigRF_RadioB_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
odm_ConfigMAC_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
);
void
odm_ConfigBB_AGC_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_REG_PG_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Band,
IN u4Byte RfPath,
IN u4Byte TxNum,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_8723D(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_TXPWR_LMT_8723D(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte Regulation,
IN pu1Byte Band,
IN pu1Byte Bandwidth,
IN pu1Byte RateSection,
IN pu1Byte RfPath,
IN pu1Byte Channel,
IN pu1Byte PowerLimit
);
#endif
#endif // end of SUPPORT
hal/phydm/rtl8723d/phydm_rtl8723d.c
+68
View File
@@ -0,0 +1,68 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*============================================================
include files
============================================================*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8723D_SUPPORT == 1)
s1Byte
odm_CCKRSSI_8723D(
IN u1Byte LNA_idx,
IN u1Byte VGA_idx
)
{
s1Byte rx_pwr_all = 0x00;
switch (LNA_idx) {
case 0xf:
rx_pwr_all = -46 - (2 * VGA_idx);
break;
case 0xa:
rx_pwr_all = -20 - (2 * VGA_idx);
break;
case 7:
rx_pwr_all = -10 - (2 * VGA_idx);
break;
case 4:
rx_pwr_all = 4 - (2 * VGA_idx);
break;
default:
break;
}
return rx_pwr_all;
}
#endif
hal/phydm/rtl8723d/phydm_rtl8723d.h
+33
View File
@@ -0,0 +1,33 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8723D_H__
#define __ODM_RTL8723D_H__
#if (RTL8723D_SUPPORT == 1)
s1Byte
odm_CCKRSSI_8723D(
IN u1Byte LNA_idx,
IN u1Byte VGA_idx
);
#endif
#endif
hal/phydm/rtl8723d/version_rtl8723d.h
+5
View File
@@ -0,0 +1,5 @@
/*RTL8723D PHY Parameters*/
#define SVN_COMMIT_VERSION_8723D 22597
#define RELEASE_DATE_8723D 20161209
#define COMMIT_BY_8723D "BB_Jessica"
#define RELEASE_VERSION_8723D 31