From 9a3236e6842ef7ccae50dd5a7532c5741a08f692 Mon Sep 17 00:00:00 2001
From: Ubuntu <owen@iris.easytarget.org>
Date: Sun, 28 Apr 2024 22:20:47 +0000
Subject: [PATCH] working dts and bt

---
 bt-fw/rtl8723ds_config.bin              |  Bin 0 -> 47 bytes
 bt-fw/rtl8723ds_fw.bin                  |  Bin 0 -> 48988 bytes
 dts/README.md                           |   39 +
 dts/bake.sh                             |    4 +
 dts/dtspp/dtb-6.8.0-31-mqpro            |  Bin 0 -> 19857 bytes
 dts/dtspp/sun20i-common-regulators.dtsi |   32 +
 dts/dtspp/sun20i-d1-mangopi-mq-pro.dts  | 1315 +++++++++++++++++++++++
 dts/dtspp/sun20i-d1.dtsi                | 1141 ++++++++++++++++++++
 dts/dtspp/sun20i-d1s.dtsi               | 1058 ++++++++++++++++++
 dts/dtspp/sunxi-d1-t113.dtsi            |   19 +
 dts/dtspp/sunxi-d1s-t113.dtsi           |  940 ++++++++++++++++
 ubuntu.24.04.pinctrl.txt                |   90 --
 ubuntu.24.04.pins.txt                   |  224 ----
 13 files changed, 4548 insertions(+), 314 deletions(-)
 create mode 100644 bt-fw/rtl8723ds_config.bin
 create mode 100644 bt-fw/rtl8723ds_fw.bin
 create mode 100644 dts/README.md
 create mode 100755 dts/bake.sh
 create mode 100644 dts/dtspp/dtb-6.8.0-31-mqpro
 create mode 100644 dts/dtspp/sun20i-common-regulators.dtsi
 create mode 100644 dts/dtspp/sun20i-d1-mangopi-mq-pro.dts
 create mode 100644 dts/dtspp/sun20i-d1.dtsi
 create mode 100644 dts/dtspp/sun20i-d1s.dtsi
 create mode 100644 dts/dtspp/sunxi-d1-t113.dtsi
 create mode 100644 dts/dtspp/sunxi-d1s-t113.dtsi
 delete mode 100644 ubuntu.24.04.pinctrl.txt
 delete mode 100644 ubuntu.24.04.pins.txt

diff --git a/bt-fw/rtl8723ds_config.bin b/bt-fw/rtl8723ds_config.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a08fa3a9f8f6cbab10ad4584a36703336168df07
GIT binary patch
literal 47
zcmWGtt=z83@P&bq@f!nEBf~ESCZPr%1_7pqNh|?JUr9cc{<}V&aS8WL21foT42&EA
DU1<)g

literal 0
HcmV?d00001

diff --git a/bt-fw/rtl8723ds_fw.bin b/bt-fw/rtl8723ds_fw.bin
new file mode 100644
index 0000000000000000000000000000000000000000..4c323a3d92dcd21e0481492819c656b9d4996b90
GIT binary patch
literal 48988
zcmd44349b)wm)9gTRKT6sWbr^2+-+-EeQ%qz+DRn$kI_{L?eq+O$ZgbtAhqqT+jk>
zo!~R<viO=#KnTHs?gah4-}qin2h@?^gAfo==S3DL>Fz)W5gf;v{(Vn%Itl13@ArG}
z{r}15R^7UF>(;HioO{l>-*b9asZCl|T2l5)ael3uVHp*pW~Oq_-MapXF$}}_IEIm@
zA=3T#=MwFL5gvZa2=By#RR!{q;a=HPoWma(<{j=4&J6E5jzD~bH+me2_()G{xYXSm
zUhNk0*92R`FT3Rexxg7}4U2B(Dy5n0*8~?7w1yY@Tf;B;nX3!(SK&&;)yw{Y-a#m1
zP}eaX@pNzWI2iH4UOH+wF_+XOOljeMPJW0n$`2wOsO98vf>GYEgOh*6`NF%LEOAD8
z0M0)ejPi;aPR@!q$^!D@1LZY)IJrh|lyAeC!~M7LTvnn{K8k!zNZ*d@I^;iIhijZ8
z*M>TzkZhGg%(v`3se`d=ZE{hhNa~2pFBZ*hOes@p@{E&&&Q*Rhj;sA?IKJfXi{s1w
z0vuoQC*k<2f0o2JgwEIePvEM=FLc@weuW?*I1$PbmLNQa@Hj#R!csrIf$EO4o#K2Q
zdqrK*&t^dX*e1qhraP7g61>L1v~vmGk~0atQngB|4yp94Db6VKOVBQEPEJSs@pm}+
z(zT&>jkhwu=ka;YfZA(r<G-Lb`i+a(&)C&o{)m!x<i6!bc{&1PpPH|)fBZbY<IA{)
z!h)&`LK8b(X`w*EoK73nPlJ592tSs@EzliH@kGih+uo`*o2CrWXd@LV!U}Qf-sC`H
zcI##R^x`(X$JjQZwKY7=#m*@fS&p&CZPLBTT+)>6eiHp#Wt9I^62CxyJnmRzF;h0&
z>#B}OhLHAzY^oZmIjPy8UAHg5H=-<iahn<6yZCHtc&eMN=ws954faku$JZuX^!bD8
zo#%zEbAxR5g*IbgQadX=Afncbt?leoobA@OgyQ42$m5J%B}DAG0j{2J;=D-~*WUNe
z`mR+MywS1lg8IQY8|yUGyPEhTDvsaFH^pz#SH+>O+7cGuOLe91rtdFA;1MPwMB4#x
zDKmtktuQcqzF1bP)H#@>^iga0P0X8}ZpL)-5>p!Ql{-1fwO8X<7%+4=I~dcXDTa<%
zyU=^yWSN6BM>WT&+{!lQvQeU3`$gt*T6e5pcg)lk({9qBzUq?iOHvjjA5WsE7ps;v
zwU4(kR}9+|PBNwolM_GVPbX|h+%$P-Kg-meGFo!>&TSPs8|&!rF^5<9pW3PC9zqIQ
z!(miXmhVjU2>$uv*iTl7D!Vy6xzYSB#%lO{<IE$vlZl>HTjDmxuhnm2Ob=Kz&1#M@
zE!%%wOxcuNm4w>pF`ucg8MM_rbF{ztZOp8J0&CYar+Bo@wmM~;N>bnlr|&zqyyjcO
z60@o130<?^8<AuuU%j`ZGO#azaoiZciM3OYFr_n%I{5>PV;Vmyl$3;$l02-0GCDbw
zk+ekDOr^v%$9v;JTjIU?FeC9>*97=4;z4I(Wn7H-n6Ilj`D4%&niriVgBPS9A9O5Y
zuM9Abgy!cxO!}v0!N0<*5{1s(>gPO|(Oac}#=<%hPZ&<<xSV$1HOpAWX*iyEa+#-a
z3)j31?e?UbUE0^SS(zDnEtmb3_}IJ3oCub8jfr2nH4Z7DMmeQu-^CuGHpQMYmqw@*
z5WTD<H@+z{=_k#7n+2~qTwiStZ$x;adYHJTeZUE4`!Bt%)en1x>XehF7UPL|h()Bn
zYg13m^}6<!ij_h2=tsQ5-pb%3^)!mimzi?8&Jg-E#LjzPoPBUcz3W3he4-}#WYVer
z!x<+Z_8z))ZJ^Y*xgTa<`^dD<it1f;tYqj|)4^OGV2zH_v`zii^<8@}mFQ%yGG%gI
zWyf~W)0D6=T)=HQ+Qw}RUOIZockS#gZMSrU25h=A{%FXw@igKon|?$*7s0SGansTE
z(V_E*N6J&HnnJXWtZ6GKFjkF0&Y}==m9CT5CatG_w2ob!SJa+UpX=e>a!phF%)HG7
zYXWgnU1&|9Nuh0t&BJleJeHN1t9)KUGmQre#zW%Tgbl(~_P)^=Jx+`+-LZZrqGKX)
zlX-kXRlju|7e`;*FRCzqejM+-ICxWf)gX-76pXLiL6eIoW86lVNQ_p^#2B7M;~3#y
zgcu#zh52d*%^j#>4h}(l4(>gIKx3Z9sX`-;Ymd$J@_W&85<9&T^prm`&{pJmqE?+_
z_3*Xv7FL?!k^M6~j6_G_6BRcN6nZMgMIo*j`$X^TBRo<jdqAK4Nb9t^(}>Pug_u}x
z3_8#I!uD$IQVnMAofuI%u7`GqY`5bn*;GAJ@Q?RoZBg4n8#CC&`6%U|+(PF*H?=O~
z&{%Rjf}5SYTpaGHy1+hY4)=9$7TIN+Ma`HsZ5V-WK3wB|6}@8)uXo?nQHfYYs%+~w
z+T0*?*6rlOlicqHQnJk`jaGr79+x{E@pl8-Y>dbp#B0?S*>vxy5mK5LGpV|-hw&$R
z_;87z4`=y7Y1~HCow29lODTXZR%y{E8uSURQPdaI4^{-~3tGFVFQ~7Gb`q_gf}lbm
z`b>R9v^3cxY+>w4oNMpb=z+RWV#E9U-VLd9(MA$x`jxV+mvgk)aShS2z?8>$5eYm3
zz4JDfWvHC8y2#Rj0*4uX(A{qsTHpD8FsT8pf8qUF`SQfQ@8YXx)MzXvH5$z08%hN2
zBK{^eo~X<pN)i_&9FIR{-gb|pP|OXESsIZz+XDAfIrn&ddsn*0I7<AS!x5|u+Wf99
zG)`60G%j<g%9bfj<WiSTwy|3*c@y(00|P8791G^e*@j+Y?K1+_Hr-{$uIJL`#0jw!
z)fL8G)W%%3<b$L0_v1!*`9{VbUoqUPw!I*|)~MlFsp#CVLUJS81=NXF{h{?{)Bi4D
zN~s?sj>vQ=kUU2tREcKOw*~vf5fb$#Q_9+ha)Xwp+bm-(V=LR$qnOJ~nTi9|DRXt|
zy4EM6_!`OJ`N1h%9az4jGi`}hq0zcyU-oD0iJKCt;?dK(65{(df>)b5Av%A)Eg7)D
zbiDtuK_}BsEfnRtp;rdj-w0?ezr2#V%okP*UvR6cmo_XrnB20go<Br^mGBKmD;hQ*
z-E>s`^l_vxPFi(|ilv@NU6;IJ&pC^mu|LE;a86s3;#^%**VZ_Z!5B|Fb^Kg)jS3?q
zDXXNuwT8XF_0XFl*PIHfcw%JA$&?ML>$tUZ>kXwJi@sg#l3fKim4-sU6OW(&Sd>3}
zu-;eW85inE#@&+_T!+%u?-$=X_u{VHP~|1n&C?rP`=%Xqeae=<Jg%wZn5Y^(z2UQc
z)86~+-(MfcmQxBl`t+|SH=I8DMgi-r3#oGNsb}i$u4kIm$|y}<{}=13z%CnWuM(}H
zyS#E^cK&S*)*x1!!#CwygX0UVA#-@y;aj|S-y%2Oo<Dr7HE3<mL%$UqT+=Rm=xonF
z*!rP4JnpbATRSS&9*i>%{W2Q#awKxn3aV?)!uWo|?fW*VeAMLuOX5z@dZx$mL3e!f
zAmmDD9*ARN^H3a#q8ge9aFePB*Z<(8w%4=_tk<^qzU^DiN~10hT#~9#U0rkPI>vce
zWK2uF@?O>+#|>J?+WE%x^^6_;V;``|RMj8-pHw1X&MrbA8cMX3=F421iSEuvC`Nb`
zfoLny*eI{W*D+VL6>5RGGN7WrjVV(&ur@;%*I0)2SZ8Yu&vdJ^&8ES(zbW?ch5?(x
zIVrP~Xb6>O@URZP^96qrj?efLaD3L!cRq)(0^xbTwqDo3m@4n&x+n$l@LO2$h>%@k
zJgvzyz*`a+ZZmo0Ehg_9!HgVLZU2VBT>tuslP84++I()T21_PQnbekMn|vWNlxkbK
zQ`ku|RVdW@ZQ8teVNz?7M_p8PmfjR<J0PAN*~67GrQv&0Ws;SqBFx^K`O1AbN03H!
zp>K$<XPk`bg;Qna`mUIvT-O!Tch!5|uQ|B@!HN)V$6SvqtaEG3vgzp@&|FS7O~rYH
zXB?!P1%5M*3;k(0miqhRxX53Cqlk7AI?MdCa9r$v0!KBZn*;<0f&n23AsHbBfkQ||
zFe3Ev8@p;`EN4uAXkkiIx@(=(U28*ktr^p-6O0t&beYocv!k*fhx*_6Et6{&){x{w
z^3Npv|F%<Ap|P1IvuVkbDkms>7d^h+oFR=j|FFEk%zSjK*}+%H1;_fChs;UK-0;KQ
znL0I}`IZ`T6UPWFlf}d_jBqS23kh9+++e0GE1kI@({&0XGs#Ti$}x;CcP#VNyaHx;
zYCh9<Q63|>kj~P*Y({f22YKll!a0}9m>46j`!Mo3gjxh)5X1b4;6a#(d=s*951|%8
zz_ULhco66wJCbQ<bD3A)rF>(fXSOfO>&wVygb4_X5q^c>Mfd_CLV52-p1Y9;0daXT
z!mkj#2wxyj9=4eN9$o(Y=C}X#FZ5Sf{M7Q@c<^9zk&MUxOa5rwErMjb$g6ioH4>#*
z`Afavi_esLWbnz(knCUSc82zaR{9rsR=U?<HMD^%{slPVwbgvyngA=U37EsP8Yku<
zwQ;U@u17Wv86%vTgP3rJuIV@r$9d7CXTDcB!`SCFSo4d=&#QM{sQO0!A|hEsmHEyK
zdhlqg8}+jo>7~Y(8((P**&g)H#<R1#jt?RJkT-gK81aX_(PJ^<#a=qz)~zjhsNt{a
zOJ+h}LfVoA1*9t>oe616Ru!-g(wI1c)9QsU5e`kOchMPPx>x>Ude?CV;xp=_M=Rpi
z`slF;@uK?Z@jk@)@G3X18u{>xZschEX+Aah3s?9_zuMsnKjok9osRm)_@Cvcdvr1J
zr#N{b)@2#=<!)7U-cA0PlkZG6%3tHmLC;bJJxe;y!wz!tgGk@!1%1NVN_h}p|BO*y
z51Rem3FJ${xl4cZ(udIN;JLSOJrX=u1I`T2I~qCp5Z<{5`iwE8&jF1qMEVENb71hv
z1t=>IAq{CGao+wB?xUPF$2mEK=Z?0ZUbr`*8tJ%RbCQ#basFTzC#T{3-C>lA`>)~p
zPCWNG&JW_8g|b>u*RS4>>WK#L1bu;wIQzGpycyr}(h-!8=N8lm;I*UxaZ5%^BDnR)
zwZT$lQ22zTS}73cCF<i0K>Bnz16nWt1!-%T(pynJ)t_WegD0t8sBvu}j?rM@uerx9
z%4el_!SjJP4Kj93rn!x^YiX@j^iebM4Ao7G`cp~*R_kT%et6ml`o`Cgu7y9O11}wi
zG|en%UL5AO@&K(1^j(n>_84PN_sUzXx5&<p^Cgh5Bjt6$rr?O2{$62g$GMVfx-#eV
z#nqqBoqH$L(bO?uG&{X15I^UfjpM9i`kp_xQ+Dp{sJj#?Z@QFtGkflwi*o6dT&Z&|
zf=dB$v$Joa?%;WUlWLUDqy0|fj8*UN>fEAvq>ic!ujHBA(7tx-MQg~~5ehtffw}4$
z$6T!*_kPET^CT-WS6?ik{Kk&WA!F#Z3zR>(YrTT31Z`Y4jtjAh-?(bUBc;qg8^^_p
zCa$+Gj<r(@vS>lAh2NHnIU)u4FRAya?UT?OdP@>=$ld*)l%0TU4o~PU!ZuZyL5$>k
z6?koW?tAoCT8>e!OEb!P=(@mRY^w{ZGC7P4m4jj$FIKDWchHifS<Bb*N9k#%RFBd1
zbE8TV)$Cn2rZk|Zg?aoH(8D&!H>Ee~{9ea6c$voFKcMsDk*|!#4Rj(}uQhMlIlW_{
zpK+A>7vZ}^Kh0^zZcr#`;@_pDG-8=jdWPr#m1!;DypNwRtPyJ_VYK%Xrql@A=q)w=
zSj=~3QB7eDJ7bQb<KqHT4&7VBPQUjMtLRLrEGj1+bz6K^bSGr)bgy<tX0SzDI@sI`
zs38}6sjGh}ua<N;;Qm#a;8v9qn9}8tAEW#a=CGT$Yeecrnm-ZDY_)|kjmTvraH>Ay
zJxB|sE}^+Z&ln-)@^)ccT_7SQ;hDMs>SC!3_Q_-%29n+JEHo(`X?Ef*&_=n3Af|Ja
z2UOWQNMJEegvzrZd~A%)Z7Mr9i=#DQ!TCgG$k@BDzfYXe_4iXC_p(w7Gz-0@U&B8n
z{Z@j$-A?uSFP49)JmRxS{w3W=Y6I&?^{AvpXsI8^Gvz7u{5EzveeoI##){o=@T|B>
zOaQ;V6&gl8xM{{DTQ)jbhsGm*5{EC=loX&Wk_BizxC^wO+Ky;L#7@+~8q#|v*2?4d
zkDGk~l)|1TS)q4zHnZJwKIwMp8CT~(NQs40NM6(^G2WTrVXiQ=MuN5vwabuatsPQ_
z{H>;la#}lLZT|Al>TL_V^|sL%>20Gi(%Vuj#?8j$26~G%G)%N!jFhoXZHwkqsEwCM
zayr{$ZBH?$dCZ^8lvwcgXIqYo+eNW3euli4^T?k(AnCYC-FFHl%|^<DGB#%5U1wXM
z=j*!5l=nyy!=J_4i4c4LzypK!5AyPFWk_tfwT<~4y6R?XE$s=-+J5zHc~MCIT)U1+
zbT;qUi+X$>ts5_K9$)QD<xQ+J8Sw|Y;y?FRrnC<0SR`^Oa-Qf1XkDxxF@4$K{VZC0
zs!#5m?^7c-1F>nY0S5-uPx$Qs%%TbI0S$8J(@34;!&td9sl1<(%5^4|CrfhYv$!)4
zcj&usK}}ZR4DFA@8jO@L_+7F@($U!#!+pJVOtePQSO`IuTSoj2!g2%}8-1X?GFx!m
zGB_Jrs#WYSRJO<r!Jp#cSEXe$(jldXSm!k5U96MVBp3ABYXW|8T35SE7o(%)_EARJ
zgtcIJ*SOOhlTCZFnbQ6!D=E9b2V<=)DxoHI&{!>;az-+Gm`_r?d^J0r^qkDqNqKAq
z-<V><%!Z~nG1CCKnz_t4Duddb1n;Dv%EnH=+&?zDn9|wcw~7%SLZJ7b0UPhaprvm!
z;@bvWaNII5I~8^4^H;uSN4Yh4<YLd)C~G9zAT|en?z>v?U04~r+bhn)tcn{Mhi{C2
zmlod@t7Y#x#>OM&ab5(v-AQ>*ThX`ZwZbWy<}5GTw+u6Lv1@NmJNAt_axo{9iwsI@
zJ!_RsKD<}6HsS<V-!Z_mpw=}Gy${MuR3Msbg*D9+kzTO6YUyd$xBZK#Y(s}^x{7Bb
zpaG!ylv0%FkvmmVG#|Ysny+ULJ%hPV<K}ssS9Q^WVGY7gT9;m$v?{<zDYhLu<D~b_
zvR7m4k`eok_=ooUMg0G1#>60JGkI;*j<d`)&Gb0OGXXXSJ6hM}igPRvrFe`%=t$8j
z)F$d#tPNVruB*tkA+uD13i>akD4dZ7l8`QERaXyD9b@xrEczL_#xhqk$KDi}ZMk=X
zGP3fSt0noVzhG?~XeX~+F~3+Yl2({_pxD?`&C&`M?7_*M1KbH*%B-PYjg77hZZ${e
z1h)~-3Q8UIvvjtplfLgBx8N)3E3fiO4H?t3CqU<=8Pv0%vE_Gx)>?xpc0*ulUQrOe
zyoBzt&=0)PEM3xg%>JGk`y|FP&Dp1Mj(t~D%XGFSLyGU3^)wT$L9QIvc*ofm=S8OM
z6+W^!-kKYV(gjUEJC&=?ZF8O<Qp_LewDo>6RT=Zr#pttiXMXb#X=2`edEn=JX{g&k
z$Fe|2yX#S=Z=t*z$s)?wchqMyrc)US66UqCC)sJ!uOsd;7du<`;C|0nF{RyO-@ZbW
zO_uDLjk2jeN2A#;K30>L87Z^24Z?^V<(50k+#_0<t7fGaQ!?dFhg+S)I&k(Ikz<B?
zPCM<3%BFca#!xa+R=6qG^If@~_s1jcZTA+a5H7SarfDZI-b~|i-V}SrHnnf8K86F#
zTkO=7k+SJ9v_h<OK#V`gEKyeGW3Aun(YmrleyitMlF9nUbW34I=|yKV&8kxw3niiJ
znpRr6W~3U>P+FIx?WWyy54bPlXnNW-OVs2|`<mpep-V>zLliFC5N5DrIe{<49V$t#
zHE|lGCE6m8pm@8OUlfeql|rmDj!Vj>tB5r1YwY_gBf?j!QhMch|DIl;Z~p6hl`FqX
z@7k;U>hJ7Tj_DKKtGrs$XMyo}>amDDve+6LHSN}rwc}P#QcLnlWBcT<!RItT$|bFn
z@(M7kM0ZLK>C5w=m(2rj^n=s?-N5og-}c4cD7~+U)4KUBhB55fLKkF=iebWdP6*p~
z@StzW79m`_XQ=&O$5}ft(mMFfv;#wW&v9wc+k?itHuHfhk>9*RjBn;QCp3c#4qF?|
zraSt_Ym6MFCvBMS)@#^ubC_@BH&1t)!xI`Q*ThD~bSa`*f*tx%N$U-3+3AL6!#cbr
zXgFb5o4l?h@V2ebCSz49G`R_o`|ivGpO1M#ZLoj+H_S|3&sd7sv%S`krp3J1+CDX7
z<iQ=67wjs`8R5lVc{Ok*)vj@CI-m(bT&yN4xeqjrbSaRm(5p$AgJ}hjguPNog*DF_
z)MPT9^LDA`SOif0vQbk_fqtF?A|Vj?@C4ViuW|IrrrUEh>ytbyFI(Mei`lerFep#w
zEVQB7RHo6a*Q`H4BhcNOKRU)S2Q_1(bmlq4>6>DE?6-P^@C4|?i@AjL27AO=9AYKH
zDG2V$;Izyvx5|+loSbu9th_jJ_|Wp~u}$rfvbuKEtv%<UvF*35{#vRVAGY~^KYqqH
zb%Caimfi1tQ~z;R!;Z_g!#ggoI_ws!Kml&gO>Aa5D_n_dp$$MytHi{$Riay|D_g$E
zrLn(=J%K^F&cGDk3Q@Ss*=HU}1E(C_n?E4xjz{<B6V}JsS*taa(30R4!hChY`ZogZ
z?D*^2qxasu>t>@&-%H<by)()qn@y|xpw&!$`!l7oX<shI??OA8O|K(eyNPwEX%A1?
z>$(NH65=m3#|C<))CzSP@&14mU_p)fCVi%C3gT(OrBY;Q-bXQ#yBJgbKuTA4rQ7g*
zQXmns(~iq8x@FUIc*^F|Dt9L+5*g%U<$YAoUh}LB^K7aq<nUTM3@yesTdQI8YL|@l
zg~p36#}|How_&~6w1%}}q!qg~*-Ynjmn+=Q@=FiXDb?!j%wlU$YcI)smouz0*o%XY
zD7*JA?2Zs8A%_QB4C`lmD<Q3l?n3vZpd3yUTEmZRp0X8t4X0Jvt>FhxQ_0Mdcf`na
z#C+d;VOZZNCSyP8g;7bLC2dMx_ko!3*|MX2b-y{OHZ^unCSv#G2d7H101dJ7iV6EK
z$tQHjY2NFblh^UpABcB&H|(2s4%!J&zZsA=odH_mW*@Z%W&48s8MrowXB;-HS347Q
zjHzx1yM&#FIoeJ&*_zFB28`9>&~Rnf*cIMTJrwij)=a~O%=)@~=lNHv7gm>q#t2Mj
znJc5dI0*F7`5Eqn3I@Em+LmBvI;Z)lomeMIosO7~TBbj^66e_j`;12VKKi=k6Uplg
z>t9$ht=hNs(Q#}M)x>&<>OoI`kgd*maQEb|3qEG-Jrsk++MPptXvVFXI@ydd7~3a}
zERM~e`@F1u$K?r)jI`r2-#7y!V^!mh%bATd--YmN7%`OrlcmsQ#tO0`yGmr8vMFt}
z?gZ^zdNe9$p-Z=}C^&2LLSMP%6`o|x3D(72l?cgC$){VV!j~?u#`@!6Esu*S(&k{q
zZVaxTWHyy2SVI%B>&lqEnLO)bcKYPgxzP8%1eDK0pyCJ<w+Qijfs`Y9MI4hefWAUa
zZnc!UNJFH{p0~SV_x<N|zqnbr$+ALZ>@z`MX9ON-WWuRhvuU<SYyHd`wqmI5@tQfi
z%L6(~D#qk;H_ec~*`=;jW%N&me6xNEi}mvb97|nhyE8D^m*ADFiL+P(&LX<6N*W6t
z=rPR?YGYc{e*t~!A4`%J0J(CEa9oDG`~#D}zIVqg3y>$K=XS8p$vc?Ed7QA-TCnEa
z>S}csyDUi<%*k7|EyC9AqV5Fic<zu^L+ggVnM3*qB3u4?jcUo8hlQ;gjlKHu!>ps?
zFmOv)GxW{+wTAqGz-ldo1j9~?a<>tO)XoK@Kw7;)8F??Ze{3^eM~x!(Q9zPKkyQNU
z=?c{@)4VC_J+%7i?S($ZKG`?LcdsvLlc6dR>rNcLlhz#i)+p^^%4E}jj8^viz<KG5
zzqhF!eLRk!S|Yu-E4<0id0qm=E+tv68+R9dXA%&0(Drqw>J<tQkJOmVLTx#3no+(L
z7!Uy%ycN(D---Am{~DDWqnJLmO*ZwviRfdDR>gR#q5B0_oE<ZGF?QTr5>F<5*3>@I
zLbxNMftqGo)8j0R1JZ4mE~y`vR`04w^Jt(o<hR6U^4BKj@5(C&U5)CiR9rIjlcYg;
zod<OWiU@1oriAs08yM5b5yyM+b}^k(3)+kH%A`}KHp6`AQ0fY*O4o&T=5G@!`r7zy
zHEu`kWcRLd>L-$IeJTvLRzl|msZ|!A^@YJ#X0i_9@(Mp=O1Ky+fhmpctC~&ei(;uU
zp02PiOXRN@D@NFuZM>^bg~_(S1)9Ju9M{mgYG+D$Q|PxlP0(1$1xG{ghBUdd=@bwL
zS}uy+C<z2@yeqXrZ%gqkubt>B2d5LwQMgCAoKg{Q6Lt`-W-Fd7pg#DI(P$CVmrqrR
zJ)9m>N;;|NSSiFB)rxP;vb|Ebs(>+ldi?c*lnS#j)MBJrrK}wh@E`qiY_1e3xxt=a
z87#w|k!$Oov-}qmT#4T4z+r$BJtx$%GlWmnoY^#dJbkkUW0UY7KaP&#2T7-@v_UT%
z<@5hZ9A!+G78^@9;wb;^rvLxoDDTAg(m0^+CY`d3@EpSP2sh&HR&?R+p6kNhJxe;<
zF5I2rL{cx@UD9#G$)yVJZYlObdT@8o54j$9=TzoxYq$q@w-8)P*>$+PMZIu${hCV}
zd^_hhxOUFRPUFUE<4FN=bNCAO9G|F8J^3im99g2NMJq<6j`qqn!sI0$>$g@jx)^tW
zFlu=?hP-nS@~#}nyY1p~@twky6XS~Hoey9y?%sOf?tsDTKMb0=E(Bh`=Co6?DL=dK
zXV~|<4uMCSiN2fCHuhUvs37nL0}J!xEtMUfj}z7%gCxzAaT}d&+`1zdofm!A{Nq0c
z!fwFEmV9T(v~D@#NgF#thE2J+KH7dhe>Bi{&QOzrzB6uG)0Vn^eSWxLO|S^-m5}dj
zO93~ZxZXN;A<%cDKuwz3Nyg-HH5{mL-Yrxs=)Ang@|}S=&>?5Q0;!%*cFU2{r0lvE
zwX5uF+BMCrl<wJa6`D4Mi_tdk7ms62AS~03m^;$L6Xq^9t}8J%-az;q^yx*MV`F9)
zbSyk*Yz%WZ0{2cK59zBv!<pob7=3x*C%C)&6x>}AbY6tJvqC#=Rd9D!1$Q?cQvEcH
zi^&S^ZW3^J6Ob}R!QCOP7w&G-4Y<3zFru!<-QD4#wdeRvj33&Tu*yHK7y2#_W&L-c
z?+BGc=({1<mmsuG41I^Vg1%#K9wGJl8T1_o?I{p=Ka0Mjy&~!p>W^0us847QiTZ^4
zjOI1X?^OtQA<&$rzKY37w7Ol7MgHc01dIH{4OnFQ1{y2RnS12W|4N+Bn!ke6p?&n{
z5D2HU3g;M3Crba(I%S5C*+kU;Z{f$2!as)}C%S;O46BQ#g!+N-<1xPOc4fRKw=iYu
zY!*1Hh1@L%lD;miW}Q>=>Y(!j9|d&QzvRZB)US)*FxgUAZSBwvdlNkJqXil*vpA8P
zu!F5o+4vpbSu~na*n?SfXF~b6{gqW8lpwn5+ufE-;(wDvLvs1cuesS}18pfwO+wnz
zeu8mnip>|E<2FF64GRdjK8I$IYL3Q6i1UZs+H8&H0N(fS*=%`KN=bO+m`%@79X5?7
zt})r0bdGO~YRxpo|7=TMhkdxlD7Qy^E%AFa2FF0BU67?y#v=9eZr}%Fa>I0wMwGV<
z6DJfBSM-d9acVVFy1qu0zaSq{NswJS-)3!}o55UFjbW#19n0H*plgRb-)3#Qxz$Q^
zF%SA8=v=i~kbAmx@Hk(mBOTTnDRTr3?NZ=z(a=u0W<H|m>TUNsBIRnasVz>re_V2Y
zWm{86Q?N3iH*4Zn{9*Mw?9^A<nnJ7FR)1vg&}j6whV!grVW4nlWJXbN;bD&ZU*}nA
zbs%D0{o#bkT27;R;5_53ITYi8uG!M+wc2R!05PCRZJ2$b==`B-VP{iNIGlnjVJG(Q
z5eLT&T<1mG3K6?2rrBd=c1Z|P`QT&dXQ&Miq3y~L%xKrxSOP{B`=YslF%=QV1Gb4Z
zBPtBSNMJ#Amf;ntLOnOKB2hTN&BMNro}26Oxmm|tkL?rIelyotqqgV5G9dY1S&7CW
zQ$CEF<kC0qbY;01)6?T$!fJ5;8AhrShd~?nzsIY}i*DEhoPKbXIJMy{^3fjPl&(EM
z{RY<V7j3SYd6RscA`eaQxi&{v7Au!oktt0PQY)s}ERfZ}0d6LYtn?3KWN!j3?8lAn
z!pP?S4UFutdP2i8r4~@z7)DkPjI3<hG-f~aH)d1LxF}YZy}1i3TM@;|N<V{@r9HtY
zR+a-+cI8!dH&zy!KLsn>Bk2%U_D3VuOwcq#AK+ikF!Dk0@YHv-2FCcpA&@axjByk8
zq|*-wpED*auW26S6+R#2)vT4b3NHTIs)9xNZ$K|Xb3u~>X=4lc*E6&#=t<_Za2|~$
zg&=QaEy{<)ah<#Y47XbYJyP_U9{n%L6}j=S-vXY8<coS>A7V1b5RWfh>?ZkqOg3!6
zI*Z+!iX1^*F-icsbjxsX@ehwB>nosAm-P2OG(L2Zy>H=??=Q-GBTnN*f5>R#p+~C2
zK6{*UhF;tB<w$V%5}QpDF?Q@pO0deX=!v3HqPtWiuMxeV{kNF>L%e_VeLeD7R32a)
zw}B71O~Kfh!?WG2Gqs%L`SFkjj$CXCypdlQBpzrj&O(0VyCFpj^Xs62iGxl>^9zkF
z4iW=&TAUhfM{#R#b-^TYjiRx!1~VH7vAZDOg7Tj@97XIz_xc$LHgUbsB}NNV#+bgy
zh<+IzV{v@1qPx}<U$UhFNksYuqlNQUSI1*c)CDFr@-<1|Y#)ML;;L3pf3RREFbbp_
z=#fbXcR=kz?LmEZ9%JfDgli?K3%KJc*qz*kz8K<R+(UrKL(d^-oRu9w?TLxQULHr|
z;oSgG%Yg_2X-rtit8t54x1@PoTl%6uHOJ#x^rsR&OFU^jpoKm=<6AZK=f)-4<GN$<
zScAR-iWoX@%r*+Co4BeJtZ4C|?Xf!1xS=t`Bjhqn1C4LmKczjx*f<wz6n#N(h_W(O
z)jnBU61v%z4jfZ%j%rKkmVwZroOWx*V8wN+>~(ETfia>cJEQQ{He-8TJ6h67ySR)0
zO>;uCt`A1MEBvb46`tlMjNzpA1lZ-t(7*r(V_B5{cq=r;A7KZi+fpp5@1`+Mx(8}c
z!u!PV>l-{>2zH=~DhX2}t@X%f<h@Zmdwdt3eXua}O21{TVWXf;T~+;h!>@pA{}mAI
z6r#BH*Sc`+uOfwT3WRGf{7>N8pSc0oe$SW~uD#-~;MyI36W4BoydzwPYqtT{F5G}?
zpVtf5{t$5Ov;PXN{XqrSKJ#aA?e|@WYo7+XFry3CKK&=Sc0zF6gE`gD9XE1Pw^heP
zSex95=hT)<*EmVVk;N0qT5K6%;P1d*O94?E1p_~ZW~AG8dC1RT;7R^TP^^v;n{yD4
zj^3MqfzRp2z>kC$cjaYWFAO~G+r%*N%M=X!AkK_A4vl=76i5MILKq{~k&YePFJY;}
zlxeYJNE#fLW6K7uW&G(1=hGW2AEU2dV$PmLAQ_0{AL4&b<4khX8HAGvUmy_XhGZm~
zJ9pqrbBpFxln?EVp*MA7=rfhM)Ed4XLqGcl3_aHOD{RFm8;}{aHwPL7ThJr@6xrD=
z_Vp%Zk(OVJo$0zjW#EdnG64N1@K><v19jdP&^Y%6ID`+xnTO@Z`Qq+c?D=C{XIK^9
z7JQxtw1D_qGx%HjJ|py(RBza;<!G?eS~OX+K8glnO1t*}7Bl6nv$CCbeR*jPN?ZXv
zjKXgR<|&wr6)nllhCott@>=FwrhJZ6bTNvoF<eYqr!Jo-IlHePu4hL*TrZpAbD6S-
zqG#-Y61^z=Y=YCQ&~}x*D9B1Ef5{<n0(cqPv8EkK?D|U2<GS#(LqKC%gNd0v*BV^g
z^9?5mp%ta-QRIiU4LhpE=WL8*XkqPlC~r(@PTojgL8zXjjq|!<2^w=a0o>pB#}aiZ
zYg4jUhzIv>AX_tsTqJeCvU$GNCR-!0a*oV1*fOvSu7^D!m6FoTqTbuZWlbq-fBF>c
zpt_$sE$W&LYX{bA9NLz+Q?w%~Tr+`!r!3K&h(Dg9P;h;7$~xV#?V{!c=hdEgu#WN!
zD35ENT}S!!%@5USC7LVocx$|;^phUFe;qJ3s}W8kjQI=!<CA!r-g=>aSRYnREX+4B
z&ert>tB$;U1l+Gf3aIB?fnKj~e!ul^im6H~^wF&li|P9-^uoma^8D@MGfns94MpBZ
zo1!`SuujW|lXcW)2F(Xz@jl8Or{sS2Xf*FHkA5XS|L#A(`!DbQ>D{g8n5(|=%+<#6
zr!NM9K#k&Wj2DXo#=s-r;91~PQy)zeoaeWTD7%giude&x4}Z92W$Oo`m>)OBdI`2T
zZG8BqeSElbADAJfz6Om^sc)L@&tmbfd+Ph#zej7phxvb>FK(-i*gp^#iq_zaQa&u~
z8!X->4%~hB9x0Gr`ia;s9%=p4*FCk1)$LFF^rb`h)ryNt-}yrfA26+Sl&GKu6#Q)O
z+P~jH^*45mF0B>c?-(T-J9d6;ZO<1zz}M{F*VulSI2!Lhwx^E(SuCvEgD=_h=kx4^
zVc-1W7W%#sW20XPdCA_t`8F;Qb)=jc<jmc(Tm0bsYa)BTCpYVi<?nye!lgc<w=qj1
zW&J-J0lS=32e-t;-6j6{JeBY=O3?42dW_k#5<9tX?2EoJ`us~@j~EM-T6_Ofgy%Ay
zp!q%EGqj|H6}G(SB2qERacA9tO%c14-+GHR7`mk+*l!c^IQ!I}&#MbgJ1>0lm8i8Z
z|1@fm+<$HSXEeT<YbuOyZi((h+%f%e8n+3}E5v@AHt*dJ&VFL{aj{2xMHsf;{C462
z!+zKszhwn}PBy)g56ic;dhlRHLAnC}{do`95W~R{299`6*hYB^kHpo-0lkl4$}dnb
zqKfXA<^;p+8z<~w_7m=%@?VdaOseN=A{87s6_pd5)E3&Osv~=4`_v<@L$L6J)HkVM
z+L0(P9K+8m_+XT$@KMLIuo7l@RAsahLKlu!NLr#fMi$jy!J>MIcPK0bhDMJbv$x`m
z*()I|L0E*a96>;M_KX?))4lE#*nvjtVZbg{bbX7ADuHI4YQmJN99T0x8Q>k@iQ(k?
z04I<30sp53&8K!HJMFLjjg#AeA^#&V`7_N%xyfmi+y56Q{}EvaLKVVm|H8?4HF5Ie
z%_tnaSM0lDczXukF`|4u>G|1;AvOV0Eo8!q0k#Z}6u85Z;ZZv>>IHvq3@Ymwj5RsG
zK=>qrec5qEQJm^9ZUEN)q1n-$8bZ#moD`Rpj(x(uie50S{>3j~<=UN^qNJuGm6fnV
z*GT&^tFU^!dfS`b7*K`*CKh}*^$Yd&YJ{KLSBmL2Czj{bGp60A7-w(9(v4UrO&%e&
zUg3c%1m=mInj0d7jk7toZAkHTSf?^WfROHf@kX>$>$fb>{?-m)18eVbu;o(V!Mvgl
zLeV*ag(9?0y7V8IQR%?iQ5st=n-%~=*L#m;Kj?Z4BNgp~(HI|bimlmEjDsRByFOdd
z$#CVPy72pdAGxoF71?6{kb1)L>^@~K=ev-Wy7Czk-?hrIy>PFxX*KG_n7ETnY1H;?
z_o<2HT-WmkppT;^>Ci&JrGY<O3#3y_Qlc?Mc76rW;Sqmt#W&G+RU*_NMCVUGWk*j6
zWGFlxEAcMYkp}q-d&#DgxvK+&%1*ayrDAx9z#93Tp_~mHmc+b#F!ltm254KFZMx>3
zc|g3{7`&7A7;k$gx<*FZF{SH$X<a<zjqiiy0Nz&|j8pbN$Y)6GdwQ2S0A*5n10b<s
zMk<yJ!!5901czFQZ|UcmP%B^I^W^V{q71O`igX!q)&=??4kS-5=Eyjv)WE?TLcKNU
zYSKU=zaJ^&6@oDEJ+d{)Z^XOO`$^6u`7`=0(b=RDQ?a`V3c5uKs4T#*Z($s;wm6gI
zT?L;t{8pmgazR}Ho&w;}0UXw7V9GF`dd;L#7vx0!>u4vu>-#_c@F#tILZV^dp!87;
z!+ife!;C@%_IC_ZjDIkdDl_5;NSm3;41rDFZ$e0!$ueAu3b`Wq>z$8m=x)OOo0-=(
zk*(ZM^D+!?W~NRwGi)KwQ_QQGsVINCnfcy|^L=KXnQ7Kn&N4H`hs?~FVly*yj+s+E
zYGy{#dy<tp2|h+hK;6vBxu*_h#$e`<2XCc-Kf2e;ma*klbD6b5v1J@dwv6GMG9Q@S
zZO<sMOrd3*AXvr^AiKsp&7VD1kP(icm|k{{3t{ir{l~>@9PzCyWA==F7$y@oin-Jl
z*@(j?k>c!4%<M~)mLEN{+027{4s$I6JH^{aGp2vLiCLlCAA>a5EZ&}nwESoq+n-_D
z5Z*^v-n%d8z1hr_HY)#a`YV3y$>%n1d;iSufB*a5`QjOihT4MO-@AX}nFW=Uu2R{b
z+s!k~#F6*ac7NUfLnNkq*p5|hyZ7z=6BVyY+p%Y~-MbxQ7HK##4#fS@_}fa#+unah
z`agFaU5LB9(c=!pcX*>mH{xz@^jM8}wU>^q;mIzbO<e3^(nSGp;>u~)I|*-61e?Np
zUBm@C16#b#z(iOU7W&}3$;Vusn705|i*R+XZ@qUt%31H-fa3-nB^);*zOn1L3Gq!H
z^O;RvCFb3X>&;!qw-A5J8$E78oN!vM@Iyf9yTT9qeBno2zVLDv)xZ~i#ucrVFFd!a
zR&OY^g6<DFpYEy^^5JT(k9E9?R(cihMZoz+>(A8<6LylVr!z3&@G9?%csJ}lUFL9w
z^0qYr*ns*J8&DsRY0y|b>xIXbGtYU3!eZ&!`sW%F%FX@^zs1j(7Tu8vpA!pQ%RS3!
zwGWrLp7JnG!T*%^DLnC%cR7yBqes+cc{KQ!d!I)7(_P1B5P!xSJz|IY%(LF;k=_YP
ze@cZ_(1=>B5;a=zI@u~%Ydlu-M7@xo6coN3WLXA|hyQY^cNy|8>pDJx_!FKdz(G9$
z-f!}lMYt19W8lGK-&n!l!#OggZ}v@9d}YyEM7rP)zyq~FA66BC9V6s=W*aBp_7Nw)
z2^`+`@1r)Aq>C-Uz4?EHZ6?lN{f?8((9ymG8%_<bFErvBvULZ__zlvJw&J-&$YNL@
z3^-4_%E|S}_w|=32lp{`<jJt3%tG1$*hLl~&l>pGD#l(y)sLL~CDJ$SM%l>w9p3pR
z&cxR|fcNDhZ{J!@cA?Hr<RLrG2VjFa64$>&z2@P5{6*Ms;u`NUt;KWo2>TIad@tFd
z-i7ZWo6p1boJ=-$2He}tL-#gJCvQglLFCzn^KaQyxd83(Io|Us_(<Cx)Dh=2+%qAV
z5oY7tSEH=Se$)YN;6$Df&MR;Z<4pd=^f+(Fnf!}Y0pmmVqfx$`WlGWhg?NWPB~{kb
zH^JtWY+uvS76WjPMfmMrych5Ii#BSD_V^99Xob+-|KHez(l>sGJ#n(I`_I^fQX3J%
zDI%39`erN8k;$+i5w?~9{e~T?Y(4HyT6KTG2Q4p^j$mg>-%mBlt!Td%oOQ6_stoem
zwe`$*LOvl9;ce`z9vdH_j)6B4@|(oK2MI=f6P1IR(J@)n*j8PfBC<kZm%lZ#PbIr8
zxd6N*thX$qXD=JqFy1@<puxs>&aLJT^PTgmC*U~0dLoXGR&!isfbZN|U3FH*^){SW
z;=CQ_RXD$0{n}an!(rZG9=>yq+f}_voY=t%FNt!ax!zW@AixR>MBAak^$WV<3l612
ziyloE;F)4L*RTG8^RAk*g8m0rb@YEPUWk)62VCzwb-@@qaQ>}t`bdc!^G@87?*r>D
za1B)#N?PR_<E6oW_~SS7hwO|9utITje-B$6NThRA0^>N{KWY_w8tqQ=_Dh_72w@HS
z9rGEy4fOK{uc0C7;J%=%#!%lBbd7V3+lPKB3MSOUmgY<B;dv#XEcPk(qS#R*!3M$u
zI25emk;v3)vaO2z8R0LH|D^3K-tUk?y=-rl>%Z+IZ?Mv~kqVWN1RLZLkm$&72KH_`
z=esF20jWbBX}Deiy9D%KuT)^w;8_DBuyby&)OcJ!>yN|n(O#))TtDB-RyVE7H(xfq
z?ydGG;CQ`nK1fBd?tRriyUQ!zYmgTHx+lJ<{V(j3poNt?xBJzwA}jOD@Z$%I3FWQS
zU&`q3<v%YMeK!&zIy3&d-7w8heC2=IZnzCJO+VTwyZZfoyJ30<v2Y9iFYVIbR-TXA
zrT?7&44q8_t4qPJ@oKS7Md`ps&;X1*uwa~=>WP33$nF$7cMx;(aGjl%?hPXLY1~r7
zLHW~UA<4q;EDt1P>*uP4c#rce?Ac%m%g!;kDgG8gSJs1Xzk+&PMUXKcG;4coprhFG
z=zG7%eU*YW@3~graILxF`tR9L_x^qjs9xa>Hq`oqm`x$!U7}6a;F_TDsn+WnC+{T>
zb)a}h7QjA0g^=h~krvnv>}<yZ;0p+E9-sM~y|_c?F?KYZeQIaX&Kc((K1?+y9mV>o
zpru#)E7r)Mf5(|)KvR*FV{ZZvl~A2q>I;8dJ@T<UVZ@Uf+h)-hezj4}u~U3uePe$w
zv(*>QcCpiN^qIGQJVyJq>v!g@t&ovmo%;2JJqe{iAKPCQ2`j!YFyVLnR%qkS#@VY~
zWPN>`BFABW%g1m1{H!b7`XO7zblL6yh&Cp<EYYKP2xqX%yCu3tL~*8Z*>N5{bWAU9
z1%54{>9VGs$uRY_E_{r2fkB|>Q#>4=Cv<J^=Tov1J(XJ$JqE9;yfQ$@%><9O9M%cQ
z#|MDXP^_7$JX&k0ER3@h1RdzwAE|sQ+u$*yY{Ly@W7YC*-#Y&bTDz!r>TX+KDv#DI
zDv!$0A%`z)uLW)*lQ7sZt8n^u;_XLzD%}z1lES*+J#)tjrS2Nwy7!%XGpt{lEjZk@
z-B+1HiTg)qU2tfQ&0QBv&smJ)fE*FWemVQx=J|aD*16w*!0+*U{b?Q<zCwZEJ)v#Z
zozOtfw&U6$>@*EplFAu?G<(cn;eXt}6j-c8MHirh71<BY-(FKAPx=zGsqRT2fzUdn
zA8SQDi7q{dxe~)_5Kg}D)ZC7yc2oN_#S7=OZuGbz+ZUeVVu6@d+xhTh-z25AtHkA;
z?g_nMHl6BckX8Y+FvWC0EaxWF2;s#pXeq+HZ$e$%w?oQRmy?$W;fWtltkXzBxbR~R
z>v_b{cgFH|Aw11T-uK2pe^_(bWY=MLjI09q%TxCf&ZzFmxMux2SLX!GdD4dHEUw)j
zO@QQXI<Z)NpAg>T(%Va+=N_3OgkN<H1trmDs<1ai<&NTLhov&8lQ8STWj;dmn@yKA
z`ev%1eyvl<Wj5X2kNE9q?FmB^PBS<YxmS3`RGu-}iYI}QCyyOMcxo@icvb;ye)E7~
z1D{6iNVp-IePls}J%V3bFRl<@fK81Knh5=-__ewXaT^&^UWTSQ5xt-*S-zlW51N6t
z5W9EjzaE+;E)WNK=4@fg263Nnn>nuGo0@&*Zw*hx+xkIkSDv9cLF4V=&o%2(xZl9$
zot=7L$6k23@m+hdpc38$D%%q4KiKAO``Q-onZM<}HuXpv%@2Rhq#qpm;&uDZ&teSt
z%A$B$niKSP!ix21ALA75qYm0fdU_Q!j)X=gzp(`lqg)D|X$-4Zhj-xH7jwY2HnnRl
zFNxd+K5$$#aPMGGbeTH?e4Nh0t%s-2dyb3d&H)xkr&|;W)gxnn5AzL@W@X^}Y;J@4
z30GJvXr53DswajDrc|nzzU3`%>)y8xy0-phTI=sOA5{O|&-;$LwhlY&+Uj#1g6)8Q
zeRcJ|(2I?0>(@dD9<8q~HU3!i>4fGtprJwy%acoWV&%cQHs<&7>r%?Up2WO!b7@nX
zubLTiwC!Uctqx5>xm%hhG#+i;0^47w|JV1ImY2eQtUM?lxfr^bbTJ_M|J}ExU2J`)
zymSmanH&)h@4CPAjnc8@AtgsZ?6?>d4}U~??kn}Zb7uVM@i$@D<?ycZ(x7-xdFWz0
zas-qd`t|2_-CT<6(2E~J-(73%m?~O3xY-G|Y7ux1=o3HxU-2j6*Qv4vPf>6VB<{JM
zN68Bj`Xgced~gPGxQ}HX+W0AVT&B5G{g_6uZTWG=uyYw_%%-H3Z;GqAXum!P-+&J`
z$Xn0yzOSY>4F0NycQwgd_f6P!$n}nIYl>9avC`!lr+Rly2fh_OV!)VM^{H>G>zy&u
zg<X{$|7;B*<)se`VMQ<mzV39(a%>Y3XYu6lVf;Zi@)(A>wl3J!xN{NKu4M%on0rlF
z?@A62=5DKpAC($*DdUK<37uk1MEc8&%AgAN!8g^bGUaV?oV?BKsIJ);)N!NWWv04@
zo~{d)92$-*8F9K-a%g1zpzhuU|LE>(8LWJJYG%onKjW)2&lor}*3loFBcR8%h5Igv
zYDMdw)HO$K)Cm2jFVTZPBKp^Y^KS4+>EL~7{Ye9z?^-j=w|1=|8cM_Zfxu72GutYn
z@{0lKhoFZ%jnIlfG8pnGw1DQ52_u}b`@*kRkI3?cr&W)T?hCP5D<}HGuQjGN$lHD4
zPii9f;dn^i&X)VaM-EMe&CH9{uI;|PZxl?s5a+B5=^Jc&vAVjCc3@?OX26ppU4&mB
zWggO61OCYs)9Vlahgbjf|MJxzJU7<E8E$np#A0BmqB?wPYfVXvABf)3WNT1Q<Ru>_
zQQHQ52ensnJ#@BbNR!@jM^ia8w_B3P%MmPTgfm1}CCDv__0a&|reDOK-~B55dZP?l
z?`e&u{-VC5{-OSi;W?vrV0~dnNp@hYVh6@5c3>>*z}Oq?zy?^Nc3{s(?ZDFC=A(9C
zm#(t|W2Z+g!OAnbEy0wWf6EeVcS6h(tg-OF#}X_DW~u+ECD`MWL1#?!a4hYz1dIPG
zmSD8j(V9o|W)k!mG1~u}=POa=;I}w}@y*Y8UUZwoyLPemw+rep_s!u&A6kRH@X(wm
z>doQfHRkaCnx$Uf_<a}6VNZ=-61LWb9?yF0y_aE$D#KnkglEv#Qd8*WQpbBQ!y1{t
z;u;qUE`D!c@O50t%9V(#H*n=st`_2IEv}gFDCYuPZKUUvt6$=33q7Y?&BxW-^qg|F
zFF5DGs&OxgkGyA9JRjr+i}$Yy?t<r+l+sYJ_7<MB376IcTW^s!x88C;sB|a<+8%oM
z7V9PcYU?dGm$o5=XtxI`3{rAK9U=Mjz55U19j%*z{=eoLXT7xVQtRnL&*b`|;AEid
zhuGHy>jJ8Z1RJ4+{>?pKG>2V&4$?cDy(XB8v3{qr1DXWPtEO3Z>UJO~e{k-)nq0oJ
zQ?GDwT6iip!)l7RZ->Vrb67Z(Wf|hh^5!(~TXO0p*i>8}26^`ZxhDk%B7Fq(sF_}0
z^$<r>PzCRnS-8$p?mGiX*g=I`!MkXu>lpU07{^f0W6()D?t(X<UcR}PLH5u<wxn@D
z*g8@dMAZg=!ucA)C4~P#_&0<X5TY4q&w8GcKXQroEJ^)9^wWT{h<{=j%v?n$!7=kd
zlVdt^z9yv%NQO4`W0CSXg7&duA+Go#Vax$@`28JbiM7{-W@VYserG4Ss&lbt{V!<!
zrVd6jn`FaBqPc<>*vrye)^QqX-?<N~n?kqdn!~4e@EBw2tOBzR^3jLY8mTbvXb67$
zCJywlm#xGpI4Z0SXLoEjn~udxAv5;Cqvfs=KLS>T%GQ2nuF$O0ZsKg_@Mc)iLsw%l
zpu7YDe!8TO#D5uQHk~z8c0jg+Uo+O;TL(*XDK>wypyB1ip+oe}y5No-_ec?ZlQpC&
zw6?*&JWv*@VeC}k$+6x=oP~Ls>2-nlv%qKu;Zs%6V3cHocXsVavB$O41$4~`Yia%a
zrc)0~;FKltClVDdTHl<wE&@DhLQ5X!4+%R`1>(8~;mH(G);Ps__#5~^UwMU7Mwza8
z2uF9O=Jg@3`CBxWDzWd^e4vkxa23{_DVAi6!sTujdEzay>35^ST|;9-$mJ!fzF#M-
z?LB5R&}S-r3|^VOo#;K$bXX2xRby{rmqe-g-%2-|&MP+Lxnx70zH%as)BS_UhCJ{S
z8}gg+J}OIdEY0(CHsn@VRrc7B_t=WFWGkM2*QCE@D^7Lq9+yA^3=<i6kWH|ut!C4x
z42^a^_U3nf^lGic#d3>lvVc%t15K^A{B*$5U<4MqY5eCGd~a)>Otp<fn(^Yv3yu3)
zFLTcKFAh2g8ULHs@PVD`(d;tv&jO?p_|H0M0RO`V8=KDi-P6v4zYnP9;I3Ug_eGI%
zMIiC0p<B#_4*}=dh4~4d#b+5)#$*>{Q~tMIV-D-EwuJZ-Yhl#xrUo|BvG14=_30Az
z{L+$?efLj131v(^Bf%T^C%62>laRs2*b9335X$TFA@p5;_@q|+?qp1U+Io`*UlR4Z
zQ`_6`&a+mksi7n0ac9^K9(PuB-8cWl;|@I)^R<I`5q6w!@U=rZ;Fqo2gOI+L2O;_%
z9lob$MixQuJ`>?SgqV*b^3OxIOMl-#4|DB*-apTdn_~WXsE#z&qkhOTCKJAwyrX1H
z{@Z@YAlhE%hb*QCFn9KY2N@uLI@9gbj`%t?_UT8MvU|7>#KquA-*3ysNZoLu;TzY^
z_x;(RN#s|XwUX|gH1E(}!xlh4x6P&jhR%7uj4*YJ*{LtWYG{R6x0mV_->hH1Lfp4k
zrSxxZh_2q<tLb(1>%F?JtN68`{KabMz+V*qwSNlzdO<zc;5;u^rvMKlz{1xGo*_3V
z95vuq3<#s18{m)hSUWJKF+KU0XeZK@lfLao?4yv*jd*9qF&?rv3mIb^R^M?RU%1Nc
z3qMAlmVp;=h8XzA!V1vobDKMDZe5m;e>A9vjI;)_ijc1lv(nMvuR@iOR?MA(e?dNS
z`7=F~*W4*nDR#2xH`fbIX8bzEU@N?jC^*-Nd3r}taK89Bb`~=x@2-XZyW3*Czk<5x
z57Y&`dv&K8mDD~+RXY-|vqeu)Y|&-Yq1;k<I*Q_6Nxpv$f!1k#DswO$<9TG4>>iK(
ztX#ww!>8&<*fm@%$y{JLo^kA@{V%`wvX|fda(zdDKOOz;3(~b*z9aoJ;uA05F$j3J
z;v?kq{_-6|n!gg~eM)2P@*Ng&1=a=rh+erG*i38M)TSru<r<YEu{5{zHBky#O9yQj
zxG{axq^!q~9+$h#@fC7C_NfM~sppcH>2347QVdAp!<#>a4pQ0|`Ym}44av@Zp%;qS
zqJ5#rm7zs-p|r~kjvOTOgfLTd<YHZDg?Kcy{)ieHCf^ZFOEJ*Yw~qzIY#*||_1mF9
z%*M6oj_Vc8*-O`S<;B2q(~8T6St>usUqg98UnkxWRNfGzH%J|ES7>Zl;S*>(w4wD)
zxq&!fj&BW{is}OMn&K4C`Avb3u5!30G%{MDiFT}J1U`0JgZqMfxU6ZsS96V9d}|ZG
zb=<+%#ijsS_X~bAMiEMu0%f8zU<%V)B(%C3>+&e9%Xq@BYtf&KQ}lQ{uW5m)OIFtA
zyTq@=`ge(@8af!$U+!R}_xDim{N)Zq$8Yvf-%yMXyY^7uMB}^nP|r|YK)Sj+eg7V9
zcl`Z5<aeL)WNxxlWdKWOgszZyJYvh>kpyQ(LwF_)jV;WjC_nedNOY~$VD)=AW7D=I
zAogI_<9}*1bmwPS(pR01^Vr;RNQ<F}u+QE#KC@7sjCgE4Voa~yxm<c0HF@n$ix@p?
znnx<vDp9iz8i%&K$L5aJjG3MXO+#RG8}_)`U{Bws0am|<rc)iMUeMLLlPk0~>@z~P
zJb7whmsXeVThpR?JNi9^;mRt-*DeqZLB`Zrs5_B)z}lV(Y`Pje4iBHanr1V6ygPz?
zt@ebqO|v#B056ASy0xt1-Zm*P)RF@Gzlc2!{;<p@lJer#S%d1OeQasoS$PM*tM~CT
zotvx4^U%}+Hb=98F@1ancxiY*Vg+q;)FMY;{FzO=w&#}(n9^p@sYpc4oWi+9iL*>^
zK7{I;1^+JFMPYAQ)9v`JpqHu#WPK&>-$lQ8qJ6NBU=G*q0GA<c?#OR2hN>=@FTY&F
zF8hVBYAbmIqB^KV*gKUaw&hYAIQUv?FbBHddDwR%9#A_=Bgm$bF~D7dkDU>)@hT{P
z@-rv3vBFGo{T|k_s$gxw!jK8GRSKnM^}MgY^1jw^RgEUMKhXkMc_z&<+1M+T(}<jv
zR5Qo&P?Dl+Yz;qNt;tCOl~*m*+T!7rSp5_3nSL*Ycp1X=&q8}Byfpe!(SsZt0<QES
zH(QZsgH1%|WcLWmAkPZ=ZKpE6cIpw(*jmOkHH=@nuxu9-n)G(n7y~?I5XM4}FN4LO
zL&x=8X&uhM%tJBDf{e*St?=xLb|K$SYvWl-u`_^<gLFbvC#oCK*%*&Yzx^>ppkGBg
z=pKmQ{s5;JOzHmZkLmdBkCa}&{SgmqI9Q3y(c1J4@dp{xC*xGT@Ne`E`sQ2ltz?s7
z)-IYITeGnaJ6@0kzd6im8PiPox|nEr9y4a<D82SB3(1%nkju$V#XOcQ>^1lu25mF&
z%J$MLi3(Pikh;*dA4f|)o+WI@6Sf*W0sp##q4S?Q=5bMMQ;R7MsVzBQo7u+_QE>F%
z_E$Nek(LsHNqniRB<+c=vW~G_q->_xdoAt*8bWlVd#*2jtPHy_jyFYUzfoI_mfAkv
zGwLim4QsOUTU^{D*0v5?&%CBGX#Ya7GdosR134LUOKV|Fcd8&6gmu|viti`j227u`
zZ;H?3n*5>A^+?s5;*;46HcwFc8hI^?T(T06IHW)pJf=(pr(K4+JPX@Wv+2$X{JMbU
zZqP0Rl~55cEONbo{Yfd{`!3ySHf2;y@s01ktFh5t3I4S56bYT${V_lJp^C$M=uU=0
z<EQwtasLHH_Fv|wy1_Qgm7&yQiZ9c{hbOpK;Mw9v`n{(?knUkW2l-M3Zz@w=)}S#H
zcKI0N@pzxmU3*5-Wve)iV#g>bQv8?vYF>-JPDNkyn@NwLYo4@u^0)D@4js58u6g2S
zee;CP@y&&ssqYh-VL|sM>FnYaS%GA8;vEPd(!0<8D{bEw-SP9kQ9&4`^$2A9z6Ix)
z?R#vz--TYXx|6$Y)a~5uy=>IycG;*`jgH!=&*){N{>0DNsOJJfyy%XojXGy9ZXcys
zFZse1?qRS|U*k>=Wxz(g3O4G4VWU0>HtGXlqi(ddh9?54J`i<T;!f<cQIE3?R49<z
zLP&2dEZ`47BHoqLW2t`B#^86-1b@_CUAT$t)l;ssSAXkg?bV6C&{|0tC87gF4+yJO
z$;V{fzvhSfGCZ?F8tmnVdNbw^t&PIAdzI0bMmCCBj3oQ}Ku5*fBT`-9M!(e1!+ruz
z592H5ml~*&UVf?7u)%~BkMW}}p)o`6SdT#CD7p^!*s4+~G5u|<F1`IyQ;mDykI{>t
z+9VIV=YPT`c^keX9hj{o@Xf>z(VhW)BYl@_vgQ%mJNo5JDW#3_W_twqo|$491$iQB
zvCL<Wz(^sB<vRp*#ce_sIQ#L?m($Z0n$JrtKVz|MQ7o3T6no{2OtNy0?uJ_-Z=@)`
z_X%+YjZijO%raegEJ}erEmi=u<j-0(Lwka6B0U_<aT;5shl}-DZ=4o=kLK9_H#W^Q
z4zM%&6PxDWn4{lD$5<Q)od0K=W*V>59@Gxh=d`aw`#Uk4=1j$}cLZL2u}<1EtXAdM
z7)g?rO?%Og>9BSN-+|ym_<PpQeHCkG_=4X;9-@1!ol_NS=V4*8qUo`Au6xoz6uR5S
z*$h4-R!<s>G%k6BTwvFG(`#_$*g@5tOsltu{5H)7cKQGdG>idg>#%dbxdIk&z}lB*
zz-APylL3@T`6VNu=(X7iUhKFizko<Pj#by~AJaZC{ch+?A^KiyeK9mv7}Lc4%6tGF
zh+e<&RP35~v}DD$_LFf;c~X7MVus!h8wSN|dmO0obJ!)<Djpkb85^BZiI)7e*P~BH
zU5VNpXpY7FZdq(mzgwN~yVd79k6Wgk{+55-=hnB^`P>TM9Q9AL5buogmOZ~+`ryzT
zf4h`}$2oo1Z<jvslix0l@oq6X7I83(Cp0iStDsAkO;W!0q;^A6;O=_<FnC0)K$>;N
zz-wn)@!L}@yozPz-C95GJYPH1a!bQV{Kl$l8%Ccrw?p~$Qb@)x!rvk*Od>89QZDqw
zwIiiBfWgdFa`Rt~YRJM<d{Z`f*Uiw_R)W)sf5al><_!l*abnG23tu<LvXV-5&IwVe
zlf=59F;v-60@R~15G{9rN3I=dzb~ZA&CN44OuHa|vhvI-f6V{NW?N)wnnwj$N2nH*
zU*${1O7h-0-?iAUrQ%lxok{hsL%q?+WWzyg8MX192!x3v-nne4QGN#T<p@tBMB5+r
zC^JB|qSlZ3yg_Sq|7PlDcWZc`n=#$@vp#P~BN*e?>7C^BCZ>Z&$v5~KYApQk{M}PR
zfk3h`J@D)6fA^He$!+-F$1FWM8S)3tI1-!RgMYJM4;B0eyZoCqU^R*PH%mT|(&OK3
zNy_o$&-TH;8GhHY0v5u}TH9V)U*;?qlTOrvJL&Ow_TW(Rcm|%k4&!cmaj;s^FfpC?
zcK^~Su=;-39Q697(QU9vl$Bo^JvcPIc_XZ~$-mh~guc}yL_^D(_6?Bq`0&!|A;$)^
zypDJ(Syz^ul=we2B()n`-asm|GktCUmNoTq9e1J<qo(p=B~tsH_!Z)5@LwR;^o6%b
zL$FVaCX>9A8$$A7ZvDV4#`!e)KvRBuG`)Esb~o->Ip~zEcuu?C`x*84pp669rLTQj
z@qWfEk?a1cw6bF{_9FY%<eB5dSHvNk?4^54ZJwmF38ix9tm;U`V8PXCuRa!@3V+Wz
zrDbB#IexF!kx)8KTn<f*F|Z(@vg?I-N3U!Aa!pZ4y-X`$1%ia6gA89;Izx1dLq40g
zpK-xfIzO?^cMY=U7=39mQanwGn@nQ{tY@w=W0<SzF(XS6E9+=`vmjxUwKQRU@Y1RA
zYr1|F^>yqpTK`XTUjiLfm92ehN-C9sn+b{#NL5mSm;|g0$RI;y0Fe~Pq@qZ76%cNc
zstOorwcDvgx?7(?A_UM@dljjuh(WLt(D%CWudW1~qC$)lz5HJk(9Bej)_zTE{%_wQ
zDFQh3duzR)wGMT2@44rmv(G-~?6c3_-!7d{TRTm>imH85x{9rRM!3qJM$uCHx+WuE
zOzl?T-r$DbUUyDh?S@iA4nUDQYjdJ&gVXxDp2^?VwFnqPhMZ}>$(@F}F?$kF3qwv{
z7q{oh-1yov)B3s-_tfNX>;66bR>My8^*(}YV39hU{jJwI_;<TW7qX~}VwOD0FY3)M
z?d5OegZX8^Ct1|<7^2A9peYgen3``BH>3y=cGm?}mEk98mmwp$(cX4g%S5qLNd_St
zw{-BoJYP=1wHc`%DGZ6`1j2EP#jge_4#|TgW4cYpbsZ9oAzA~4c>{4&ZQx*Cg&6Od
z!^)?(uNLs!?!a70cy5UO6<8(UxvheftK@EjC(cT|vw~z^$1>lq-o8b^a=TgBcTfyf
z&T&uoazST-eS#E2brHtOrC4qyc+0JSAkP-KAq2&(7^Q5lqZq2QF)k^F>MY1OgqA-I
zF;ppns$#{ZF;ppz;*7)SiB4<oBIuZ`ogFxX!wKkf(1vwa_wAcnoO_@<_b|@apR4XW
z&}{||VR7!_e&xh%u&9M}i5TotdXuu#VTV(Vu~`JIeSBsHz8(V&#3V>8MqED*DN>L`
zQKmXml||PSdo?0|l5<QWW*hG~XxLzTEyZ3<K&|z@4CoygVnN#i(C_W9>{VvFK|uv@
zEQdWgX<ny3rT)xBqCO=XXzFX~cbboBEugtS19Lz1wFxN=iRORVhGRAV<lEB`DVwVp
zEL++2OJ4&pSmu5H3)C|{ldPdQ{BLlqZW84)Yu_<=rMmk3En-AblG7$-DA1p_fct#K
zi|E}z2hMJ>YU~wPjZ}U~(-L?Qg~}!BGR$5T>MkqnZV6H9Mo1~5gfh=}J*U{n%4XZ=
zVOITBohEJ1ep;QvH07xy%bkN#XQGBvpobtlktvX_NZy)`IxOR+K(9D0#DkdRp-aDO
zK5QQP?quKIZ%LPFH@g3D%`29@gH>tvbYWgkNu&7DD^j9__3<8oQY(8Bh5amQ6tX^2
zEb-_bo0*waX3Jkxgl+?_qH{Dv8W*HnYhQF9olKByOB@iYlcfHlF-YT&#$z&mQ;-sn
z#v?rozgFt+3Ai>O>5<Ce|4M7FxSt@|&G5Ch%IMSBaT4QrAYl2!KQoK>5oYYQcFU8f
zk854sW5A7FpEqmMXuJN1|M~bSV_@}bd7AvwTd~6#muh)h>!81Azmq_Fsi_JV$Eh~S
zIJ1xrdLw;ty-Uw@1n1WS^}fP=eqIaHm-G*NeHvgZ6ps3lO*OSko-;BokxnQ2CSpah
z36x=FK=?ML;cs=By4TuC<0LtgMvxIF3C_MneW-o8%yZd&h@0je+#HFs`r_W`Zi_&3
zMTN>-(w*IDX-@Qw>KvweRJTZT1@t<R*ij>TOEawIh+~Cb7#>qZYk4jtnp0m;KM=i%
z&eR`rTP9u7mULhGh_<8-wS`)dEJS0za$8`3_XBN7xN=*-=g<{kmbg+oh&QMmRDa?Z
z;;Ybh5Wfso#57iSyS<Bh<4uJ2MBHHnj{jr5D}csO-2<<|fpBXmw~E>WS|g}zdHx`-
z^PEqvinUMik<F6GJGxYNeZ2?vzbWdl)%+v-iI148c%T1#G_bTyudIKOW}Gw$*SsTG
zQ<q@cgNRbM8i8kB6}B_l#`N0rIFAQ*2-Dwv-VOXi6*T50*D0LE`v%LY933#KCko>+
zwrOQoT(?`FZ(e!^SiyZYJZ99os8sQLTA(A-4nW%!*X7o4$;vqsI_`)^Ih@xKpVIkB
zaBa$(2`9&6CuHK?z(ZC8ZQ0WO&@;MN_XSqv3629k@;c9B`_|{hZ_>BJuGVgRYS7it
zlifG=gVAcHpA+~G|JWT5VkgKPpI;cgLB*AN6!_(w#U6G0-8exTU90^7dc*dywP(H_
zQyJd=YY*aTos58F<^*2tWBa1oE1S~KY~35v=Io7bpXX6KN43rOaBVkuV%rvY;@WQX
z#J4T<B(#-yNK$LKE3r+#BWdSg)$KO4vwV8D%@@~|{zXS{323&&?hh{88(9@+$9fF<
zK4v_`8_uiuDk>ItdV(zDv8R|GSc@*)`^!_D9+8p_`Xk1q560Fe?Tp`?W54yOhYG_@
zixB^E5p0=g1l{^+M{wz0@)jALX$#)>qGnZ`O<x<27$U|EIHRdZf+hHUFJi3<-uKpA
zaCXv;81PpFr{87J-#x#EpNSPtlg1pjzzporZ~b)YP`z%$EE8p)=ZS|FR=<<_Y_h-~
zV!sx@=)Mq9WwcwKT37emy2$<O^Hk6m#&71t-o=bTnDdmkhDX~yQCMY(TeRFPSY;6!
zE3Lap*pG^c)RA`EQ{feN!8R=g`Z{oz-JN_rEMN@!^Xs30-@BzQHdXv4_zpd<!<QqP
z9Mb$x+_oia>6w&06P_54Q$21i$ws70BtB}NEArBP;3pb`!gzyySj-V&P3ZH#e6Y{j
zYwd6C+t%lSjUGiFvi54yVuH-Et%qVrkOVI8@PUwknD+8`gT8@h%dWGLE!%i#p$i&t
z=31_HW_SO?HSe2*%Cc_~&<|vtTd>dCr3TKw&X|Cmi?S-r9uFM~1D3+1X=;~!pBTkZ
zn~76@uLgY-(+KQ_sg}P+<4oP{vLGI1HT+bnflwEUUQg{L`ND{Hy+F3UNJlY-hW6oD
z^;)~tn|1B!eDufAl-n)OsW6I10j0d~0NM6v?S;>U0pVk~E+Y22vzzeN$ztB-fp#6e
z5{}b@u|qo2(TLgXsUPzLc<a<_gxj}vE_5Hzu4n|jb@gtF0Qd^fVs>VS?vz<6wc$x5
z(osEwMEV}m`;bkt+#UwYjU~-Xo0l~&Z(h;NDrPk<I&Jd~I@iG>dnR!7ZC+j4;ykq`
z-1)1s)?T26_PU?j282%$6)FApuk5+7<~;PgyYA%k<N1c(y>;h3@t)ScK;3Md-}m;P
zu5<P|`=idO>sIV_p0jpN@;N&hA`GyB$N(GY4n&q_@G8VFQEg%aZ{f~9q~8awwHpQ$
z0mDEC{`ya(*O8uupNf))AJV{YUQ#%DoZ*g1V*~NlCp+UC<9hErqr-UJS5N2jnk<9<
zH{%rxfN{goJ&WT&4}3CO#J!ew<!2#hLqXUz0asq|=OtN^>{Vsj=-P`L2s7Rt<OI}s
zP1Q{MLSLF^&}G|S><Ql3&|}G+_c<XUg72LT-PK+3sYQqV2dd#|THRfkyD)bOe9%%Z
zu!ZjupS`Pg8uSlq3H6V9KOuDn?J*sm1}FSeokIS_T@lxamH-F3o#elY{7N8u%ptCV
zH;u+#<ROdc+G(uR;)z2%qHDkt!sy0qz?_pp)~GdnUMeBorwB;*NtYnqPZ&bFkIV)t
zW}R-8+RpTSK+({W93B|Py+30o+<Ol8WFqc;WF}#C>Q*UAG}0SN4yOn>|9b5%UG4Ch
z+eX-rT!*vPDM+-Y(mF))9qqSdtU~`~ScOMJunKPwunN@zQel$qj@Tmaks;i>!&qmU
z&ySUG@8X1YBCIV=iv3>VquB2YV;fLY#5^d+{8wfeNXEz^?eISANcM$j#k1ju{2VOI
z*Ltn63eskIam~s|N1ojcE)>UG*?8b2K706&M@F^(5r~MC6wolZ-+cx+iSGCIy!&(r
zPNH#M+y`+xN9|&jFP>J`#e6iM-^49FonAl6wY9#X>vW+ZXImHd@xbYa>k|aMMzra1
zU>_0>wf0Vdwk)>It^aB&l@YrmVV4qT@{y*8kwdZA--5XtPh0b(r@QZc)$_t}c#FW-
zt}?oGAKwaZVfPyedp0+npW0F1+V{7!o)&n>Z0I@n%4u)?Z~3U+>T{}VeN$WeH0d$B
z2VIKA4gE16DS)zhl2=YH1^2Ey?0;8L`8(vGJL`b5xONC-@g%R9{K>&zhM+9o)?{c{
z*<@%{EgZxia8&L0)-BzS+7&pTb@twdJ+dx$#SyYOzU6ofWbV;ZoqgDu9#6_&?sN8f
z0?UzO!n9?+jzAcmE`%P3ERTVJdOR#klSwizNodSf<Wn0|j?z=>PANIfDfOu$aQ*y7
zLbuepl$;I`y=d0=duew(Au|RRAIep8QQCC=@vbR7iD|PBxji!*wI;t;&KuhnyCaN)
z7mu)B=v)e%cHs;*kbzy%Ep^Jw97xgOIH^to#@r;7^bgm=z^DrQzyR&lF0Z!jn)72f
zgtwzDu-uJkqmw&b8$6NgB5_VmSdFB67v*oDD(=Eb&#~m)mgAwQima68WI7{~bq_RG
z)BGHIma-4`UPjuBM0yGuLtgxn%uDh*={cT5@*q8rL~}mvO|(cf)@W^Ju(TszcUpzR
zN5m*)`kFS`s*mgfW%)nn|C_jdwI5)$6XN!5{K2?=FI*P4uM)PIbT)G*e&u#CAzq#v
z7E-CayCNGpZ>E3M5E?IU(5c<wc2svc$VM<Q95W9(RoHD1J#8+c8d*xcYFLN=skGrJ
zawFsFC0x6t*{xqPL#@7_hql1GG&QRUF-GeVJ+Hn5n0g}0pA?4?D@pRQxK5=_4ci)M
z_=L!Y8bn`Imw~SkNs$TKzZk?{OD1k3<fMTGb>TR_cI#JM14~YQI?$it1HUDvTSsw3
z@eE!v@Q^3TVa*3MJWge|#PlfASRe|BP8&Y=f4eq!aZkzVuw`nyTi-VY_SpX6d7S9?
z2>4<L(xXW7+88wyqt7t|=RiX-`fv_&!v8G?3PINp5~FV`-aT*@em6MJaqH`5sN2=G
z#SPd;;G2Jj{}1W5Cl<pRLthV10`dHYXbszjI#nk9uS-pBOvBj{R?@$w3UNJa+Kf)J
zYfxp<|Ax$@#_`hGQ<87*e(EDcmvtS3?&TtIImbwGV=n^LGEs^fOV<_w%j;r0tO6S&
zpx4qJwmhx4<4K<Vjj*4#;cN1_^1q`E|A9n)3FNb|1ZTSBk{$+3Y%8vZdF;pI2fk|f
zx$y%pwqGfJpdfo!Rtxx{Xv5GMxZF>IM1I9MzZXZu`Mr46IKT8njPpzM665^hTOpJi
z=9kN8A<<uqlersjk<2rU9d~g=oJ`6=aWeBq#L1N2EE~p-1L^|$6$rferKk7>*X?dk
z<p&*#5}Zpyf=UEBBR!{lgwja)qPk%L>Im>I0k@H!P~2X6((x@r&7hZjTfQSk@{RYc
zc{}uN1+)`{UPt%n{gZr@5V!MUJAKP7#qA7-MtE5F!ht{j4BnwRHVW5r|CI73L<2KA
z!@#Ax+sQJjg}1!L^cz1ea*^d?vCHxf{e`=44pSNNeK3x~pr>BmM6LetqxqF?{q1H}
zmR-37UcVoHWD>CYB&v;|w>o#h2&6t5D}>W`UWiF5y>$gzhf?8cG$iT}?ahc642n7f
z(D1wZiJ~KWVI&=AOZ^bl4UbZxhp25A+vz@0RmKN|O#|=&CpblXK&m@gwYnvAKr60m
za18_ySaC+#(I*$kFP6Se*9z&{tv`yHYq*Cn_rSKZH9poY_Z9V%8vP~r6?tzMB`#Bc
zB=ppq)Hek#LgQr{tmj(Li!Zd%-*mO{;|GK*u|Er321sGna|-B$1N@?M!pH<}ub7{3
zd#RVPH+bht{e15sx84GjC%67v*k?=y-pCrifLrL-;kwkHi2v97^YK6Lk8rRG*rfSy
zcGU5<fg-<cpd4v2(oIN9kd`7XLt5@%FK|n?glKrNeHhX3(z&r?09arH>pZBnfCiS?
zZMLcK7SUDV>KG`-Q;p{~noG@#I*FIFJE<3y`B+E64RP0nJL)lJoP9g;Uz_UeZG}gl
zv(ufwH9xw4TYq-H@FvPy)IU5Q&p8B)cf{nr->(8v3dQJlApOGc*8c_eicEhE&=sd$
z%KxSL(%(^)dA^N^6J|y9+8h1mL(4rR|BvL6A-)37T6-3GQV37ORZX~)J%l(})8_2c
za7L-juu8*^@KoF(+dzTm`>N44=Db7bQAOo{31!p$K>@Sb3a|A=J@lM7k)#&4K6_>;
zC(@crd`SG5fz$yWwBVO`k>-0uwFcs;8v35Ccu&Q-_21)HT&2h+N6a&<t)!KI<#ag*
zE2X{I<=EA<MiT1tZuBRpfYC2vSMP4W5_a{)_NYs+tLg7sfL%?P)m<}K+0EiFBm;3I
zfcphHjKr>{_Dd3&fL%>vK!N#6#;z8|1pXezt|sdp(asZRS|QlgGleh8*ww_9B6c-h
z$=KEDCx0Gx^~Il!T|G7gyZVcu7WO#9*wqbp4P#f2lCZ142u56nUEOe3MB6ZGH7i{J
zUN9hSMzTRaMLMc;YmI9RCsR()S-)Pwtd7AFb~$Es?e%(KR>y0YKK*237<pMZC7di+
zz=}9oL2K(#+~0hF3HVvV_g4U&`VR6NkT9+vcu&TRE`ASM2$T$bYmFs1I*dw>QGbV0
zDi4k<W%2vtasRG;Bk$kx=KcH~0)lpggrNPPgrIE+&KGL5?f`J05B%}K+yi5PjqMQ-
zrC;mIIwMQXaeai1ee+q=5T1dts}pSYj{EuFehviZm(b3aCgp^iU1xas6<LDcG+1#W
zXN7k~ZG#_UhH5`LECxF5^pgpi&yZu|%Oh*J<UMN9J(sm;C0caHKB9|Qb4$?nrc9Xy
zZ$8Vf=6|st-V_a%;3EyXQdpB$9OJG1mf*UVs)45+!FK}Z;hnF>h2VY5Epj0DT+}`6
zr3(H*><&7nv2RWbzQlta_)CZa6pE>RPmh49-IG;X!Qa!<#mDvB|CRMzp6z~W&r8kc
zzT>k>Ex}I?0vF~CsB#c=IGBER+v)GVB--$KUriIKLhI64U}~4~rDwn6U*h*7cQtZf
zIQSyJ?d))F!oemgTF;IBD3y!-B`~$i1|4Hh1bIbCY#CRs=MeJ;@7ACVl`o~Aos=V@
zmH!>I*xf*16yJXqxaA7qbC3NHGKDJ{nA*GB#|c&+)_zrmfT`_DYNOS~kQ0@U6NujI
z97L0YRY+^Ee)o9(nKxUeCLKBarTg9Fo#XbvTc=#b<IG`~zBXwGayha)d%K*S&Mw-+
z$6~Azx^_gn?!(BoQ9eIBBgx}+%|H_L$)bl$6g-ojd0D@QP`9IIp5%>t3{Rv$^Bqh6
zERX|e%+b6|bL(hf&q4odQxh9UOM4QxUOkIBfj)%&2>q|kjA`Vg{RllHJm#Obzo5MZ
zeNTNtdq|7(Udtz1pIiUMENI&*ET0Vf#Sl(6;dK*UA?3f+N)Bg&uu+M!>k#2vJimfn
zc&Z!7PFOc)$*Tg{$<h0?Hpn*9WGk673-QyPYp|B(z_$ioAJEGKkq0q@0v9F-egME0
zIzjr5@ROs15gT>(zkHo^XSjW3qkmw#x1eGh&e?8iz8N&%0AGR?hkuj%cu#eAb<Z-K
zxh#YAny-Fo`V;jxnG{*$Q*Ua7?7BhR;gvK-dKY?M^uFPJ#Je6?D+L{%sWi&{*I7Gv
zo&EKfR(Ls6Pu1|n@XMSlP@PW6CuYuRv@|JD3hmrxHfp@Z-ZbI;rMxAl(2Fvh)t&P`
zFYv;CsLPUD{zY|nfUn_6e;zec+h%T5ypz*tct^Vf8lZQW!wlVK3}+6}tJ1nVCr?^;
zLBG_-31kg1V%G>{>KT^5CN*yKCT1nV!=~Juyh&*r#5r?WA=Tkr2_g24YEs*iA={L<
zC^^U}ErVF;5ECh24<zFMo1vQ;-qR0zMaaBJdr{hxl6-KrJ*nKMwC|w(yU@2M*70s2
zk`Dq8%Up#hTiz^0)yhVcEiN^)N@x3)n~WGqQ>vnE=iy7E404rI@eAaz${g+<?3`5<
zlM#hPiFedhm{)LesYbM|G_K0`hy9=K*Kl_tPI1ltj^KOy{nz=g+t#nHNaUQpKkol*
z|F>f*nmU55^@iY+@WQb6TVX5If*k8$UsY2Nxd>P#4|x%3tC=EgRd*LOE1jOF$05p=
z(w^qr%MpV5DqnRs&LvZC2Zs9XBP<|jbg)thKONE)Y(`5T<zlPW+qVc70DGTaeB`Fa
zsj2LnExDHC(D^l6>9ibYAh(?^!O2I-tE<1Vc{^TEEZor32P_KP@j(YgGCOBC=nGL+
zF;4Tu=x%hX$SSnz*^M`!S#;Wu7-*r9&%Q=}9r91)NK0&Kc0==*hw}4aJ!$iL>LaQ)
zz|Rk}T92(oWq;7+?DJ5RHQ`%5_G_A?x0?nr?%J=9sC>|o<|_|~djIj<IGhu10sb%W
z2(qzal_@y`{+F!><hWi*7^7+5jvk8Zg)_4glfY3CKtTt7Ads#I5pN~0K;MG5FxOFx
zJHmG*dm1_mAzN?aADSDU$2nL8e#w7;a8DN?Q5-koMPYw*A{39Dto1|j!97_c@yPdn
z!(9cBoX+;J144Z?s1NBx36GrcqhjAed_#OsoD)Ow$Vsn1@_X<kyb2z9Xqf|V{`c|7
zC(U6a@W_jBhcsG}*Mi{Tz)H!^nsmPOeX<d!b2(}YbDiZ)!BLoPpLHA~%q%ItY-<|(
zp#@e5$RTLU?n2r6So?(}a6u7bce8;6`{S?=E5eR|e1I&?YWUodKbED%vhOG#<1_>d
zj#>7pD+#l>@R*{)5G*>z^etst%>_;!Ou)(MgH2uwd9-LM`w?MBQx$E$7w3?&wL@6u
zuW_3BFlNX})4aTUA98F~+1Q1#I6>d!o4<dMtO4{Xl~Jx%&LP;l0ZlNq61H75V>`Q@
zLVTVzd|__1sQ}}_3BOxI5G#<dBcPhvTOv4%)77hV9OV~b+_{h8-ZAohzJ?<H06FRo
z!OswK96Sv-wyuPh{z%=*rkHe!_XE3gl;rHbP~z-9O6^7)EiF1w!PTvXKOTofU$iuP
zS_Yj)D`74e=N;OA56X^kJl+$YHOIGnKiS1?NG<ofIOBzs%?ZFMC}>>TvFNnNyS84j
zumM<7G(IB{2Zrg#t*XH;1!w(%<(%R|(&m-Cu5D@NG+)QSnz|131ff!+?Nv9}l#VSp
z2`Mt=G%3nI|J%6Amah{xXn>vZFdzAW`lNW0JpnYE8Hn6@l>hxa|9~rCw0i3O1I|D?
z*3g#&hUPd2JI|aO-gdpMay<Ta_1olcW*f)~kk6UQIiAk9h1oI!w1sxG89gLu-JW%v
z<zsiPudp0baj`q`+bkh$fWNdDTXfDH1s<d|pUw@)PK10B>5PGV1(Z=D#xad~l6`3G
znUH4*>;OJld()b!m^aDitQMzf!1#W3*AZ*auEV>V#-?c?b?s`@d>jtkLCeb&-=yH{
zs7h^{<-k8&5p5P=fKkhJ*tbyc-_~N}=#585yb&AnhEje*Z!xKzZXkAHUVZvAoU<Yx
zHaPmW;~Jqhw>RI3+C0n0XbSTT!FyW_!8=+sSP5Fn2A!LHn-NC@NY_Z^NKT{;NQ8b(
z*x2_V-Fs>?&a<Hv{zFt-6}W82^J@`{t)%+_0dIIiW5>Y5-j0EQm*Rx4<6|oudfw^Z
znAZw>SE9wTW&><HoqZYU=>5$}HaZ&)Po>^*c2i52wdgrDxbic)J`O!3#{3NEbHpov
z+q<-!m|N!AWz9=`Q9Es?mNvo$@zgTm|3&{Jhy$~Hh5=ihVW2?Z*4dDDW(#@+Ri;}%
z4&H#*A5QUI->4;jdO-`Wteo!izdhY2{*?`0|6QFQyU&Qsx$sZ6i5!m+LUNNrkekeq
zS=srdA?rX_pJ;ED)tHU8Wc#uk*PY64EJY$5g7v3v0uDh2_>zGaY3(6?yMSxLXeHeT
z#b-J9`howu5*S^ca$tm?;@n-p6#Nv)^`Dr>5!dO?PdWEnUvln(cRBZDV0wpQ4?Xl5
zaI;}2|LFUi`wVROv^b+CeF=jj3XK5~msQCQN#lWRgg-pM3HY6A@c-w)5H|u>`+g*v
zx77kxAbgx*PxEu)NbJo<zr%iG*rJe?dhks-j)bglM0D(3tj^M)3@WN_wkd;3NN9=+
zWNo73@K;s7jn;%P8%gqOaO%S<j&gQ*Y}^BXJouhw4mxfu8CR*|3W8e4#md2o*t6Dt
ze@jehz{1L{{l=El{K>Ox@|26M6gR5Bqs88G@+|)9*Yd2zh-<o|TpZ&}<hIUZdVQJt
z!xBh##dQjYdKaNH^79NOZm$+HzNPsM%M9ckgiLogSAbllbsexECLD{7;P2|(umW=R
zb_Dr4hPdC`U|CY#qfFCQBys-WQ+2@cM-Epn@cD7Q3U5&!+7Y|Dm5_*)X<-$xNWhh*
z0$%VH#mBO+wv-;T>@Uone{AB9er>{k>uWb0i^jNER~O@qsw_L^3C^p#@mLhTUm<+I
zL|92lq8irPlI%qDCHTs63w}walKYfmM<&8=!qnu<BafXl*x0~Y0r5jE!TP#~o_^x&
zLx|k7rTOxxlCY%y2~j02uU{>yWHfdup;0A^kB3H;B)gX~$bICeDA%9xpgRVSPD*C~
z=b)awe$W{7sEm3yGjbk;18Me}Sip<loe2u1Nzc}>I6Xs4m9tFwg(f4n2D{h5LFCy9
zIv~!81<-o5qYZ4QUo|VNre8NJG)GF$s4V&UC#<lRo)6-=(O_f741_2wR!7l2gH)yw
zu}u_AW4bk3v6=20JN+uubvx?1-N24c(y|T}-Twq_Frf_wsSO#d<sh{o8}-Na_NqZ9
zypO+yx+dfP(gL-X-o>?W&&?^BTd!nkdbAU5)aHn7)T50^LYuU#u!i1QDYYko`Moow
za^yT}R#crJmFY*BL?=WE5okg5lH0FV6xC=HVtEV(a)@ON#PuTca5=>z%Gts+()X!M
z%1dPpvUO&)VxCYh#-1~$8|s-_QS4DBsgP%_S)(YHo^3U!>mOzsMUm&n>L5Q?vf>(*
z^i8pj#VE7ToQ3a)OEe(*a_rdldnFoAmFPiqlIfseg(h5k6VU&1`#?*9CQ7vZLGS?a
zK_<#QFevhooG()Pej?tN`-=Et6BBs?_lNp48Ra9&jp^S8*9g2w`~toJue`oJBZOa0
zfM2q~FBvk=b8cov`5f~fH2(m<qfQ55-zV@WXf(tZOzKB!Bh_1{!)Fym4IF55M9NRJ
zK>a4ky#BsL<aK%cL@*0SG($Zu$){jpCM63ug(<}L%5;g6z8Mzs9=$KnMm;=U&`z}d
z_3h@L(0=;1T*ieWv3`$A{T%v?#w4&`gfT_*qVeL_tJs3M;+T>7l<1L&F%n%Uj<qZ0
zWmgz4L|Y_z9ufFgZl{8&Oo^;Wpw)j#ye8+B#~Jn0$a~<OgNV*#!rVfAgnqEF1ieV7
ztCgdZc#r16k>$zH((#PSorqsE=w}M)W4Z6l60Z^u5PcCf$#f-JV9pfUn#8s+r9}5=
zj5H3d6=^BIUkDn|_b#V>ILb)GefkcK(>iH9Q6Kf@7Mgk^#BZo1zL_~eq=A{W2>qC#
zP+_irSeWZ6Kg~5WmEt>cA5c4~e4^p10+CNb@A=|?nEx(Yb1?p>Uw&+@8SaCkYNo(C
zgt}!(?Fd~no|ft)=l@=!YmAgvzW+~FMEtN*9+M;ci}KM}Mm~&Xksp;K#$D)lWm<&Z
z+a4#<;$CSC2z0y3I`$gorDDuW7HM9hK6?b~kX@>O256LCB#tFq3w<zh-J<-|XW&^{
zn}soiaZyX(#XM|wOEi$5f#-y0N<6zy;<=H}=)JqH^4=D#aVdCC^EcZ4gMCP2aAetm
zSgetH3)U5-iTZPp6`7GwsCR+X?lj!Tn5Fq&x^MBw*BPv+_KIbKH^nly2r>qhL2G8n
zd-d{|Q0QQ5D~%7DUzEBc5Ah<tIm8=xCy4zhzyH(t;L<XPzi!+s&YN;MBrm9$$jjLh
z{fD0w<C$s}t=q`guu-Wr<+H#GGJipyIY{+BF}JXKI%^ha!!hr{Y^=v-c6@t2dt*C|
z(OjeW%@m1uh!;YyWnMx*o2VZ#hnR`iWd5_EA2Osl#V)O_*M^iO)9z|>3$4T8>+Rs{
z?F&NIp^<W%5%U0j7n+G#C%D3VnQuwvKwrE-{XuodSfu$_xLz;urCbN4PMoXOO0=Z=
zHjMK#Y;BDV^X^%;RhVND-i;Am>E4&}J(GN|(DaqWdu+5Qn=!7?94~!~>UZCW`k~KW
zK-xp~qp_qNQLkia-oUf$xzaPD>D6Rw%=ZV8Bz`Zdk=rZCei$Pm&pcEPJ(uS(nO9|+
zT&-W^GDh;U%nzaSyZrswkh+I{(`aT)=IuX+@W$1yuO^#~TpJ9K<-zX)9b|rB$x5b5
zRta+YH)?VIVhOm1Gzs&Od`<I-e2u!kfF$$}&1b~t*q2~sMX<p!;`n%|P+ZG^A-kFG
zbF6vK_tLyX?^8YK9zBEHQg6iDSKE{P9do%lM84F5XSL`j>XT4eiPmc>4Ry+<vhdD!
z?GKERpR%`ERs65-ZLppuP<?1`QzVsxaVOCK$M!bho1uK5mv9}<)(A8nxlfoYl`Vct
z9LqHSfG52_WuI{Be_)^R>d)OLNPA<*UEX}5p8kJ%&+t#F-${;>={q0y@}+q;Mxq<Z
za<r!jlm4c>vP?p9C((=U$?wf)w7(18cQo&$eDQ3J(66*#3f+f<NqcUrp~8H6wS5SU
zZ{u_XJ&^VxBzuAeLvxN<x=%cOr9H<eXaZuGp+1i-+?B%~`^{|jTQ&!2F8ge?f!+C;
zktM$|k;TMJVrQmjAR(`56qrL`p8wt0s;$cmEa8@)5nJ`j@l&Tr@l)>{5kEEmviPa_
zX>YOIw8;_c)AlRN(h{R9(r!$2rdh^kr~aEr5}N|@T{vU5k+D@v-87!&Ft&i=oX%!C
z#T=x$>`#9(u+x7svgwacWXZ{s*qe7|Amy>CMfq%E4#h&H{JG5Ip31n_=<oQS6_a)F
zeZ*v4Fq!FFhhwr1zK@u!3vzKUBqr<M$NWf4*4eC}KR$8H*m2`i@}^FkasBMM%WuB*
zwpFWtx#?GT|N7qhckbHrO5@>I|NX;{KmF@>;Eg46jNKoL*DA)`9g25L8xG+gfzcP>
hN+JE@xD{J-7c%w>e)WDa$G`snV1$A#ReyK){{wtMD_H;l

literal 0
HcmV?d00001

diff --git a/dts/README.md b/dts/README.md
new file mode 100644
index 0000000..79112fb
--- /dev/null
+++ b/dts/README.md
@@ -0,0 +1,39 @@
+# Rebuild dts tree fo MQ pro..
+
+see: https://manpages.ubuntu.com/manpages/focal/man1/dtc.1.html
+
+## Notes for re-generating MQ PRO device tree (`.dtb`)
+My notes
+* By default the Device Tree compiler (`/usr/bin/dtc`) should already be installed, as should the linux-headers for the kernel.
+
+### compile the mq-pro dts with the current kernel headers
+Example here is against the 'default' 6.8.0-31 linux kernel from the Ubuntu 24.04 release
+* clean the `dtspp` folder: `rm dtspp/*`
+* edit and run `bake.sh` to precompile the files against the latest linux-headers
+* cd into the `dtspp` folder and run: 
+  `dtc sun20i-d1-mangopi-mq-pro.dts > dtb-6.8.0-31-mqpro`
+  modify the version to reflect the current headers
+* move the `.dtb` file into the `/boot` folder:
+  `sudo mv dtb-6.8.0-31-mqpro /boot/dtbs`
+* make a link in `/boot` to this:
+  `sudo ln -s dtbs/dtb-6.8.0-31-mqpro /boot/dtb-mqpro`
+
+### Set up Grub to test boot the new DTB
+Initially we will test the new dtb:
+* backup the grub config: `sudo cp /etc/grub/grub.cfg /etc/grub/grub.cfg.generic-dtb`
+* `sudo vi /etc/grub/grub.cfg`  (or use nano if you prefer)
+  Find the 1st `menuentry` section (the default Ubuntu one) and edit the `devicetree` line to look like:
+  `devicetree      /boot/dtb-mqpro`
+* Reboot (`sudo reboot`) (remember the mq-pro is sloooow to reboot ;-) )
+* If the reboot fails you can either attach a serial adapter to the GPIO pins and select the fallback kernel from the advanced options menu, and then restore the grub config backup once logged in. 
+  Or (if no serial available) remove the SD card, mount it on another computer and restore the file there.
+
+### Check that we have the correct device tree
+`dtc -I fs /sys/firmware/devicetree/base | grep 'model'`
+* ignore all the 'not a phandle reference' warnings
+* you should see `model = "MangoPi MQ Pro"` at the end
+
+### Make this permanent in grub
+ToDo
+
+
diff --git a/dts/bake.sh b/dts/bake.sh
new file mode 100755
index 0000000..8e20d99
--- /dev/null
+++ b/dts/bake.sh
@@ -0,0 +1,4 @@
+for file in `ls *.dts*` ; do
+	echo $file
+	cpp -I/usr/src/linux-headers-6.8.0-31-generic/include/ -nostdinc -undef -x assembler-with-cpp $file > dtspp/$file
+done
diff --git a/dts/dtspp/dtb-6.8.0-31-mqpro b/dts/dtspp/dtb-6.8.0-31-mqpro
new file mode 100644
index 0000000000000000000000000000000000000000..1e499b350a17f2225a7e88cbe3209aa998abdd55
GIT binary patch
literal 19857
zcmd5^U5q5xRj%%t*-c`vy*9=qc7Ps_<817yc>Z=g8w}~Jot+rl${G?N7__PFs+lRa
zyQ|#Q)3duEu@MmuC=Vo&tOyBdiIC=j2PB9hA+!pQ{74884~c{jf(M>JF^@b1zVF;~
zs&04J^vw7taCh(2z2}~L?m6E*_uO06UHy0Ge()bb@ak8CAlM3m&z#5g0`f!1EF&#^
zDG0W|>&jz)8(N#gbzaM)S^Ytjt<Lh}uSWgd>}uM2^|jX3K_)%O`!w?6K^kX+Xt_t0
zJPmtqggIEEZucPV_mjbLvEN@?NyB(mx&@86b2AG&-5ahdW8P0WJL%0NMnl$-Cdywx
zUM9cCOMO2%QGcb;-z3TO{}q(kw~5?{(<1Lix5A{qoAwh>9N!YIi#1w?NASN7{4p|d
zp<Isje&n0rkFIwUwlT?=Mb=@NJoh0l7HKc<CgJt{f@God`kP+)x3zrSe6amZ<!$6?
zzcU<k+iNS5Ko;2_#<kWq<u^XsbV!ARfJN!Mg6kh4e;%1*{i0sKpx4*+`m1`qrdQhf
z2=ceJ{y|(h2WOC(*!}?Wy(qsP>}5qK=<<&wwlVz`vX#H5W$N&sT4o#T|2<xB5aY8-
zLwn;x6ZMZy)Gwk=gH>MRg^Bjp#_Iw7=^S#S6ZKa@fas=C`a@3R+SSWz!PU#_U=bSZ
zhMR+z1SHd&a)^QW2-;WcWo<wfRUDJ0%V$g$*QUto^*WP!0e|RqWhJ<JWfd9vU0Fwl
z>?`B4*_VSM`Fb*jnCwYCo$PJM-iGXL$liwRZOGo9l3l0w!zOz_8Vn(Pce4V5Iyg+X
zHzDsiR7EfNQ6m<9QpR=V{EMz8Zz~)Oi?D-SPL?Nk3vw@+j9GFSmrA(+`1)3zyvvYx
zd0L)=>SOu=l_xSK(uJL@KOAJ;ZZhB^Ud1w|Vo2=AHB`HfJDq*wp&w%nbGn$NpRGfG
z{c#;~T*{^2+^g1LY75bHWqh^x&-K(BugiMiIutvixI@)1sp^#R7;>%NyE(Ygh(tcs
z{dZBMxRPcu<Z4B0+*YPmMUy!7lF})!E*_Ik8@`0A#qLJjOR4nw1m0`lsnwhO<6GKA
zY-xL&p){aZrTbxXj`J{P598?tB~l+Un2i=k85<0fd)z2`SqzfVO8cMkXkSN}HWNqo
zMQ(g!a1$k0pM}Rag-ho!T`LI3x;KYMVgcT1C<g0mmqNBkGCP393J5gU?2tKo26X~N
zJ|7F)YkuD2m;K@hES4%64a0(RX}8Je`X(kr2aAk(T3j~XeO%g5aSE4ZPj4TWUsC$#
za5Zda;qs*NK}LxSV*%~vl``HDF2l4Z0qY`wS%EMl%G^M%T|dG<?loI!7_F^`u0{L1
zct8z<;4U&{5(loImytQAujrL+taBZ)hs2_TXxQ0{vt2kdREtzKk+TV&THOxfVK_*N
zWH_#$JF|vpMMor#XZqbmxrJ;r>i1b>^EvJtrWfNb6L}f`y|_!V(8V9A!(cRVj!Xt=
zgyWsy?5v@jhmaSGeqJoc2O-W=A@@BBLo%HXn^#$-N<u@S@ux~459@z{tL+K2jdpNv
zHakeOIQ26qtL!osk(V^gQR!zq-_Raj*(QF5#iwCOXq>N`*^THHu1u!SU!zQnY@C0L
zlbvY4E2hc(0wKc#Ym!}s_k?)REaq~&li=|q+DUaP@!%e5dfMJZUebI#xYrU7UfFh1
zJiyxcSM7s&Xb_wGkm*}Cu8&XSdUrn=X4!BL49fGPxGoNos5?w<EDwg=t>@O(<08E7
z`wDgaFYxhvOJC)jGN~O+0%mQrfyvs4yR~t?nK)0AbG3E)xuWZxdafSPPKr-CS8dP@
zGn*^&svV{80t=ZdUfEVRSF%=X@A)d<?3~_SPV1@d<@~bKq`jZ2XysZZ@1(t)Kib3V
zJFvGrMN!5H*CHW4wY`sOr%8J+tNvUkHoxSZw3oh3do6Cg&G}t@8?nb+Q*?siCyK>C
z23_ms_XV}hx0k$=_A(yPUW-eovNv7B5&7Z@A1y$H$bJde+C3D!<GUwz_tC}mO&kd)
z8aA=*udfQ7Qk`5bcI;OzTuPrHjr$Sr<?Aqb5p?x~a?W|bG>O48pb-OJ*(MmA{5*&r
zm@H)Wr5+XoCB_*>>Ja34k1={u)iB!yqsNrU@rj%5*`G#PX(dL)lQb;AGVU#-PK<bE
z+k1kMZUU759%FO?LvX6hcERXzB`O{zMpr7n5+mX{iBSj|G2-<-!$>!d9|A_4>M4x)
z+>pdcjJ7LUi4pOf#OULo5hGsTb&T-5jPc077vp-bjYr@`Q)vfcOB>ZGdq1MYNqfIq
z^)2o7_Za`&#l8?M=QEyxSSJRx&xOqfFJ7F&h8NvXm0gUFPbqQIhOdFHw9<wbJlat<
z*g5q`8;V;69$K~etU$L08D|NyYv%&|!=z^qy1-TH6&zAQcZ(-7Sg~i~GFhlk#$Lb9
zXC^$?NGy(fkqyG9Y0%HME|GmC&gcgbh81;cp~~|~Nh8jjf9gb)*=RA=e2AMQ+lZTc
zeq&GjOF88{AifGO<TV#jrabm#oomNrvHnx2Puk2e#O7pYzes56rcH&&Invf5jnP$j
zWY3)ozKAM^xA9pV8;}0L@nyWu;8s4&Fd$bUwRHU$3u@=y@t1sVOjzZ%sZtN(`yw)1
zh(in6@O=Vh(uotVYskcp`jD6B&GLEKAnFCfL4OxCCbnbD5_k3&J7O@7Im>G4EbPNQ
zveus7_?!~B!@2V<T+Rn`=LtxOCGKOJSA?H~p#@3xk^PACYW8xz%wF5epVf9g0B1kO
zmV1@FQW3V{=An5N*PxAj2N{WU%4hQZ$L3Spo3CrT;DXNr+8Y7|Z4ntq`Vx4JN9J{&
z5-R&i<GgMmo1Fy5>@@q?PF=`<FWS2vjLR+O&f*eeH8b*QKU|u>u4T4;<$d4(`#WCS
z?`ipnXAWqc#)mY+=MPZ!^l#E8-t$r({g8>gNX>8IkM;Ww%4fa$-;CE~zaSoJd&7^%
z{#@A275Ppv7ZlBG@?|bAq3+pI&c*XeXS?b%b1qEp|I4}H*x!Y|T>sP=srhgC!!p}W
zg1_AdGDi6LHxAOBw7p81CNDTd*<VL*qE0{HcvydeFa3efujtF9GX}hc&sm1yL3ASl
z0f}?#&#!G#<ljK9jXMb!#n^|{{QMz;Z-ml>e(cY259gaLT&Cv!6Cl>j{ZA{M?IvT^
zIyAg%=6=q@XL23R**z$SY3W$J*m;`eb*0yxJ*XS?XY$4wzaJ~|l<|v?OUcJR+%IY|
z1@APZ@;L@uBpDvS^ePBbnEoV)b(sFF(m#W%$#9rfpXoqYdH?k&_-He)<cA+keP%%)
zy^S`G$8$RQ-YHIYYM`voAs>ZP7+;@()$CS?EinL&Uqp2Z#}<fnIKHg(mvB7^j(i3}
zOzc_6aX9|C%6;27?ibhF8;sB=@V6eA#~qFzfvm5G(f~~=8xQ9NB5`-KoBIyeis1x$
z^DVapm)O|e%JYx*D}9FNN~O(l@8x=AGTLR7eHzA@+osCOQ@4NK2cFk*Jon7^l0noZ
ztBY;<-Yvn!yU(G|*7_I52*J<3)P;K-?5CNHVE#O-xV9MDxa@@odN!}1&ozGeCCGdG
zEBsT%YcdlH>dZ{JjP>_0*2*;whQg{8Ky~e0kG8%pfJOyArfpc4%}n~b4~nF>D}uxI
zufvBJegW-Xyqb$q=fgni#4&geL)>LgfMDY0@A*%mtroXruagG53BF>Lc0#Fu)5)d%
zz>rQ<Vn!N$h<?Cv4Qun6j?xpoM#|&k^0c<`;Q{+Y=G<|9Q@6IpZ1sHPNLw@CR;gh0
zQU}^fNT+PIGc<K27?ZY|jj*Gfd)oN!*v6f`iVH{DcI-U1pwYB#^!B=Wq<@jVqgO6q
zwZF9S8Evz@*Plm%NPftex&Es;gq`oo9JZ+T)EsjEX2awh#!5H){5hn3lXG|~yOJRS
zT0a@KH@r_?oy>K}u3wM6sP2rmxq%}ZT9{NP`0G{F#MF|;waL#|%~sqyAihVPbnphK
zRbTVrSCxh{W^k_<_P`3Q$yxH2^ZgS_18)<j(J5YxIkyiU`;4e=%{F>*no&5C&4qmi
zjj=;(W*co_@-QDer-|=OegDZpz2dsc7+WaUVjU-I@)gplBk|tF(Av<q#GAp{!`qJq
z+?S~D<H*KeK2NA<C6>NTpG3P?ul=4B_6|Mo<NK|H_QmS7;KpmA{YV>o>=OzkrrY5H
zwP&v8fj+@;n0P&dZ2U*rV*KQz{oIFWOC!(l-8mGHtc_*Q&T=k=_lWzXM$(V-EbR~3
z8A)Z${RYZ*KC^K-2lNR)H^lb##VU$A87=S~gO?lx%>Kg#_Nd2;HW3HAPe%-?o+Y8I
zGGy+_=VL&;#E*Xnc<~TqbHQ<W-{E5=dc;NAzUbl=nuY&)Tx+rFrTC^cI*gx3%X`YQ
zS>+Iy!-Y@d@ATQ7r#{Xj^&`sP);eRwhmfh8&Bal^$o`D0YNMPf9@9FO?%Z~)2SlaS
z#wX4L+L>ngo~?89y^nz3$FhN;h@*c7V_cqrBbA$qL~?WPfGm|a9DrrHh>gbhKMPCh
z+ebG3lVZv9CzE0;>zvq%&kXS-KOAN`4CcMyif}q!-W%20Y<)al=O0%{k%h*wTFB-L
zDazD;pjXZl>p3!cxwga}CwsIK3`faIKnImX9_qYoV~0cXsPf{-B_DJtV>RtDyC-6`
z;6VR8eY|rhnOr^>Vw&Z1jBm!z^~?BYJ~u0dS|6~F#U4HjWh%#P*XyMHCFa__uKE2E
z`il=(oNn`^Rq08)*zU`)bA-v@nReWcnKHnAoE_CY9LJyzUd$Cc82bztV#(Mzt^*@U
z#X}k7w?1t1WLA4wiNo<&wmf;%;YsAvV!1dW<D)7=<S>@CH$bWMrX9qjoO3oJ`SbHc
zRTuxhfciK#7um)72);ZT8IO$J?cgn(>RaiE3>FHd-|V=6&N6}<L*v4EkeH=EX^eHh
zhD>{?KN~Gp@U%;Mj?A`m$nxw=mV0M!1$8F2J%sFHLXLw{w|aR<+ab4%1w@l_H?<9W
zNHe3l-BGN^9g#^M#tNo)D>mpHIhput^|!N*m%RS;J<f;BTj{^Yuc0R=WVBR<$PwS0
zDFfWct)ZFyWgT<hH5_OM_hsJ?>wWRLa+hM?4<pamqef_!F`OT6vr1PhY4pPz$eeS^
zW25;YeS-S~6Wb>J&{<f@D*cQrOzm?1h5G+TKVs}wJtbB!wx8CI7_)pCjA=H9v-Y)F
zF^n<Gm-&Pz)02IG`yww&!7s`v<@$49sP&CJ=dG@cA%1aIrhUvW=mQ@^HopL$%r9xw
zLG_#a3d-C|NNY^p&pszAt)PvGeRzhc)d{w^H+p=%C|OjHzVvnK#dyv8J0@N^HuYrL
z#_+ylF7Ni_-EQa}(}GF)*k|HQRD1twHa7;tPWw4|%|}e)SlsRF?HSfQ3X#uNAO)R}
z*x%ugNbK238rS7rC6ezEWSf(-C=&zf#l&`5oBTvv-f7YghqbN7PVslcu2H@-u(`5&
zQXkT{0!kasG{k>eI;Pq1b=1v=?nilY{@7oh-&F5nfujC|Tjyjj*w2T)pHsmy1d8p%
zp>_`PF5X$fbF3&{?%?IDQ0gMS!k$`FK_u#e>fBvipGLk<ubdsWF?|o2WptVQ7OsC>
z)lqUu+vOciZ><RCY?HN8V!n!ns}B#+#`YuE?Ih-nTr_WKKg0ZYP=7m^b8Omrv+g~N
z8_6xcAhmMIzRB)%-2{Iv_T2&BbDO#+lojCG(9_9~HP8&cfvVU;J<Jw9<1<@GqyMnJ
zhpc?%zVoco#D==>r|Uaje4YYU>3`(<J>5HAEr=8U_jRWaneJ>f-G4#pKZmRF&w7{X
z3FU)~^7B&mGrwdRYkBJP(mEW-3!NI@#FdG@DE`>V_04Rj6L{vnGx1J2`5BQ_Ms?qS
zzIyv5Z4ZHGv0QeW!5}R<BX&m8zH|S8K3-kU;a2zO`O99Pe@40O)!%aJlrn!11b5JE
z^?9z}wpZu=e#fgn<MD%ceoGWxE=KE@z*Wil6w2Tgx#au&V6?fB_M#nqkyG)Xzb16{
zbi5b9+fRdD5aFYUIOqho(+*yB<)z@?ouuDMQWW;`p7jCl^S^}(=R~oZ{~F56$c?&q
z2s#sad6r&uHUQla+#NPa8?RpMlGx<WCC{JqSB`7Bk>z<f<eUAW&X$wKy=XDRZW;~K
z{%$CbIE!$^rDQrwtRrS3V`BwDV?1VKj^}@$9X|Nlo4ine><{yQ7@Yg_yOPiU<-dSN
zT|~yJ$&jTh{H2WNANeP+&6FW>@Cm8$eE<c;N~x~@P3Z6^DvLVN7cnQ2xrVv#B2%24
zH@NQPzpRX)&9eJPS8IULWtQh8izYZ%H{@*H#&uD05VRnZV^W8|)iN$<b>p+l-qeAK
z=K${EOlO44mG4KHeVERnB+8=v0Lqll^dQQ1wx36N(UGN{Jm1HV|E{#g|7b#;crZ0R
z8gXHo^Jp!hK!`_cD{aA}-BH?^ie{<@XDgbS5ZqVMTG}<ZzoNB`cCMn`G1>zqtsEkF
zu%x*m__s0Ybl8VD&^Ek3w!7brhS?yLU+Azl_{G9mkC*jFgI8W|gMocn|M+-a)&<v(
zjT5eq<YCQmV*z&=%jb9Ft^M-dvGK<1SJ1}sR390iek0>Y-83o^x%Fo|&K(P{J&Pai
zcvimz$)nb@)fd6Y16d2N3y=3ABG}O6WOi_nOZb%5jfuTrq2pLrKC!yW&ocU3(yILU
z*$`1c`DI=1=4lpI4Gk3CCqShg3z_m$C)m@7i(xeMep>|d*1&!s=VJ0ajLby4o$aGI
zUK@!jY@apHf_*g3@34RR&+ecv`@6XwuM>M>t?hz6*N==JLmtXZ$BmEmzHoMe-;Mw9
zXYXi#H~x6t#+UIhoJH~D#&f<l&hN%^F}bpLyk6&P+_z+Wx>1-P42t9pki=%r$s$}$
z$)Wp+7`B#}EHGg6-sTK4&lOy`KAxmeKJ)vRqBzFc6+e5Cbh|~cRHV1Dbx9eo&nMlW
zll5|JTG-J7cdwf55A*$D*pGTx21|PXDji&TXOO(Hk8S!^knctP82zdfZJy>y7r&=d
z1nPSO{QeJW{1$#c>vuAIfS%yPziQXcBOxH1RK&t*q8HUf7C?1xUvYakLcx;ba;8>;
zIC~M6@M9fev7hJNTY=O%W3_m!mW<VQ#%jA(lOGb<*~jngq**^$l5hVgyix{&ShpPj
z)#sB)Q4C-xA`apr+waF=9HnK)-4LDd3rhIp9>9dfUb-_3^jCVY>aFCah;Mm^dr`q3
zH^Fb41aUG-JBfU^G$b5Fko4ui;wt4APqk5AkZ}4rtz>!&2wIXRQJGq}(MZ!tT@rvX
zCH<s>+fil2EAz_QiSn?B!@YEOugDX;!rqH+hL!j9vyk6k#SOZeiYLrYMZHf65AtBd
zwO}*$hF4)xmkt~Yuj==*5v}z6!YNEG$n2?s8Wu&kdTndO@0Cks{o48{fJ#N|{^DB=
z$xS|7hL_(e_{RVkT;swCmPm3&%NM^!G(<IZFT-H&df70+PfY1Y-b;DL2UKy^i_*UK
zEuFLoF&<cflRK}XI12bf2-mS8dAPaxy*9j+CjsJD)Y-#NNb&cv5G-z2B+LWmQ`@Bl
z{x!*LBw;Qq6w~YNhcZOnq1GvgU$|0LQ3|Q0R~2IlEDFYuEJIM(Rf~BJSDbj5-n$*}
zf}c_uWTOmk^*iCo2yp@*LWVuu33RYR@YtiMYZFFo7(@r*5gp6p3cZ4>N>496%!D^~
nMTf6e^bxpJXZsS+N}yXfLS2lQ86t}AA)0ox0mO3^IA{J}PC%YT

literal 0
HcmV?d00001

diff --git a/dts/dtspp/sun20i-common-regulators.dtsi b/dts/dtspp/sun20i-common-regulators.dtsi
new file mode 100644
index 0000000..2a6f5df
--- /dev/null
+++ b/dts/dtspp/sun20i-common-regulators.dtsi
@@ -0,0 +1,32 @@
+# 0 "sun20i-common-regulators.dtsi"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "sun20i-common-regulators.dtsi"
+
+
+
+/ {
+ reg_vcc: vcc {
+  compatible = "regulator-fixed";
+  regulator-name = "vcc";
+  regulator-min-microvolt = <5000000>;
+  regulator-max-microvolt = <5000000>;
+ };
+
+ reg_vcc_3v3: vcc-3v3 {
+  compatible = "regulator-fixed";
+  regulator-name = "vcc-3v3";
+  regulator-min-microvolt = <3300000>;
+  regulator-max-microvolt = <3300000>;
+  vin-supply = <&reg_vcc>;
+ };
+};
+
+&pio {
+ vcc-pb-supply = <&reg_vcc_3v3>;
+ vcc-pc-supply = <&reg_vcc_3v3>;
+ vcc-pd-supply = <&reg_vcc_3v3>;
+ vcc-pe-supply = <&reg_vcc_3v3>;
+ vcc-pf-supply = <&reg_vcc_3v3>;
+ vcc-pg-supply = <&reg_vcc_3v3>;
+};
diff --git a/dts/dtspp/sun20i-d1-mangopi-mq-pro.dts b/dts/dtspp/sun20i-d1-mangopi-mq-pro.dts
new file mode 100644
index 0000000..986758b
--- /dev/null
+++ b/dts/dtspp/sun20i-d1-mangopi-mq-pro.dts
@@ -0,0 +1,1315 @@
+# 0 "sun20i-d1-mangopi-mq-pro.dts"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "sun20i-d1-mangopi-mq-pro.dts"
+
+
+
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/gpio/gpio.h" 1
+# 5 "sun20i-d1-mangopi-mq-pro.dts" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/leds/common.h" 1
+# 6 "sun20i-d1-mangopi-mq-pro.dts" 2
+
+/dts-v1/;
+
+# 1 "sun20i-d1.dtsi" 1
+
+
+
+# 1 "sun20i-d1s.dtsi" 1
+
+
+
+
+
+# 1 "sunxi-d1s-t113.dtsi" 1
+
+
+
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun6i-rtc.h" 1
+# 5 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-de2.h" 1
+# 6 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-tcon-top.h" 1
+# 7 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-ccu.h" 1
+# 8 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-r-ccu.h" 1
+# 9 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/interrupt-controller/irq.h" 1
+# 10 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun8i-de2.h" 1
+# 11 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-ccu.h" 1
+# 12 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-r-ccu.h" 1
+# 13 "sunxi-d1s-t113.dtsi" 2
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dcxo: dcxo-clk {
+  compatible = "fixed-clock";
+  clock-output-names = "dcxo";
+  #clock-cells = <0>;
+ };
+
+ de: display-engine {
+  compatible = "allwinner,sun20i-d1-display-engine";
+  allwinner,pipelines = <&mixer0>, <&mixer1>;
+  status = "disabled";
+ };
+
+ soc {
+  compatible = "simple-bus";
+  ranges;
+  dma-noncoherent;
+  #address-cells = <1>;
+  #size-cells = <1>;
+
+  pio: pinctrl@2000000 {
+   compatible = "allwinner,sun20i-d1-pinctrl";
+   reg = <0x2000000 0x800>;
+   interrupts = <(69 + 16) 4>,
+         <(71 + 16) 4>,
+         <(73 + 16) 4>,
+         <(75 + 16) 4>,
+         <(77 + 16) 4>,
+         <(79 + 16) 4>;
+   clocks = <&ccu 24>,
+     <&dcxo>,
+     <&rtc 0>;
+   clock-names = "apb", "hosc", "losc";
+   gpio-controller;
+   interrupt-controller;
+   #gpio-cells = <3>;
+   #interrupt-cells = <3>;
+
+   /omit-if-no-ref/
+   can0_pins: can0-pins {
+    pins = "PB2", "PB3";
+    function = "can0";
+   };
+
+   /omit-if-no-ref/
+   can1_pins: can1-pins {
+    pins = "PB4", "PB5";
+    function = "can1";
+   };
+
+   /omit-if-no-ref/
+   clk_pg11_pin: clk-pg11-pin {
+    pins = "PG11";
+    function = "clk";
+   };
+
+   /omit-if-no-ref/
+   dsi_4lane_pins: dsi-4lane-pins {
+    pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+           "PD6", "PD7", "PD8", "PD9";
+    drive-strength = <30>;
+    function = "dsi";
+   };
+
+   /omit-if-no-ref/
+   lcd_rgb666_pins: lcd-rgb666-pins {
+    pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+           "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
+           "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
+           "PD18", "PD19", "PD20", "PD21";
+    function = "lcd0";
+   };
+
+   /omit-if-no-ref/
+   mmc0_pins: mmc0-pins {
+    pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+    function = "mmc0";
+   };
+
+   /omit-if-no-ref/
+   mmc1_pins: mmc1-pins {
+    pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+    function = "mmc1";
+   };
+
+   /omit-if-no-ref/
+   mmc2_pins: mmc2-pins {
+    pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
+    function = "mmc2";
+   };
+
+   /omit-if-no-ref/
+   rgmii_pe_pins: rgmii-pe-pins {
+    pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+           "PE5", "PE6", "PE7", "PE8", "PE9",
+           "PE11", "PE12", "PE13", "PE14", "PE15";
+    function = "emac";
+   };
+
+   /omit-if-no-ref/
+   rmii_pe_pins: rmii-pe-pins {
+    pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+           "PE5", "PE6", "PE7", "PE8", "PE9";
+    function = "emac";
+   };
+
+   /omit-if-no-ref/
+   spi0_pins: spi0-pins {
+    pins = "PC2", "PC3", "PC4", "PC5";
+    function = "spi0";
+   };
+
+   /omit-if-no-ref/
+   uart1_pg6_pins: uart1-pg6-pins {
+    pins = "PG6", "PG7";
+    function = "uart1";
+   };
+
+   /omit-if-no-ref/
+   uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
+    pins = "PG8", "PG9";
+    function = "uart1";
+   };
+
+   /omit-if-no-ref/
+   uart3_pb_pins: uart3-pb-pins {
+    pins = "PB6", "PB7";
+    function = "uart3";
+   };
+  };
+
+  ccu: clock-controller@2001000 {
+   compatible = "allwinner,sun20i-d1-ccu";
+   reg = <0x2001000 0x1000>;
+   clocks = <&dcxo>,
+     <&rtc 0>,
+     <&rtc 2>;
+   clock-names = "hosc", "losc", "iosc";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  gpadc: adc@2009000 {
+   compatible = "allwinner,sun20i-d1-gpadc";
+   reg = <0x2009000 0x400>;
+   clocks = <&ccu 80>;
+   resets = <&ccu 32>;
+   interrupts = <(57 + 16) 4>;
+   status = "disabled";
+   #io-channel-cells = <1>;
+  };
+
+  dmic: dmic@2031000 {
+   compatible = "allwinner,sun20i-d1-dmic",
+         "allwinner,sun50i-h6-dmic";
+   reg = <0x2031000 0x400>;
+   interrupts = <(24 + 16) 4>;
+   clocks = <&ccu 93>,
+     <&ccu 92>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 38>;
+   dmas = <&dma 8>;
+   dma-names = "rx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  i2s1: i2s@2033000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2033000 0x1000>;
+   interrupts = <(27 + 16) 4>;
+   clocks = <&ccu 87>,
+     <&ccu 83>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 35>;
+   dmas = <&dma 4>, <&dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  i2s2: i2s@2034000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2034000 0x1000>;
+   interrupts = <(28 + 16) 4>;
+   clocks = <&ccu 88>,
+     <&ccu 84>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 36>;
+   dmas = <&dma 5>, <&dma 5>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  timer: timer@2050000 {
+   compatible = "allwinner,sun20i-d1-timer",
+         "allwinner,sun8i-a23-timer";
+   reg = <0x2050000 0xa0>;
+   interrupts = <(59 + 16) 4>,
+         <(60 + 16) 4>;
+   clocks = <&dcxo>;
+  };
+
+  wdt: watchdog@20500a0 {
+   compatible = "allwinner,sun20i-d1-wdt-reset",
+         "allwinner,sun20i-d1-wdt";
+   reg = <0x20500a0 0x20>;
+   interrupts = <(63 + 16) 4>;
+   clocks = <&dcxo>, <&rtc 0>;
+   clock-names = "hosc", "losc";
+   status = "reserved";
+  };
+
+  uart0: serial@2500000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500000 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(2 + 16) 4>;
+   clocks = <&ccu 62>;
+   resets = <&ccu 18>;
+   dmas = <&dma 14>, <&dma 14>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart1: serial@2500400 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500400 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(3 + 16) 4>;
+   clocks = <&ccu 63>;
+   resets = <&ccu 19>;
+   dmas = <&dma 15>, <&dma 15>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart2: serial@2500800 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500800 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(4 + 16) 4>;
+   clocks = <&ccu 64>;
+   resets = <&ccu 20>;
+   dmas = <&dma 16>, <&dma 16>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart3: serial@2500c00 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500c00 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(5 + 16) 4>;
+   clocks = <&ccu 65>;
+   resets = <&ccu 21>;
+   dmas = <&dma 17>, <&dma 17>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart4: serial@2501000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2501000 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(6 + 16) 4>;
+   clocks = <&ccu 66>;
+   resets = <&ccu 22>;
+   dmas = <&dma 18>, <&dma 18>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart5: serial@2501400 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2501400 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(7 + 16) 4>;
+   clocks = <&ccu 67>;
+   resets = <&ccu 23>;
+   dmas = <&dma 19>, <&dma 19>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  i2c0: i2c@2502000 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502000 0x400>;
+   interrupts = <(9 + 16) 4>;
+   clocks = <&ccu 68>;
+   resets = <&ccu 24>;
+   dmas = <&dma 43>, <&dma 43>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c1: i2c@2502400 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502400 0x400>;
+   interrupts = <(10 + 16) 4>;
+   clocks = <&ccu 69>;
+   resets = <&ccu 25>;
+   dmas = <&dma 44>, <&dma 44>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c2: i2c@2502800 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502800 0x400>;
+   interrupts = <(11 + 16) 4>;
+   clocks = <&ccu 70>;
+   resets = <&ccu 26>;
+   dmas = <&dma 45>, <&dma 45>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c3: i2c@2502c00 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502c00 0x400>;
+   interrupts = <(12 + 16) 4>;
+   clocks = <&ccu 71>;
+   resets = <&ccu 27>;
+   dmas = <&dma 46>, <&dma 46>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  can0: can@2504000 {
+   compatible = "allwinner,sun20i-d1-can";
+   reg = <0x02504000 0x400>;
+   interrupts = <(21 + 16) 4>;
+   clocks = <&ccu 145>;
+   resets = <&ccu 66>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&can0_pins>;
+   status = "disabled";
+  };
+
+  can1: can@2504400 {
+   compatible = "allwinner,sun20i-d1-can";
+   reg = <0x02504400 0x400>;
+   interrupts = <(22 + 16) 4>;
+   clocks = <&ccu 146>;
+   resets = <&ccu 67>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&can1_pins>;
+   status = "disabled";
+  };
+
+  syscon: syscon@3000000 {
+   compatible = "allwinner,sun20i-d1-system-control";
+   reg = <0x3000000 0x1000>;
+   ranges;
+   #address-cells = <1>;
+   #size-cells = <1>;
+  };
+
+  dma: dma-controller@3002000 {
+   compatible = "allwinner,sun20i-d1-dma";
+   reg = <0x3002000 0x1000>;
+   interrupts = <(50 + 16) 4>;
+   clocks = <&ccu 37>, <&ccu 48>;
+   clock-names = "bus", "mbus";
+   resets = <&ccu 6>;
+   dma-channels = <16>;
+   dma-requests = <48>;
+   #dma-cells = <1>;
+  };
+
+  sid: efuse@3006000 {
+   compatible = "allwinner,sun20i-d1-sid";
+   reg = <0x3006000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+  };
+
+  crypto: crypto@3040000 {
+   compatible = "allwinner,sun20i-d1-crypto";
+   reg = <0x3040000 0x800>;
+   interrupts = <(52 + 16) 4>;
+   clocks = <&ccu 34>,
+     <&ccu 33>,
+     <&ccu 50>,
+     <&rtc 2>;
+   clock-names = "bus", "mod", "ram", "trng";
+   resets = <&ccu 4>;
+  };
+
+  mbus: dram-controller@3102000 {
+   compatible = "allwinner,sun20i-d1-mbus";
+   reg = <0x3102000 0x1000>,
+         <0x3103000 0x1000>;
+   reg-names = "mbus", "dram";
+   interrupts = <(43 + 16) 4>;
+   clocks = <&ccu 26>,
+     <&ccu 47>,
+     <&ccu 55>;
+   clock-names = "mbus", "dram", "bus";
+   dma-ranges = <0 0x40000000 0x80000000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   #interconnect-cells = <1>;
+  };
+
+  mmc0: mmc@4020000 {
+   compatible = "allwinner,sun20i-d1-mmc";
+   reg = <0x4020000 0x1000>;
+   interrupts = <(40 + 16) 4>;
+   clocks = <&ccu 59>, <&ccu 56>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 15>;
+   reset-names = "ahb";
+   cap-sd-highspeed;
+   max-frequency = <150000000>;
+   no-mmc;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  mmc1: mmc@4021000 {
+   compatible = "allwinner,sun20i-d1-mmc";
+   reg = <0x4021000 0x1000>;
+   interrupts = <(41 + 16) 4>;
+   clocks = <&ccu 60>, <&ccu 57>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 16>;
+   reset-names = "ahb";
+   cap-sd-highspeed;
+   max-frequency = <150000000>;
+   no-mmc;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  mmc2: mmc@4022000 {
+   compatible = "allwinner,sun20i-d1-emmc",
+         "allwinner,sun50i-a100-emmc";
+   reg = <0x4022000 0x1000>;
+   interrupts = <(42 + 16) 4>;
+   clocks = <&ccu 61>, <&ccu 58>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 17>;
+   reset-names = "ahb";
+   cap-mmc-highspeed;
+   max-frequency = <150000000>;
+   mmc-ddr-1_8v;
+   mmc-ddr-3_3v;
+   no-sd;
+   no-sdio;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  spi0: spi@4025000 {
+   compatible = "allwinner,sun20i-d1-spi",
+         "allwinner,sun50i-r329-spi";
+   reg = <0x04025000 0x1000>;
+   interrupts = <(15 + 16) 4>;
+   clocks = <&ccu 74>, <&ccu 72>;
+   clock-names = "ahb", "mod";
+   dmas = <&dma 22>, <&dma 22>;
+   dma-names = "rx", "tx";
+   resets = <&ccu 28>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  spi1: spi@4026000 {
+   compatible = "allwinner,sun20i-d1-spi-dbi",
+         "allwinner,sun50i-r329-spi-dbi",
+         "allwinner,sun50i-r329-spi";
+   reg = <0x04026000 0x1000>;
+   interrupts = <(16 + 16) 4>;
+   clocks = <&ccu 75>, <&ccu 73>;
+   clock-names = "ahb", "mod";
+   dmas = <&dma 23>, <&dma 23>;
+   dma-names = "rx", "tx";
+   resets = <&ccu 29>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  usb_otg: usb@4100000 {
+   compatible = "allwinner,sun20i-d1-musb",
+         "allwinner,sun8i-a33-musb";
+   reg = <0x4100000 0x400>;
+   interrupts = <(29 + 16) 4>;
+   interrupt-names = "mc";
+   clocks = <&ccu 103>;
+   resets = <&ccu 46>;
+   extcon = <&usbphy 0>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  usbphy: phy@4100400 {
+   compatible = "allwinner,sun20i-d1-usb-phy";
+   reg = <0x4100400 0x100>,
+         <0x4101800 0x100>,
+         <0x4200800 0x100>;
+   reg-names = "phy_ctrl",
+        "pmu0",
+        "pmu1";
+   clocks = <&dcxo>,
+     <&dcxo>;
+   clock-names = "usb0_phy",
+          "usb1_phy";
+   resets = <&ccu 40>,
+     <&ccu 41>;
+   reset-names = "usb0_reset",
+          "usb1_reset";
+   status = "disabled";
+   #phy-cells = <1>;
+  };
+
+  ehci0: usb@4101000 {
+   compatible = "allwinner,sun20i-d1-ehci",
+         "generic-ehci";
+   reg = <0x4101000 0x100>;
+   interrupts = <(30 + 16) 4>;
+   clocks = <&ccu 99>,
+     <&ccu 101>,
+     <&ccu 97>;
+   resets = <&ccu 42>,
+     <&ccu 44>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ohci0: usb@4101400 {
+   compatible = "allwinner,sun20i-d1-ohci",
+         "generic-ohci";
+   reg = <0x4101400 0x100>;
+   interrupts = <(31 + 16) 4>;
+   clocks = <&ccu 99>,
+     <&ccu 97>;
+   resets = <&ccu 42>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ehci1: usb@4200000 {
+   compatible = "allwinner,sun20i-d1-ehci",
+         "generic-ehci";
+   reg = <0x4200000 0x100>;
+   interrupts = <(33 + 16) 4>;
+   clocks = <&ccu 100>,
+     <&ccu 102>,
+     <&ccu 98>;
+   resets = <&ccu 43>,
+     <&ccu 45>;
+   phys = <&usbphy 1>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ohci1: usb@4200400 {
+   compatible = "allwinner,sun20i-d1-ohci",
+         "generic-ohci";
+   reg = <0x4200400 0x100>;
+   interrupts = <(34 + 16) 4>;
+   clocks = <&ccu 100>,
+     <&ccu 98>;
+   resets = <&ccu 43>;
+   phys = <&usbphy 1>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  emac: ethernet@4500000 {
+   compatible = "allwinner,sun20i-d1-emac",
+         "allwinner,sun50i-a64-emac";
+   reg = <0x4500000 0x10000>;
+   interrupts = <(46 + 16) 4>;
+   interrupt-names = "macirq";
+   clocks = <&ccu 77>;
+   clock-names = "stmmaceth";
+   resets = <&ccu 30>;
+   reset-names = "stmmaceth";
+   syscon = <&syscon>;
+   status = "disabled";
+
+   mdio: mdio {
+    compatible = "snps,dwmac-mdio";
+    #address-cells = <1>;
+    #size-cells = <0>;
+   };
+  };
+
+  display_clocks: clock-controller@5000000 {
+   compatible = "allwinner,sun20i-d1-de2-clk",
+         "allwinner,sun50i-h5-de2-clk";
+   reg = <0x5000000 0x10000>;
+   clocks = <&ccu 28>, <&ccu 27>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 1>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  mixer0: mixer@5100000 {
+   compatible = "allwinner,sun20i-d1-de2-mixer-0";
+   reg = <0x5100000 0x100000>;
+   clocks = <&display_clocks 0>,
+     <&display_clocks 6>;
+   clock-names = "bus", "mod";
+   resets = <&display_clocks 0>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mixer0_out: port@1 {
+     reg = <1>;
+
+     mixer0_out_tcon_top_mixer0: endpoint {
+      remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+     };
+    };
+   };
+  };
+
+  mixer1: mixer@5200000 {
+   compatible = "allwinner,sun20i-d1-de2-mixer-1";
+   reg = <0x5200000 0x100000>;
+   clocks = <&display_clocks 1>,
+     <&display_clocks 7>;
+   clock-names = "bus", "mod";
+   resets = <&display_clocks 1>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mixer1_out: port@1 {
+     reg = <1>;
+
+     mixer1_out_tcon_top_mixer1: endpoint {
+      remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+     };
+    };
+   };
+  };
+
+  dsi: dsi@5450000 {
+   compatible = "allwinner,sun20i-d1-mipi-dsi",
+         "allwinner,sun50i-a100-mipi-dsi";
+   reg = <0x5450000 0x1000>;
+   interrupts = <(92 + 16) 4>;
+   clocks = <&ccu 111>,
+     <&tcon_top 2>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 51>;
+   phys = <&dphy>;
+   phy-names = "dphy";
+   status = "disabled";
+
+   port {
+    dsi_in_tcon_lcd0: endpoint {
+     remote-endpoint = <&tcon_lcd0_out_dsi>;
+    };
+   };
+  };
+
+  dphy: phy@5451000 {
+   compatible = "allwinner,sun20i-d1-mipi-dphy",
+         "allwinner,sun50i-a100-mipi-dphy";
+   reg = <0x5451000 0x1000>;
+   interrupts = <(92 + 16) 4>;
+   clocks = <&ccu 111>,
+     <&ccu 110>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 51>;
+   #phy-cells = <0>;
+  };
+
+  tcon_top: tcon-top@5460000 {
+   compatible = "allwinner,sun20i-d1-tcon-top";
+   reg = <0x5460000 0x1000>;
+   clocks = <&ccu 105>,
+     <&ccu 114>,
+     <&ccu 116>,
+     <&ccu 112>;
+   clock-names = "bus", "tcon-tv0", "tve0", "dsi";
+   clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
+   resets = <&ccu 48>;
+   #clock-cells = <1>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_top_mixer0_in: port@0 {
+     reg = <0>;
+
+     tcon_top_mixer0_in_mixer0: endpoint {
+      remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+     };
+    };
+
+    tcon_top_mixer0_out: port@1 {
+     reg = <1>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
+     };
+
+     tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+      reg = <2>;
+      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+     };
+    };
+
+    tcon_top_mixer1_in: port@2 {
+     reg = <2>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer1_in_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
+     };
+    };
+
+    tcon_top_mixer1_out: port@3 {
+     reg = <3>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
+     };
+
+     tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+      reg = <2>;
+      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+     };
+    };
+
+    tcon_top_hdmi_in: port@4 {
+     reg = <4>;
+
+     tcon_top_hdmi_in_tcon_tv0: endpoint {
+      remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
+     };
+    };
+
+    tcon_top_hdmi_out: port@5 {
+     reg = <5>;
+    };
+   };
+  };
+
+  tcon_lcd0: lcd-controller@5461000 {
+   compatible = "allwinner,sun20i-d1-tcon-lcd";
+   reg = <0x5461000 0x1000>;
+   interrupts = <(90 + 16) 4>;
+   clocks = <&ccu 113>,
+     <&ccu 112>;
+   clock-names = "ahb", "tcon-ch0";
+   clock-output-names = "tcon-pixel-clock";
+   resets = <&ccu 52>,
+     <&ccu 54>;
+   reset-names = "lcd", "lvds";
+   #clock-cells = <0>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_lcd0_in: port@0 {
+     reg = <0>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
+     };
+
+     tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
+     };
+    };
+
+    tcon_lcd0_out: port@1 {
+     reg = <1>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_lcd0_out_dsi: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&dsi_in_tcon_lcd0>;
+     };
+    };
+   };
+  };
+
+  tcon_tv0: lcd-controller@5470000 {
+   compatible = "allwinner,sun20i-d1-tcon-tv";
+   reg = <0x5470000 0x1000>;
+   interrupts = <(91 + 16) 4>;
+   clocks = <&ccu 115>,
+     <&tcon_top 0>;
+   clock-names = "ahb", "tcon-ch1";
+   resets = <&ccu 53>;
+   reset-names = "lcd";
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_tv0_in: port@0 {
+     reg = <0>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+     };
+
+     tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+     };
+    };
+
+    tcon_tv0_out: port@1 {
+     reg = <1>;
+
+     tcon_tv0_out_tcon_top_hdmi: endpoint {
+      remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+     };
+    };
+   };
+  };
+
+  ppu: power-controller@7001000 {
+   compatible = "allwinner,sun20i-d1-ppu";
+   reg = <0x7001000 0x1000>;
+   clocks = <&r_ccu 4>;
+   resets = <&r_ccu 2>;
+   #power-domain-cells = <1>;
+  };
+
+  r_ccu: clock-controller@7010000 {
+   compatible = "allwinner,sun20i-d1-r-ccu";
+   reg = <0x7010000 0x400>;
+   clocks = <&dcxo>,
+     <&rtc 0>,
+     <&rtc 2>,
+     <&ccu 6>;
+   clock-names = "hosc", "losc", "iosc", "pll-periph";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  rtc: rtc@7090000 {
+   compatible = "allwinner,sun20i-d1-rtc",
+         "allwinner,sun50i-r329-rtc";
+   reg = <0x7090000 0x400>;
+   interrupts = <(144 + 16) 4>;
+   clocks = <&r_ccu 7>,
+     <&dcxo>,
+     <&r_ccu 0>;
+   clock-names = "bus", "hosc", "ahb";
+   #clock-cells = <1>;
+  };
+ };
+};
+# 7 "sun20i-d1s.dtsi" 2
+
+/ {
+ cpus {
+  timebase-frequency = <24000000>;
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  cpu0: cpu@0 {
+   compatible = "thead,c906", "riscv";
+   device_type = "cpu";
+   reg = <0>;
+   clocks = <&ccu 132>;
+   d-cache-block-size = <64>;
+   d-cache-sets = <256>;
+   d-cache-size = <32768>;
+   i-cache-block-size = <64>;
+   i-cache-sets = <128>;
+   i-cache-size = <32768>;
+   mmu-type = "riscv,sv39";
+   operating-points-v2 = <&opp_table_cpu>;
+   riscv,isa = "rv64imafdc";
+   riscv,isa-base = "rv64i";
+   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+            "zifencei", "zihpm";
+   #cooling-cells = <2>;
+
+   cpu0_intc: interrupt-controller {
+    compatible = "riscv,cpu-intc";
+    interrupt-controller;
+    #interrupt-cells = <1>;
+   };
+  };
+ };
+
+ opp_table_cpu: opp-table-cpu {
+  compatible = "operating-points-v2";
+
+  opp-408000000 {
+   opp-hz = /bits/ 64 <408000000>;
+   opp-microvolt = <900000 900000 1100000>;
+  };
+
+  opp-1080000000 {
+   opp-hz = /bits/ 64 <1008000000>;
+   opp-microvolt = <900000 900000 1100000>;
+  };
+ };
+
+ soc {
+  interrupt-parent = <&plic>;
+
+  riscv_wdt: watchdog@6011000 {
+   compatible = "allwinner,sun20i-d1-wdt";
+   reg = <0x6011000 0x20>;
+   interrupts = <(131 + 16) 4>;
+   clocks = <&dcxo>, <&rtc 0>;
+   clock-names = "hosc", "losc";
+  };
+
+  plic: interrupt-controller@10000000 {
+   compatible = "allwinner,sun20i-d1-plic",
+         "thead,c900-plic";
+   reg = <0x10000000 0x4000000>;
+   interrupts-extended = <&cpu0_intc 11>,
+           <&cpu0_intc 9>;
+   interrupt-controller;
+   riscv,ndev = <175>;
+   #address-cells = <0>;
+   #interrupt-cells = <2>;
+  };
+ };
+
+ pmu {
+  compatible = "riscv,pmu";
+  riscv,event-to-mhpmcounters =
+   <0x00003 0x00003 0x00000008>,
+   <0x00004 0x00004 0x00000010>,
+   <0x00005 0x00005 0x00000200>,
+   <0x00006 0x00006 0x00000100>,
+   <0x10000 0x10000 0x00004000>,
+   <0x10001 0x10001 0x00008000>,
+   <0x10002 0x10002 0x00010000>,
+   <0x10003 0x10003 0x00020000>,
+   <0x10019 0x10019 0x00000040>,
+   <0x10021 0x10021 0x00000020>;
+  riscv,event-to-mhpmevent =
+   <0x00003 0x00000000 0x00000001>,
+   <0x00004 0x00000000 0x00000002>,
+   <0x00005 0x00000000 0x00000007>,
+   <0x00006 0x00000000 0x00000006>,
+   <0x10000 0x00000000 0x0000000c>,
+   <0x10001 0x00000000 0x0000000d>,
+   <0x10002 0x00000000 0x0000000e>,
+   <0x10003 0x00000000 0x0000000f>,
+   <0x10019 0x00000000 0x00000004>,
+   <0x10021 0x00000000 0x00000003>;
+  riscv,raw-event-to-mhpmcounters =
+   <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
+   <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
+   <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
+   <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
+   <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
+   <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
+   <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
+   <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
+   <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
+   <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
+   <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
+   <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
+ };
+};
+# 5 "sun20i-d1.dtsi" 2
+# 1 "sunxi-d1-t113.dtsi" 1
+
+
+
+/ {
+ soc {
+  dsp_wdt: watchdog@1700400 {
+   compatible = "allwinner,sun20i-d1-wdt";
+   reg = <0x1700400 0x20>;
+   interrupts = <(122 + 16) 4>;
+   clocks = <&dcxo>, <&rtc 0>;
+   clock-names = "hosc", "losc";
+   status = "reserved";
+  };
+ };
+};
+# 6 "sun20i-d1.dtsi" 2
+
+/ {
+ soc {
+  lradc: keys@2009800 {
+   compatible = "allwinner,sun20i-d1-lradc",
+         "allwinner,sun50i-r329-lradc";
+   reg = <0x2009800 0x400>;
+   interrupts = <(61 + 16) 4>;
+   clocks = <&ccu 104>;
+   resets = <&ccu 47>;
+   status = "disabled";
+  };
+
+  i2s0: i2s@2032000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2032000 0x1000>;
+   interrupts = <(26 + 16) 4>;
+   clocks = <&ccu 86>,
+     <&ccu 82>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 34>;
+   dmas = <&dma 3>, <&dma 3>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+ };
+};
+
+&pio {
+ /omit-if-no-ref/
+ dmic_pb11_d0_pin: dmic-pb11-d0-pin {
+  pins = "PB11";
+  function = "dmic";
+ };
+
+ /omit-if-no-ref/
+ dmic_pe17_clk_pin: dmic-pe17-clk-pin {
+  pins = "PE17";
+  function = "dmic";
+ };
+
+ /omit-if-no-ref/
+ i2c0_pb10_pins: i2c0-pb10-pins {
+  pins = "PB10", "PB11";
+  function = "i2c0";
+ };
+
+ /omit-if-no-ref/
+ i2c2_pb0_pins: i2c2-pb0-pins {
+  pins = "PB0", "PB1";
+  function = "i2c2";
+ };
+
+ /omit-if-no-ref/
+ uart0_pb8_pins: uart0-pb8-pins {
+  pins = "PB8", "PB9";
+  function = "uart0";
+ };
+};
+# 10 "sun20i-d1-mangopi-mq-pro.dts" 2
+# 1 "sun20i-common-regulators.dtsi" 1
+
+
+
+/ {
+ reg_vcc: vcc {
+  compatible = "regulator-fixed";
+  regulator-name = "vcc";
+  regulator-min-microvolt = <5000000>;
+  regulator-max-microvolt = <5000000>;
+ };
+
+ reg_vcc_3v3: vcc-3v3 {
+  compatible = "regulator-fixed";
+  regulator-name = "vcc-3v3";
+  regulator-min-microvolt = <3300000>;
+  regulator-max-microvolt = <3300000>;
+  vin-supply = <&reg_vcc>;
+ };
+};
+
+&pio {
+ vcc-pb-supply = <&reg_vcc_3v3>;
+ vcc-pc-supply = <&reg_vcc_3v3>;
+ vcc-pd-supply = <&reg_vcc_3v3>;
+ vcc-pe-supply = <&reg_vcc_3v3>;
+ vcc-pf-supply = <&reg_vcc_3v3>;
+ vcc-pg-supply = <&reg_vcc_3v3>;
+};
+# 11 "sun20i-d1-mangopi-mq-pro.dts" 2
+
+/ {
+ model = "MangoPi MQ Pro";
+ compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
+
+ aliases {
+  ethernet0 = &rtl8723ds;
+  serial0 = &uart0;
+ };
+
+ chosen {
+  stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+  compatible = "gpio-leds";
+
+  led-0 {
+   color = <3>;
+   function = "status";
+   gpios = <&pio 3 18 0>;
+  };
+ };
+
+ reg_avdd2v8: avdd2v8 {
+  compatible = "regulator-fixed";
+  regulator-name = "avdd2v8";
+  regulator-min-microvolt = <2800000>;
+  regulator-max-microvolt = <2800000>;
+  vin-supply = <&reg_vcc_3v3>;
+ };
+
+ reg_dvdd: dvdd {
+  compatible = "regulator-fixed";
+  regulator-name = "dvdd";
+  regulator-min-microvolt = <1200000>;
+  regulator-max-microvolt = <1200000>;
+  vin-supply = <&reg_vcc_3v3>;
+ };
+
+ reg_vdd_cpu: vdd-cpu {
+  compatible = "regulator-fixed";
+  regulator-name = "vdd-cpu";
+  regulator-min-microvolt = <1100000>;
+  regulator-max-microvolt = <1100000>;
+  vin-supply = <&reg_vcc>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+  compatible = "mmc-pwrseq-simple";
+  reset-gpios = <&pio 6 17 1>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 0>;
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ rtl8723ds: wifi@1 {
+  reg = <1>;
+  interrupt-parent = <&pio>;
+  interrupts = <6 10 8>;
+  interrupt-names = "host-wake";
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pe-supply = <&reg_avdd2v8>;
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+  compatible = "realtek,rtl8723ds-bt";
+  device-wake-gpios = <&pio 6 18 0>;
+  enable-gpios = <&pio 6 15 0>;
+  host-wake-gpios = <&pio 6 14 0>;
+ };
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc>;
+ status = "okay";
+};
diff --git a/dts/dtspp/sun20i-d1.dtsi b/dts/dtspp/sun20i-d1.dtsi
new file mode 100644
index 0000000..100ba48
--- /dev/null
+++ b/dts/dtspp/sun20i-d1.dtsi
@@ -0,0 +1,1141 @@
+# 0 "sun20i-d1.dtsi"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "sun20i-d1.dtsi"
+
+
+
+# 1 "sun20i-d1s.dtsi" 1
+
+
+
+
+
+# 1 "sunxi-d1s-t113.dtsi" 1
+
+
+
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun6i-rtc.h" 1
+# 5 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-de2.h" 1
+# 6 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-tcon-top.h" 1
+# 7 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-ccu.h" 1
+# 8 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-r-ccu.h" 1
+# 9 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/interrupt-controller/irq.h" 1
+# 10 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun8i-de2.h" 1
+# 11 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-ccu.h" 1
+# 12 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-r-ccu.h" 1
+# 13 "sunxi-d1s-t113.dtsi" 2
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dcxo: dcxo-clk {
+  compatible = "fixed-clock";
+  clock-output-names = "dcxo";
+  #clock-cells = <0>;
+ };
+
+ de: display-engine {
+  compatible = "allwinner,sun20i-d1-display-engine";
+  allwinner,pipelines = <&mixer0>, <&mixer1>;
+  status = "disabled";
+ };
+
+ soc {
+  compatible = "simple-bus";
+  ranges;
+  dma-noncoherent;
+  #address-cells = <1>;
+  #size-cells = <1>;
+
+  pio: pinctrl@2000000 {
+   compatible = "allwinner,sun20i-d1-pinctrl";
+   reg = <0x2000000 0x800>;
+   interrupts = <(69 + 16) 4>,
+         <(71 + 16) 4>,
+         <(73 + 16) 4>,
+         <(75 + 16) 4>,
+         <(77 + 16) 4>,
+         <(79 + 16) 4>;
+   clocks = <&ccu 24>,
+     <&dcxo>,
+     <&rtc 0>;
+   clock-names = "apb", "hosc", "losc";
+   gpio-controller;
+   interrupt-controller;
+   #gpio-cells = <3>;
+   #interrupt-cells = <3>;
+
+   /omit-if-no-ref/
+   can0_pins: can0-pins {
+    pins = "PB2", "PB3";
+    function = "can0";
+   };
+
+   /omit-if-no-ref/
+   can1_pins: can1-pins {
+    pins = "PB4", "PB5";
+    function = "can1";
+   };
+
+   /omit-if-no-ref/
+   clk_pg11_pin: clk-pg11-pin {
+    pins = "PG11";
+    function = "clk";
+   };
+
+   /omit-if-no-ref/
+   dsi_4lane_pins: dsi-4lane-pins {
+    pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+           "PD6", "PD7", "PD8", "PD9";
+    drive-strength = <30>;
+    function = "dsi";
+   };
+
+   /omit-if-no-ref/
+   lcd_rgb666_pins: lcd-rgb666-pins {
+    pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+           "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
+           "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
+           "PD18", "PD19", "PD20", "PD21";
+    function = "lcd0";
+   };
+
+   /omit-if-no-ref/
+   mmc0_pins: mmc0-pins {
+    pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+    function = "mmc0";
+   };
+
+   /omit-if-no-ref/
+   mmc1_pins: mmc1-pins {
+    pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+    function = "mmc1";
+   };
+
+   /omit-if-no-ref/
+   mmc2_pins: mmc2-pins {
+    pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
+    function = "mmc2";
+   };
+
+   /omit-if-no-ref/
+   rgmii_pe_pins: rgmii-pe-pins {
+    pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+           "PE5", "PE6", "PE7", "PE8", "PE9",
+           "PE11", "PE12", "PE13", "PE14", "PE15";
+    function = "emac";
+   };
+
+   /omit-if-no-ref/
+   rmii_pe_pins: rmii-pe-pins {
+    pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+           "PE5", "PE6", "PE7", "PE8", "PE9";
+    function = "emac";
+   };
+
+   /omit-if-no-ref/
+   spi0_pins: spi0-pins {
+    pins = "PC2", "PC3", "PC4", "PC5";
+    function = "spi0";
+   };
+
+   /omit-if-no-ref/
+   uart1_pg6_pins: uart1-pg6-pins {
+    pins = "PG6", "PG7";
+    function = "uart1";
+   };
+
+   /omit-if-no-ref/
+   uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
+    pins = "PG8", "PG9";
+    function = "uart1";
+   };
+
+   /omit-if-no-ref/
+   uart3_pb_pins: uart3-pb-pins {
+    pins = "PB6", "PB7";
+    function = "uart3";
+   };
+  };
+
+  ccu: clock-controller@2001000 {
+   compatible = "allwinner,sun20i-d1-ccu";
+   reg = <0x2001000 0x1000>;
+   clocks = <&dcxo>,
+     <&rtc 0>,
+     <&rtc 2>;
+   clock-names = "hosc", "losc", "iosc";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  gpadc: adc@2009000 {
+   compatible = "allwinner,sun20i-d1-gpadc";
+   reg = <0x2009000 0x400>;
+   clocks = <&ccu 80>;
+   resets = <&ccu 32>;
+   interrupts = <(57 + 16) 4>;
+   status = "disabled";
+   #io-channel-cells = <1>;
+  };
+
+  dmic: dmic@2031000 {
+   compatible = "allwinner,sun20i-d1-dmic",
+         "allwinner,sun50i-h6-dmic";
+   reg = <0x2031000 0x400>;
+   interrupts = <(24 + 16) 4>;
+   clocks = <&ccu 93>,
+     <&ccu 92>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 38>;
+   dmas = <&dma 8>;
+   dma-names = "rx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  i2s1: i2s@2033000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2033000 0x1000>;
+   interrupts = <(27 + 16) 4>;
+   clocks = <&ccu 87>,
+     <&ccu 83>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 35>;
+   dmas = <&dma 4>, <&dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  i2s2: i2s@2034000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2034000 0x1000>;
+   interrupts = <(28 + 16) 4>;
+   clocks = <&ccu 88>,
+     <&ccu 84>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 36>;
+   dmas = <&dma 5>, <&dma 5>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  timer: timer@2050000 {
+   compatible = "allwinner,sun20i-d1-timer",
+         "allwinner,sun8i-a23-timer";
+   reg = <0x2050000 0xa0>;
+   interrupts = <(59 + 16) 4>,
+         <(60 + 16) 4>;
+   clocks = <&dcxo>;
+  };
+
+  wdt: watchdog@20500a0 {
+   compatible = "allwinner,sun20i-d1-wdt-reset",
+         "allwinner,sun20i-d1-wdt";
+   reg = <0x20500a0 0x20>;
+   interrupts = <(63 + 16) 4>;
+   clocks = <&dcxo>, <&rtc 0>;
+   clock-names = "hosc", "losc";
+   status = "reserved";
+  };
+
+  uart0: serial@2500000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500000 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(2 + 16) 4>;
+   clocks = <&ccu 62>;
+   resets = <&ccu 18>;
+   dmas = <&dma 14>, <&dma 14>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart1: serial@2500400 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500400 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(3 + 16) 4>;
+   clocks = <&ccu 63>;
+   resets = <&ccu 19>;
+   dmas = <&dma 15>, <&dma 15>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart2: serial@2500800 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500800 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(4 + 16) 4>;
+   clocks = <&ccu 64>;
+   resets = <&ccu 20>;
+   dmas = <&dma 16>, <&dma 16>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart3: serial@2500c00 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500c00 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(5 + 16) 4>;
+   clocks = <&ccu 65>;
+   resets = <&ccu 21>;
+   dmas = <&dma 17>, <&dma 17>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart4: serial@2501000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2501000 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(6 + 16) 4>;
+   clocks = <&ccu 66>;
+   resets = <&ccu 22>;
+   dmas = <&dma 18>, <&dma 18>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart5: serial@2501400 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2501400 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(7 + 16) 4>;
+   clocks = <&ccu 67>;
+   resets = <&ccu 23>;
+   dmas = <&dma 19>, <&dma 19>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  i2c0: i2c@2502000 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502000 0x400>;
+   interrupts = <(9 + 16) 4>;
+   clocks = <&ccu 68>;
+   resets = <&ccu 24>;
+   dmas = <&dma 43>, <&dma 43>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c1: i2c@2502400 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502400 0x400>;
+   interrupts = <(10 + 16) 4>;
+   clocks = <&ccu 69>;
+   resets = <&ccu 25>;
+   dmas = <&dma 44>, <&dma 44>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c2: i2c@2502800 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502800 0x400>;
+   interrupts = <(11 + 16) 4>;
+   clocks = <&ccu 70>;
+   resets = <&ccu 26>;
+   dmas = <&dma 45>, <&dma 45>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c3: i2c@2502c00 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502c00 0x400>;
+   interrupts = <(12 + 16) 4>;
+   clocks = <&ccu 71>;
+   resets = <&ccu 27>;
+   dmas = <&dma 46>, <&dma 46>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  can0: can@2504000 {
+   compatible = "allwinner,sun20i-d1-can";
+   reg = <0x02504000 0x400>;
+   interrupts = <(21 + 16) 4>;
+   clocks = <&ccu 145>;
+   resets = <&ccu 66>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&can0_pins>;
+   status = "disabled";
+  };
+
+  can1: can@2504400 {
+   compatible = "allwinner,sun20i-d1-can";
+   reg = <0x02504400 0x400>;
+   interrupts = <(22 + 16) 4>;
+   clocks = <&ccu 146>;
+   resets = <&ccu 67>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&can1_pins>;
+   status = "disabled";
+  };
+
+  syscon: syscon@3000000 {
+   compatible = "allwinner,sun20i-d1-system-control";
+   reg = <0x3000000 0x1000>;
+   ranges;
+   #address-cells = <1>;
+   #size-cells = <1>;
+  };
+
+  dma: dma-controller@3002000 {
+   compatible = "allwinner,sun20i-d1-dma";
+   reg = <0x3002000 0x1000>;
+   interrupts = <(50 + 16) 4>;
+   clocks = <&ccu 37>, <&ccu 48>;
+   clock-names = "bus", "mbus";
+   resets = <&ccu 6>;
+   dma-channels = <16>;
+   dma-requests = <48>;
+   #dma-cells = <1>;
+  };
+
+  sid: efuse@3006000 {
+   compatible = "allwinner,sun20i-d1-sid";
+   reg = <0x3006000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+  };
+
+  crypto: crypto@3040000 {
+   compatible = "allwinner,sun20i-d1-crypto";
+   reg = <0x3040000 0x800>;
+   interrupts = <(52 + 16) 4>;
+   clocks = <&ccu 34>,
+     <&ccu 33>,
+     <&ccu 50>,
+     <&rtc 2>;
+   clock-names = "bus", "mod", "ram", "trng";
+   resets = <&ccu 4>;
+  };
+
+  mbus: dram-controller@3102000 {
+   compatible = "allwinner,sun20i-d1-mbus";
+   reg = <0x3102000 0x1000>,
+         <0x3103000 0x1000>;
+   reg-names = "mbus", "dram";
+   interrupts = <(43 + 16) 4>;
+   clocks = <&ccu 26>,
+     <&ccu 47>,
+     <&ccu 55>;
+   clock-names = "mbus", "dram", "bus";
+   dma-ranges = <0 0x40000000 0x80000000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   #interconnect-cells = <1>;
+  };
+
+  mmc0: mmc@4020000 {
+   compatible = "allwinner,sun20i-d1-mmc";
+   reg = <0x4020000 0x1000>;
+   interrupts = <(40 + 16) 4>;
+   clocks = <&ccu 59>, <&ccu 56>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 15>;
+   reset-names = "ahb";
+   cap-sd-highspeed;
+   max-frequency = <150000000>;
+   no-mmc;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  mmc1: mmc@4021000 {
+   compatible = "allwinner,sun20i-d1-mmc";
+   reg = <0x4021000 0x1000>;
+   interrupts = <(41 + 16) 4>;
+   clocks = <&ccu 60>, <&ccu 57>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 16>;
+   reset-names = "ahb";
+   cap-sd-highspeed;
+   max-frequency = <150000000>;
+   no-mmc;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  mmc2: mmc@4022000 {
+   compatible = "allwinner,sun20i-d1-emmc",
+         "allwinner,sun50i-a100-emmc";
+   reg = <0x4022000 0x1000>;
+   interrupts = <(42 + 16) 4>;
+   clocks = <&ccu 61>, <&ccu 58>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 17>;
+   reset-names = "ahb";
+   cap-mmc-highspeed;
+   max-frequency = <150000000>;
+   mmc-ddr-1_8v;
+   mmc-ddr-3_3v;
+   no-sd;
+   no-sdio;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  spi0: spi@4025000 {
+   compatible = "allwinner,sun20i-d1-spi",
+         "allwinner,sun50i-r329-spi";
+   reg = <0x04025000 0x1000>;
+   interrupts = <(15 + 16) 4>;
+   clocks = <&ccu 74>, <&ccu 72>;
+   clock-names = "ahb", "mod";
+   dmas = <&dma 22>, <&dma 22>;
+   dma-names = "rx", "tx";
+   resets = <&ccu 28>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  spi1: spi@4026000 {
+   compatible = "allwinner,sun20i-d1-spi-dbi",
+         "allwinner,sun50i-r329-spi-dbi",
+         "allwinner,sun50i-r329-spi";
+   reg = <0x04026000 0x1000>;
+   interrupts = <(16 + 16) 4>;
+   clocks = <&ccu 75>, <&ccu 73>;
+   clock-names = "ahb", "mod";
+   dmas = <&dma 23>, <&dma 23>;
+   dma-names = "rx", "tx";
+   resets = <&ccu 29>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  usb_otg: usb@4100000 {
+   compatible = "allwinner,sun20i-d1-musb",
+         "allwinner,sun8i-a33-musb";
+   reg = <0x4100000 0x400>;
+   interrupts = <(29 + 16) 4>;
+   interrupt-names = "mc";
+   clocks = <&ccu 103>;
+   resets = <&ccu 46>;
+   extcon = <&usbphy 0>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  usbphy: phy@4100400 {
+   compatible = "allwinner,sun20i-d1-usb-phy";
+   reg = <0x4100400 0x100>,
+         <0x4101800 0x100>,
+         <0x4200800 0x100>;
+   reg-names = "phy_ctrl",
+        "pmu0",
+        "pmu1";
+   clocks = <&dcxo>,
+     <&dcxo>;
+   clock-names = "usb0_phy",
+          "usb1_phy";
+   resets = <&ccu 40>,
+     <&ccu 41>;
+   reset-names = "usb0_reset",
+          "usb1_reset";
+   status = "disabled";
+   #phy-cells = <1>;
+  };
+
+  ehci0: usb@4101000 {
+   compatible = "allwinner,sun20i-d1-ehci",
+         "generic-ehci";
+   reg = <0x4101000 0x100>;
+   interrupts = <(30 + 16) 4>;
+   clocks = <&ccu 99>,
+     <&ccu 101>,
+     <&ccu 97>;
+   resets = <&ccu 42>,
+     <&ccu 44>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ohci0: usb@4101400 {
+   compatible = "allwinner,sun20i-d1-ohci",
+         "generic-ohci";
+   reg = <0x4101400 0x100>;
+   interrupts = <(31 + 16) 4>;
+   clocks = <&ccu 99>,
+     <&ccu 97>;
+   resets = <&ccu 42>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ehci1: usb@4200000 {
+   compatible = "allwinner,sun20i-d1-ehci",
+         "generic-ehci";
+   reg = <0x4200000 0x100>;
+   interrupts = <(33 + 16) 4>;
+   clocks = <&ccu 100>,
+     <&ccu 102>,
+     <&ccu 98>;
+   resets = <&ccu 43>,
+     <&ccu 45>;
+   phys = <&usbphy 1>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ohci1: usb@4200400 {
+   compatible = "allwinner,sun20i-d1-ohci",
+         "generic-ohci";
+   reg = <0x4200400 0x100>;
+   interrupts = <(34 + 16) 4>;
+   clocks = <&ccu 100>,
+     <&ccu 98>;
+   resets = <&ccu 43>;
+   phys = <&usbphy 1>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  emac: ethernet@4500000 {
+   compatible = "allwinner,sun20i-d1-emac",
+         "allwinner,sun50i-a64-emac";
+   reg = <0x4500000 0x10000>;
+   interrupts = <(46 + 16) 4>;
+   interrupt-names = "macirq";
+   clocks = <&ccu 77>;
+   clock-names = "stmmaceth";
+   resets = <&ccu 30>;
+   reset-names = "stmmaceth";
+   syscon = <&syscon>;
+   status = "disabled";
+
+   mdio: mdio {
+    compatible = "snps,dwmac-mdio";
+    #address-cells = <1>;
+    #size-cells = <0>;
+   };
+  };
+
+  display_clocks: clock-controller@5000000 {
+   compatible = "allwinner,sun20i-d1-de2-clk",
+         "allwinner,sun50i-h5-de2-clk";
+   reg = <0x5000000 0x10000>;
+   clocks = <&ccu 28>, <&ccu 27>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 1>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  mixer0: mixer@5100000 {
+   compatible = "allwinner,sun20i-d1-de2-mixer-0";
+   reg = <0x5100000 0x100000>;
+   clocks = <&display_clocks 0>,
+     <&display_clocks 6>;
+   clock-names = "bus", "mod";
+   resets = <&display_clocks 0>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mixer0_out: port@1 {
+     reg = <1>;
+
+     mixer0_out_tcon_top_mixer0: endpoint {
+      remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+     };
+    };
+   };
+  };
+
+  mixer1: mixer@5200000 {
+   compatible = "allwinner,sun20i-d1-de2-mixer-1";
+   reg = <0x5200000 0x100000>;
+   clocks = <&display_clocks 1>,
+     <&display_clocks 7>;
+   clock-names = "bus", "mod";
+   resets = <&display_clocks 1>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mixer1_out: port@1 {
+     reg = <1>;
+
+     mixer1_out_tcon_top_mixer1: endpoint {
+      remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+     };
+    };
+   };
+  };
+
+  dsi: dsi@5450000 {
+   compatible = "allwinner,sun20i-d1-mipi-dsi",
+         "allwinner,sun50i-a100-mipi-dsi";
+   reg = <0x5450000 0x1000>;
+   interrupts = <(92 + 16) 4>;
+   clocks = <&ccu 111>,
+     <&tcon_top 2>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 51>;
+   phys = <&dphy>;
+   phy-names = "dphy";
+   status = "disabled";
+
+   port {
+    dsi_in_tcon_lcd0: endpoint {
+     remote-endpoint = <&tcon_lcd0_out_dsi>;
+    };
+   };
+  };
+
+  dphy: phy@5451000 {
+   compatible = "allwinner,sun20i-d1-mipi-dphy",
+         "allwinner,sun50i-a100-mipi-dphy";
+   reg = <0x5451000 0x1000>;
+   interrupts = <(92 + 16) 4>;
+   clocks = <&ccu 111>,
+     <&ccu 110>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 51>;
+   #phy-cells = <0>;
+  };
+
+  tcon_top: tcon-top@5460000 {
+   compatible = "allwinner,sun20i-d1-tcon-top";
+   reg = <0x5460000 0x1000>;
+   clocks = <&ccu 105>,
+     <&ccu 114>,
+     <&ccu 116>,
+     <&ccu 112>;
+   clock-names = "bus", "tcon-tv0", "tve0", "dsi";
+   clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
+   resets = <&ccu 48>;
+   #clock-cells = <1>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_top_mixer0_in: port@0 {
+     reg = <0>;
+
+     tcon_top_mixer0_in_mixer0: endpoint {
+      remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+     };
+    };
+
+    tcon_top_mixer0_out: port@1 {
+     reg = <1>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
+     };
+
+     tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+      reg = <2>;
+      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+     };
+    };
+
+    tcon_top_mixer1_in: port@2 {
+     reg = <2>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer1_in_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
+     };
+    };
+
+    tcon_top_mixer1_out: port@3 {
+     reg = <3>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
+     };
+
+     tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+      reg = <2>;
+      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+     };
+    };
+
+    tcon_top_hdmi_in: port@4 {
+     reg = <4>;
+
+     tcon_top_hdmi_in_tcon_tv0: endpoint {
+      remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
+     };
+    };
+
+    tcon_top_hdmi_out: port@5 {
+     reg = <5>;
+    };
+   };
+  };
+
+  tcon_lcd0: lcd-controller@5461000 {
+   compatible = "allwinner,sun20i-d1-tcon-lcd";
+   reg = <0x5461000 0x1000>;
+   interrupts = <(90 + 16) 4>;
+   clocks = <&ccu 113>,
+     <&ccu 112>;
+   clock-names = "ahb", "tcon-ch0";
+   clock-output-names = "tcon-pixel-clock";
+   resets = <&ccu 52>,
+     <&ccu 54>;
+   reset-names = "lcd", "lvds";
+   #clock-cells = <0>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_lcd0_in: port@0 {
+     reg = <0>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
+     };
+
+     tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
+     };
+    };
+
+    tcon_lcd0_out: port@1 {
+     reg = <1>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_lcd0_out_dsi: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&dsi_in_tcon_lcd0>;
+     };
+    };
+   };
+  };
+
+  tcon_tv0: lcd-controller@5470000 {
+   compatible = "allwinner,sun20i-d1-tcon-tv";
+   reg = <0x5470000 0x1000>;
+   interrupts = <(91 + 16) 4>;
+   clocks = <&ccu 115>,
+     <&tcon_top 0>;
+   clock-names = "ahb", "tcon-ch1";
+   resets = <&ccu 53>;
+   reset-names = "lcd";
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_tv0_in: port@0 {
+     reg = <0>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+     };
+
+     tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+     };
+    };
+
+    tcon_tv0_out: port@1 {
+     reg = <1>;
+
+     tcon_tv0_out_tcon_top_hdmi: endpoint {
+      remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+     };
+    };
+   };
+  };
+
+  ppu: power-controller@7001000 {
+   compatible = "allwinner,sun20i-d1-ppu";
+   reg = <0x7001000 0x1000>;
+   clocks = <&r_ccu 4>;
+   resets = <&r_ccu 2>;
+   #power-domain-cells = <1>;
+  };
+
+  r_ccu: clock-controller@7010000 {
+   compatible = "allwinner,sun20i-d1-r-ccu";
+   reg = <0x7010000 0x400>;
+   clocks = <&dcxo>,
+     <&rtc 0>,
+     <&rtc 2>,
+     <&ccu 6>;
+   clock-names = "hosc", "losc", "iosc", "pll-periph";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  rtc: rtc@7090000 {
+   compatible = "allwinner,sun20i-d1-rtc",
+         "allwinner,sun50i-r329-rtc";
+   reg = <0x7090000 0x400>;
+   interrupts = <(144 + 16) 4>;
+   clocks = <&r_ccu 7>,
+     <&dcxo>,
+     <&r_ccu 0>;
+   clock-names = "bus", "hosc", "ahb";
+   #clock-cells = <1>;
+  };
+ };
+};
+# 7 "sun20i-d1s.dtsi" 2
+
+/ {
+ cpus {
+  timebase-frequency = <24000000>;
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  cpu0: cpu@0 {
+   compatible = "thead,c906", "riscv";
+   device_type = "cpu";
+   reg = <0>;
+   clocks = <&ccu 132>;
+   d-cache-block-size = <64>;
+   d-cache-sets = <256>;
+   d-cache-size = <32768>;
+   i-cache-block-size = <64>;
+   i-cache-sets = <128>;
+   i-cache-size = <32768>;
+   mmu-type = "riscv,sv39";
+   operating-points-v2 = <&opp_table_cpu>;
+   riscv,isa = "rv64imafdc";
+   riscv,isa-base = "rv64i";
+   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+            "zifencei", "zihpm";
+   #cooling-cells = <2>;
+
+   cpu0_intc: interrupt-controller {
+    compatible = "riscv,cpu-intc";
+    interrupt-controller;
+    #interrupt-cells = <1>;
+   };
+  };
+ };
+
+ opp_table_cpu: opp-table-cpu {
+  compatible = "operating-points-v2";
+
+  opp-408000000 {
+   opp-hz = /bits/ 64 <408000000>;
+   opp-microvolt = <900000 900000 1100000>;
+  };
+
+  opp-1080000000 {
+   opp-hz = /bits/ 64 <1008000000>;
+   opp-microvolt = <900000 900000 1100000>;
+  };
+ };
+
+ soc {
+  interrupt-parent = <&plic>;
+
+  riscv_wdt: watchdog@6011000 {
+   compatible = "allwinner,sun20i-d1-wdt";
+   reg = <0x6011000 0x20>;
+   interrupts = <(131 + 16) 4>;
+   clocks = <&dcxo>, <&rtc 0>;
+   clock-names = "hosc", "losc";
+  };
+
+  plic: interrupt-controller@10000000 {
+   compatible = "allwinner,sun20i-d1-plic",
+         "thead,c900-plic";
+   reg = <0x10000000 0x4000000>;
+   interrupts-extended = <&cpu0_intc 11>,
+           <&cpu0_intc 9>;
+   interrupt-controller;
+   riscv,ndev = <175>;
+   #address-cells = <0>;
+   #interrupt-cells = <2>;
+  };
+ };
+
+ pmu {
+  compatible = "riscv,pmu";
+  riscv,event-to-mhpmcounters =
+   <0x00003 0x00003 0x00000008>,
+   <0x00004 0x00004 0x00000010>,
+   <0x00005 0x00005 0x00000200>,
+   <0x00006 0x00006 0x00000100>,
+   <0x10000 0x10000 0x00004000>,
+   <0x10001 0x10001 0x00008000>,
+   <0x10002 0x10002 0x00010000>,
+   <0x10003 0x10003 0x00020000>,
+   <0x10019 0x10019 0x00000040>,
+   <0x10021 0x10021 0x00000020>;
+  riscv,event-to-mhpmevent =
+   <0x00003 0x00000000 0x00000001>,
+   <0x00004 0x00000000 0x00000002>,
+   <0x00005 0x00000000 0x00000007>,
+   <0x00006 0x00000000 0x00000006>,
+   <0x10000 0x00000000 0x0000000c>,
+   <0x10001 0x00000000 0x0000000d>,
+   <0x10002 0x00000000 0x0000000e>,
+   <0x10003 0x00000000 0x0000000f>,
+   <0x10019 0x00000000 0x00000004>,
+   <0x10021 0x00000000 0x00000003>;
+  riscv,raw-event-to-mhpmcounters =
+   <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
+   <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
+   <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
+   <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
+   <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
+   <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
+   <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
+   <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
+   <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
+   <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
+   <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
+   <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
+ };
+};
+# 5 "sun20i-d1.dtsi" 2
+# 1 "sunxi-d1-t113.dtsi" 1
+
+
+
+/ {
+ soc {
+  dsp_wdt: watchdog@1700400 {
+   compatible = "allwinner,sun20i-d1-wdt";
+   reg = <0x1700400 0x20>;
+   interrupts = <(122 + 16) 4>;
+   clocks = <&dcxo>, <&rtc 0>;
+   clock-names = "hosc", "losc";
+   status = "reserved";
+  };
+ };
+};
+# 6 "sun20i-d1.dtsi" 2
+
+/ {
+ soc {
+  lradc: keys@2009800 {
+   compatible = "allwinner,sun20i-d1-lradc",
+         "allwinner,sun50i-r329-lradc";
+   reg = <0x2009800 0x400>;
+   interrupts = <(61 + 16) 4>;
+   clocks = <&ccu 104>;
+   resets = <&ccu 47>;
+   status = "disabled";
+  };
+
+  i2s0: i2s@2032000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2032000 0x1000>;
+   interrupts = <(26 + 16) 4>;
+   clocks = <&ccu 86>,
+     <&ccu 82>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 34>;
+   dmas = <&dma 3>, <&dma 3>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+ };
+};
+
+&pio {
+ /omit-if-no-ref/
+ dmic_pb11_d0_pin: dmic-pb11-d0-pin {
+  pins = "PB11";
+  function = "dmic";
+ };
+
+ /omit-if-no-ref/
+ dmic_pe17_clk_pin: dmic-pe17-clk-pin {
+  pins = "PE17";
+  function = "dmic";
+ };
+
+ /omit-if-no-ref/
+ i2c0_pb10_pins: i2c0-pb10-pins {
+  pins = "PB10", "PB11";
+  function = "i2c0";
+ };
+
+ /omit-if-no-ref/
+ i2c2_pb0_pins: i2c2-pb0-pins {
+  pins = "PB0", "PB1";
+  function = "i2c2";
+ };
+
+ /omit-if-no-ref/
+ uart0_pb8_pins: uart0-pb8-pins {
+  pins = "PB8", "PB9";
+  function = "uart0";
+ };
+};
diff --git a/dts/dtspp/sun20i-d1s.dtsi b/dts/dtspp/sun20i-d1s.dtsi
new file mode 100644
index 0000000..c800f60
--- /dev/null
+++ b/dts/dtspp/sun20i-d1s.dtsi
@@ -0,0 +1,1058 @@
+# 0 "sun20i-d1s.dtsi"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "sun20i-d1s.dtsi"
+
+
+
+
+
+# 1 "sunxi-d1s-t113.dtsi" 1
+
+
+
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun6i-rtc.h" 1
+# 5 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-de2.h" 1
+# 6 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-tcon-top.h" 1
+# 7 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-ccu.h" 1
+# 8 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-r-ccu.h" 1
+# 9 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/interrupt-controller/irq.h" 1
+# 10 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun8i-de2.h" 1
+# 11 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-ccu.h" 1
+# 12 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-r-ccu.h" 1
+# 13 "sunxi-d1s-t113.dtsi" 2
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dcxo: dcxo-clk {
+  compatible = "fixed-clock";
+  clock-output-names = "dcxo";
+  #clock-cells = <0>;
+ };
+
+ de: display-engine {
+  compatible = "allwinner,sun20i-d1-display-engine";
+  allwinner,pipelines = <&mixer0>, <&mixer1>;
+  status = "disabled";
+ };
+
+ soc {
+  compatible = "simple-bus";
+  ranges;
+  dma-noncoherent;
+  #address-cells = <1>;
+  #size-cells = <1>;
+
+  pio: pinctrl@2000000 {
+   compatible = "allwinner,sun20i-d1-pinctrl";
+   reg = <0x2000000 0x800>;
+   interrupts = <(69 + 16) 4>,
+         <(71 + 16) 4>,
+         <(73 + 16) 4>,
+         <(75 + 16) 4>,
+         <(77 + 16) 4>,
+         <(79 + 16) 4>;
+   clocks = <&ccu 24>,
+     <&dcxo>,
+     <&rtc 0>;
+   clock-names = "apb", "hosc", "losc";
+   gpio-controller;
+   interrupt-controller;
+   #gpio-cells = <3>;
+   #interrupt-cells = <3>;
+
+   /omit-if-no-ref/
+   can0_pins: can0-pins {
+    pins = "PB2", "PB3";
+    function = "can0";
+   };
+
+   /omit-if-no-ref/
+   can1_pins: can1-pins {
+    pins = "PB4", "PB5";
+    function = "can1";
+   };
+
+   /omit-if-no-ref/
+   clk_pg11_pin: clk-pg11-pin {
+    pins = "PG11";
+    function = "clk";
+   };
+
+   /omit-if-no-ref/
+   dsi_4lane_pins: dsi-4lane-pins {
+    pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+           "PD6", "PD7", "PD8", "PD9";
+    drive-strength = <30>;
+    function = "dsi";
+   };
+
+   /omit-if-no-ref/
+   lcd_rgb666_pins: lcd-rgb666-pins {
+    pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+           "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
+           "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
+           "PD18", "PD19", "PD20", "PD21";
+    function = "lcd0";
+   };
+
+   /omit-if-no-ref/
+   mmc0_pins: mmc0-pins {
+    pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+    function = "mmc0";
+   };
+
+   /omit-if-no-ref/
+   mmc1_pins: mmc1-pins {
+    pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+    function = "mmc1";
+   };
+
+   /omit-if-no-ref/
+   mmc2_pins: mmc2-pins {
+    pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
+    function = "mmc2";
+   };
+
+   /omit-if-no-ref/
+   rgmii_pe_pins: rgmii-pe-pins {
+    pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+           "PE5", "PE6", "PE7", "PE8", "PE9",
+           "PE11", "PE12", "PE13", "PE14", "PE15";
+    function = "emac";
+   };
+
+   /omit-if-no-ref/
+   rmii_pe_pins: rmii-pe-pins {
+    pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+           "PE5", "PE6", "PE7", "PE8", "PE9";
+    function = "emac";
+   };
+
+   /omit-if-no-ref/
+   spi0_pins: spi0-pins {
+    pins = "PC2", "PC3", "PC4", "PC5";
+    function = "spi0";
+   };
+
+   /omit-if-no-ref/
+   uart1_pg6_pins: uart1-pg6-pins {
+    pins = "PG6", "PG7";
+    function = "uart1";
+   };
+
+   /omit-if-no-ref/
+   uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
+    pins = "PG8", "PG9";
+    function = "uart1";
+   };
+
+   /omit-if-no-ref/
+   uart3_pb_pins: uart3-pb-pins {
+    pins = "PB6", "PB7";
+    function = "uart3";
+   };
+  };
+
+  ccu: clock-controller@2001000 {
+   compatible = "allwinner,sun20i-d1-ccu";
+   reg = <0x2001000 0x1000>;
+   clocks = <&dcxo>,
+     <&rtc 0>,
+     <&rtc 2>;
+   clock-names = "hosc", "losc", "iosc";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  gpadc: adc@2009000 {
+   compatible = "allwinner,sun20i-d1-gpadc";
+   reg = <0x2009000 0x400>;
+   clocks = <&ccu 80>;
+   resets = <&ccu 32>;
+   interrupts = <(57 + 16) 4>;
+   status = "disabled";
+   #io-channel-cells = <1>;
+  };
+
+  dmic: dmic@2031000 {
+   compatible = "allwinner,sun20i-d1-dmic",
+         "allwinner,sun50i-h6-dmic";
+   reg = <0x2031000 0x400>;
+   interrupts = <(24 + 16) 4>;
+   clocks = <&ccu 93>,
+     <&ccu 92>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 38>;
+   dmas = <&dma 8>;
+   dma-names = "rx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  i2s1: i2s@2033000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2033000 0x1000>;
+   interrupts = <(27 + 16) 4>;
+   clocks = <&ccu 87>,
+     <&ccu 83>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 35>;
+   dmas = <&dma 4>, <&dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  i2s2: i2s@2034000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2034000 0x1000>;
+   interrupts = <(28 + 16) 4>;
+   clocks = <&ccu 88>,
+     <&ccu 84>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 36>;
+   dmas = <&dma 5>, <&dma 5>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  timer: timer@2050000 {
+   compatible = "allwinner,sun20i-d1-timer",
+         "allwinner,sun8i-a23-timer";
+   reg = <0x2050000 0xa0>;
+   interrupts = <(59 + 16) 4>,
+         <(60 + 16) 4>;
+   clocks = <&dcxo>;
+  };
+
+  wdt: watchdog@20500a0 {
+   compatible = "allwinner,sun20i-d1-wdt-reset",
+         "allwinner,sun20i-d1-wdt";
+   reg = <0x20500a0 0x20>;
+   interrupts = <(63 + 16) 4>;
+   clocks = <&dcxo>, <&rtc 0>;
+   clock-names = "hosc", "losc";
+   status = "reserved";
+  };
+
+  uart0: serial@2500000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500000 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(2 + 16) 4>;
+   clocks = <&ccu 62>;
+   resets = <&ccu 18>;
+   dmas = <&dma 14>, <&dma 14>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart1: serial@2500400 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500400 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(3 + 16) 4>;
+   clocks = <&ccu 63>;
+   resets = <&ccu 19>;
+   dmas = <&dma 15>, <&dma 15>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart2: serial@2500800 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500800 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(4 + 16) 4>;
+   clocks = <&ccu 64>;
+   resets = <&ccu 20>;
+   dmas = <&dma 16>, <&dma 16>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart3: serial@2500c00 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500c00 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(5 + 16) 4>;
+   clocks = <&ccu 65>;
+   resets = <&ccu 21>;
+   dmas = <&dma 17>, <&dma 17>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart4: serial@2501000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2501000 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(6 + 16) 4>;
+   clocks = <&ccu 66>;
+   resets = <&ccu 22>;
+   dmas = <&dma 18>, <&dma 18>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart5: serial@2501400 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2501400 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <(7 + 16) 4>;
+   clocks = <&ccu 67>;
+   resets = <&ccu 23>;
+   dmas = <&dma 19>, <&dma 19>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  i2c0: i2c@2502000 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502000 0x400>;
+   interrupts = <(9 + 16) 4>;
+   clocks = <&ccu 68>;
+   resets = <&ccu 24>;
+   dmas = <&dma 43>, <&dma 43>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c1: i2c@2502400 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502400 0x400>;
+   interrupts = <(10 + 16) 4>;
+   clocks = <&ccu 69>;
+   resets = <&ccu 25>;
+   dmas = <&dma 44>, <&dma 44>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c2: i2c@2502800 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502800 0x400>;
+   interrupts = <(11 + 16) 4>;
+   clocks = <&ccu 70>;
+   resets = <&ccu 26>;
+   dmas = <&dma 45>, <&dma 45>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c3: i2c@2502c00 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502c00 0x400>;
+   interrupts = <(12 + 16) 4>;
+   clocks = <&ccu 71>;
+   resets = <&ccu 27>;
+   dmas = <&dma 46>, <&dma 46>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  can0: can@2504000 {
+   compatible = "allwinner,sun20i-d1-can";
+   reg = <0x02504000 0x400>;
+   interrupts = <(21 + 16) 4>;
+   clocks = <&ccu 145>;
+   resets = <&ccu 66>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&can0_pins>;
+   status = "disabled";
+  };
+
+  can1: can@2504400 {
+   compatible = "allwinner,sun20i-d1-can";
+   reg = <0x02504400 0x400>;
+   interrupts = <(22 + 16) 4>;
+   clocks = <&ccu 146>;
+   resets = <&ccu 67>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&can1_pins>;
+   status = "disabled";
+  };
+
+  syscon: syscon@3000000 {
+   compatible = "allwinner,sun20i-d1-system-control";
+   reg = <0x3000000 0x1000>;
+   ranges;
+   #address-cells = <1>;
+   #size-cells = <1>;
+  };
+
+  dma: dma-controller@3002000 {
+   compatible = "allwinner,sun20i-d1-dma";
+   reg = <0x3002000 0x1000>;
+   interrupts = <(50 + 16) 4>;
+   clocks = <&ccu 37>, <&ccu 48>;
+   clock-names = "bus", "mbus";
+   resets = <&ccu 6>;
+   dma-channels = <16>;
+   dma-requests = <48>;
+   #dma-cells = <1>;
+  };
+
+  sid: efuse@3006000 {
+   compatible = "allwinner,sun20i-d1-sid";
+   reg = <0x3006000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+  };
+
+  crypto: crypto@3040000 {
+   compatible = "allwinner,sun20i-d1-crypto";
+   reg = <0x3040000 0x800>;
+   interrupts = <(52 + 16) 4>;
+   clocks = <&ccu 34>,
+     <&ccu 33>,
+     <&ccu 50>,
+     <&rtc 2>;
+   clock-names = "bus", "mod", "ram", "trng";
+   resets = <&ccu 4>;
+  };
+
+  mbus: dram-controller@3102000 {
+   compatible = "allwinner,sun20i-d1-mbus";
+   reg = <0x3102000 0x1000>,
+         <0x3103000 0x1000>;
+   reg-names = "mbus", "dram";
+   interrupts = <(43 + 16) 4>;
+   clocks = <&ccu 26>,
+     <&ccu 47>,
+     <&ccu 55>;
+   clock-names = "mbus", "dram", "bus";
+   dma-ranges = <0 0x40000000 0x80000000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   #interconnect-cells = <1>;
+  };
+
+  mmc0: mmc@4020000 {
+   compatible = "allwinner,sun20i-d1-mmc";
+   reg = <0x4020000 0x1000>;
+   interrupts = <(40 + 16) 4>;
+   clocks = <&ccu 59>, <&ccu 56>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 15>;
+   reset-names = "ahb";
+   cap-sd-highspeed;
+   max-frequency = <150000000>;
+   no-mmc;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  mmc1: mmc@4021000 {
+   compatible = "allwinner,sun20i-d1-mmc";
+   reg = <0x4021000 0x1000>;
+   interrupts = <(41 + 16) 4>;
+   clocks = <&ccu 60>, <&ccu 57>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 16>;
+   reset-names = "ahb";
+   cap-sd-highspeed;
+   max-frequency = <150000000>;
+   no-mmc;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  mmc2: mmc@4022000 {
+   compatible = "allwinner,sun20i-d1-emmc",
+         "allwinner,sun50i-a100-emmc";
+   reg = <0x4022000 0x1000>;
+   interrupts = <(42 + 16) 4>;
+   clocks = <&ccu 61>, <&ccu 58>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 17>;
+   reset-names = "ahb";
+   cap-mmc-highspeed;
+   max-frequency = <150000000>;
+   mmc-ddr-1_8v;
+   mmc-ddr-3_3v;
+   no-sd;
+   no-sdio;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  spi0: spi@4025000 {
+   compatible = "allwinner,sun20i-d1-spi",
+         "allwinner,sun50i-r329-spi";
+   reg = <0x04025000 0x1000>;
+   interrupts = <(15 + 16) 4>;
+   clocks = <&ccu 74>, <&ccu 72>;
+   clock-names = "ahb", "mod";
+   dmas = <&dma 22>, <&dma 22>;
+   dma-names = "rx", "tx";
+   resets = <&ccu 28>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  spi1: spi@4026000 {
+   compatible = "allwinner,sun20i-d1-spi-dbi",
+         "allwinner,sun50i-r329-spi-dbi",
+         "allwinner,sun50i-r329-spi";
+   reg = <0x04026000 0x1000>;
+   interrupts = <(16 + 16) 4>;
+   clocks = <&ccu 75>, <&ccu 73>;
+   clock-names = "ahb", "mod";
+   dmas = <&dma 23>, <&dma 23>;
+   dma-names = "rx", "tx";
+   resets = <&ccu 29>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  usb_otg: usb@4100000 {
+   compatible = "allwinner,sun20i-d1-musb",
+         "allwinner,sun8i-a33-musb";
+   reg = <0x4100000 0x400>;
+   interrupts = <(29 + 16) 4>;
+   interrupt-names = "mc";
+   clocks = <&ccu 103>;
+   resets = <&ccu 46>;
+   extcon = <&usbphy 0>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  usbphy: phy@4100400 {
+   compatible = "allwinner,sun20i-d1-usb-phy";
+   reg = <0x4100400 0x100>,
+         <0x4101800 0x100>,
+         <0x4200800 0x100>;
+   reg-names = "phy_ctrl",
+        "pmu0",
+        "pmu1";
+   clocks = <&dcxo>,
+     <&dcxo>;
+   clock-names = "usb0_phy",
+          "usb1_phy";
+   resets = <&ccu 40>,
+     <&ccu 41>;
+   reset-names = "usb0_reset",
+          "usb1_reset";
+   status = "disabled";
+   #phy-cells = <1>;
+  };
+
+  ehci0: usb@4101000 {
+   compatible = "allwinner,sun20i-d1-ehci",
+         "generic-ehci";
+   reg = <0x4101000 0x100>;
+   interrupts = <(30 + 16) 4>;
+   clocks = <&ccu 99>,
+     <&ccu 101>,
+     <&ccu 97>;
+   resets = <&ccu 42>,
+     <&ccu 44>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ohci0: usb@4101400 {
+   compatible = "allwinner,sun20i-d1-ohci",
+         "generic-ohci";
+   reg = <0x4101400 0x100>;
+   interrupts = <(31 + 16) 4>;
+   clocks = <&ccu 99>,
+     <&ccu 97>;
+   resets = <&ccu 42>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ehci1: usb@4200000 {
+   compatible = "allwinner,sun20i-d1-ehci",
+         "generic-ehci";
+   reg = <0x4200000 0x100>;
+   interrupts = <(33 + 16) 4>;
+   clocks = <&ccu 100>,
+     <&ccu 102>,
+     <&ccu 98>;
+   resets = <&ccu 43>,
+     <&ccu 45>;
+   phys = <&usbphy 1>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ohci1: usb@4200400 {
+   compatible = "allwinner,sun20i-d1-ohci",
+         "generic-ohci";
+   reg = <0x4200400 0x100>;
+   interrupts = <(34 + 16) 4>;
+   clocks = <&ccu 100>,
+     <&ccu 98>;
+   resets = <&ccu 43>;
+   phys = <&usbphy 1>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  emac: ethernet@4500000 {
+   compatible = "allwinner,sun20i-d1-emac",
+         "allwinner,sun50i-a64-emac";
+   reg = <0x4500000 0x10000>;
+   interrupts = <(46 + 16) 4>;
+   interrupt-names = "macirq";
+   clocks = <&ccu 77>;
+   clock-names = "stmmaceth";
+   resets = <&ccu 30>;
+   reset-names = "stmmaceth";
+   syscon = <&syscon>;
+   status = "disabled";
+
+   mdio: mdio {
+    compatible = "snps,dwmac-mdio";
+    #address-cells = <1>;
+    #size-cells = <0>;
+   };
+  };
+
+  display_clocks: clock-controller@5000000 {
+   compatible = "allwinner,sun20i-d1-de2-clk",
+         "allwinner,sun50i-h5-de2-clk";
+   reg = <0x5000000 0x10000>;
+   clocks = <&ccu 28>, <&ccu 27>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 1>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  mixer0: mixer@5100000 {
+   compatible = "allwinner,sun20i-d1-de2-mixer-0";
+   reg = <0x5100000 0x100000>;
+   clocks = <&display_clocks 0>,
+     <&display_clocks 6>;
+   clock-names = "bus", "mod";
+   resets = <&display_clocks 0>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mixer0_out: port@1 {
+     reg = <1>;
+
+     mixer0_out_tcon_top_mixer0: endpoint {
+      remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+     };
+    };
+   };
+  };
+
+  mixer1: mixer@5200000 {
+   compatible = "allwinner,sun20i-d1-de2-mixer-1";
+   reg = <0x5200000 0x100000>;
+   clocks = <&display_clocks 1>,
+     <&display_clocks 7>;
+   clock-names = "bus", "mod";
+   resets = <&display_clocks 1>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mixer1_out: port@1 {
+     reg = <1>;
+
+     mixer1_out_tcon_top_mixer1: endpoint {
+      remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+     };
+    };
+   };
+  };
+
+  dsi: dsi@5450000 {
+   compatible = "allwinner,sun20i-d1-mipi-dsi",
+         "allwinner,sun50i-a100-mipi-dsi";
+   reg = <0x5450000 0x1000>;
+   interrupts = <(92 + 16) 4>;
+   clocks = <&ccu 111>,
+     <&tcon_top 2>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 51>;
+   phys = <&dphy>;
+   phy-names = "dphy";
+   status = "disabled";
+
+   port {
+    dsi_in_tcon_lcd0: endpoint {
+     remote-endpoint = <&tcon_lcd0_out_dsi>;
+    };
+   };
+  };
+
+  dphy: phy@5451000 {
+   compatible = "allwinner,sun20i-d1-mipi-dphy",
+         "allwinner,sun50i-a100-mipi-dphy";
+   reg = <0x5451000 0x1000>;
+   interrupts = <(92 + 16) 4>;
+   clocks = <&ccu 111>,
+     <&ccu 110>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 51>;
+   #phy-cells = <0>;
+  };
+
+  tcon_top: tcon-top@5460000 {
+   compatible = "allwinner,sun20i-d1-tcon-top";
+   reg = <0x5460000 0x1000>;
+   clocks = <&ccu 105>,
+     <&ccu 114>,
+     <&ccu 116>,
+     <&ccu 112>;
+   clock-names = "bus", "tcon-tv0", "tve0", "dsi";
+   clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
+   resets = <&ccu 48>;
+   #clock-cells = <1>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_top_mixer0_in: port@0 {
+     reg = <0>;
+
+     tcon_top_mixer0_in_mixer0: endpoint {
+      remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+     };
+    };
+
+    tcon_top_mixer0_out: port@1 {
+     reg = <1>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
+     };
+
+     tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+      reg = <2>;
+      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+     };
+    };
+
+    tcon_top_mixer1_in: port@2 {
+     reg = <2>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer1_in_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
+     };
+    };
+
+    tcon_top_mixer1_out: port@3 {
+     reg = <3>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
+     };
+
+     tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+      reg = <2>;
+      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+     };
+    };
+
+    tcon_top_hdmi_in: port@4 {
+     reg = <4>;
+
+     tcon_top_hdmi_in_tcon_tv0: endpoint {
+      remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
+     };
+    };
+
+    tcon_top_hdmi_out: port@5 {
+     reg = <5>;
+    };
+   };
+  };
+
+  tcon_lcd0: lcd-controller@5461000 {
+   compatible = "allwinner,sun20i-d1-tcon-lcd";
+   reg = <0x5461000 0x1000>;
+   interrupts = <(90 + 16) 4>;
+   clocks = <&ccu 113>,
+     <&ccu 112>;
+   clock-names = "ahb", "tcon-ch0";
+   clock-output-names = "tcon-pixel-clock";
+   resets = <&ccu 52>,
+     <&ccu 54>;
+   reset-names = "lcd", "lvds";
+   #clock-cells = <0>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_lcd0_in: port@0 {
+     reg = <0>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
+     };
+
+     tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
+     };
+    };
+
+    tcon_lcd0_out: port@1 {
+     reg = <1>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_lcd0_out_dsi: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&dsi_in_tcon_lcd0>;
+     };
+    };
+   };
+  };
+
+  tcon_tv0: lcd-controller@5470000 {
+   compatible = "allwinner,sun20i-d1-tcon-tv";
+   reg = <0x5470000 0x1000>;
+   interrupts = <(91 + 16) 4>;
+   clocks = <&ccu 115>,
+     <&tcon_top 0>;
+   clock-names = "ahb", "tcon-ch1";
+   resets = <&ccu 53>;
+   reset-names = "lcd";
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_tv0_in: port@0 {
+     reg = <0>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+     };
+
+     tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+     };
+    };
+
+    tcon_tv0_out: port@1 {
+     reg = <1>;
+
+     tcon_tv0_out_tcon_top_hdmi: endpoint {
+      remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+     };
+    };
+   };
+  };
+
+  ppu: power-controller@7001000 {
+   compatible = "allwinner,sun20i-d1-ppu";
+   reg = <0x7001000 0x1000>;
+   clocks = <&r_ccu 4>;
+   resets = <&r_ccu 2>;
+   #power-domain-cells = <1>;
+  };
+
+  r_ccu: clock-controller@7010000 {
+   compatible = "allwinner,sun20i-d1-r-ccu";
+   reg = <0x7010000 0x400>;
+   clocks = <&dcxo>,
+     <&rtc 0>,
+     <&rtc 2>,
+     <&ccu 6>;
+   clock-names = "hosc", "losc", "iosc", "pll-periph";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  rtc: rtc@7090000 {
+   compatible = "allwinner,sun20i-d1-rtc",
+         "allwinner,sun50i-r329-rtc";
+   reg = <0x7090000 0x400>;
+   interrupts = <(144 + 16) 4>;
+   clocks = <&r_ccu 7>,
+     <&dcxo>,
+     <&r_ccu 0>;
+   clock-names = "bus", "hosc", "ahb";
+   #clock-cells = <1>;
+  };
+ };
+};
+# 7 "sun20i-d1s.dtsi" 2
+
+/ {
+ cpus {
+  timebase-frequency = <24000000>;
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  cpu0: cpu@0 {
+   compatible = "thead,c906", "riscv";
+   device_type = "cpu";
+   reg = <0>;
+   clocks = <&ccu 132>;
+   d-cache-block-size = <64>;
+   d-cache-sets = <256>;
+   d-cache-size = <32768>;
+   i-cache-block-size = <64>;
+   i-cache-sets = <128>;
+   i-cache-size = <32768>;
+   mmu-type = "riscv,sv39";
+   operating-points-v2 = <&opp_table_cpu>;
+   riscv,isa = "rv64imafdc";
+   riscv,isa-base = "rv64i";
+   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+            "zifencei", "zihpm";
+   #cooling-cells = <2>;
+
+   cpu0_intc: interrupt-controller {
+    compatible = "riscv,cpu-intc";
+    interrupt-controller;
+    #interrupt-cells = <1>;
+   };
+  };
+ };
+
+ opp_table_cpu: opp-table-cpu {
+  compatible = "operating-points-v2";
+
+  opp-408000000 {
+   opp-hz = /bits/ 64 <408000000>;
+   opp-microvolt = <900000 900000 1100000>;
+  };
+
+  opp-1080000000 {
+   opp-hz = /bits/ 64 <1008000000>;
+   opp-microvolt = <900000 900000 1100000>;
+  };
+ };
+
+ soc {
+  interrupt-parent = <&plic>;
+
+  riscv_wdt: watchdog@6011000 {
+   compatible = "allwinner,sun20i-d1-wdt";
+   reg = <0x6011000 0x20>;
+   interrupts = <(131 + 16) 4>;
+   clocks = <&dcxo>, <&rtc 0>;
+   clock-names = "hosc", "losc";
+  };
+
+  plic: interrupt-controller@10000000 {
+   compatible = "allwinner,sun20i-d1-plic",
+         "thead,c900-plic";
+   reg = <0x10000000 0x4000000>;
+   interrupts-extended = <&cpu0_intc 11>,
+           <&cpu0_intc 9>;
+   interrupt-controller;
+   riscv,ndev = <175>;
+   #address-cells = <0>;
+   #interrupt-cells = <2>;
+  };
+ };
+
+ pmu {
+  compatible = "riscv,pmu";
+  riscv,event-to-mhpmcounters =
+   <0x00003 0x00003 0x00000008>,
+   <0x00004 0x00004 0x00000010>,
+   <0x00005 0x00005 0x00000200>,
+   <0x00006 0x00006 0x00000100>,
+   <0x10000 0x10000 0x00004000>,
+   <0x10001 0x10001 0x00008000>,
+   <0x10002 0x10002 0x00010000>,
+   <0x10003 0x10003 0x00020000>,
+   <0x10019 0x10019 0x00000040>,
+   <0x10021 0x10021 0x00000020>;
+  riscv,event-to-mhpmevent =
+   <0x00003 0x00000000 0x00000001>,
+   <0x00004 0x00000000 0x00000002>,
+   <0x00005 0x00000000 0x00000007>,
+   <0x00006 0x00000000 0x00000006>,
+   <0x10000 0x00000000 0x0000000c>,
+   <0x10001 0x00000000 0x0000000d>,
+   <0x10002 0x00000000 0x0000000e>,
+   <0x10003 0x00000000 0x0000000f>,
+   <0x10019 0x00000000 0x00000004>,
+   <0x10021 0x00000000 0x00000003>;
+  riscv,raw-event-to-mhpmcounters =
+   <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
+   <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
+   <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
+   <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
+   <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
+   <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
+   <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
+   <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
+   <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
+   <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
+   <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
+   <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
+ };
+};
diff --git a/dts/dtspp/sunxi-d1-t113.dtsi b/dts/dtspp/sunxi-d1-t113.dtsi
new file mode 100644
index 0000000..b33b616
--- /dev/null
+++ b/dts/dtspp/sunxi-d1-t113.dtsi
@@ -0,0 +1,19 @@
+# 0 "sunxi-d1-t113.dtsi"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "sunxi-d1-t113.dtsi"
+
+
+
+/ {
+ soc {
+  dsp_wdt: watchdog@1700400 {
+   compatible = "allwinner,sun20i-d1-wdt";
+   reg = <0x1700400 0x20>;
+   interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+   clock-names = "hosc", "losc";
+   status = "reserved";
+  };
+ };
+};
diff --git a/dts/dtspp/sunxi-d1s-t113.dtsi b/dts/dtspp/sunxi-d1s-t113.dtsi
new file mode 100644
index 0000000..e70a097
--- /dev/null
+++ b/dts/dtspp/sunxi-d1s-t113.dtsi
@@ -0,0 +1,940 @@
+# 0 "sunxi-d1s-t113.dtsi"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "sunxi-d1s-t113.dtsi"
+
+
+
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun6i-rtc.h" 1
+# 5 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-de2.h" 1
+# 6 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-tcon-top.h" 1
+# 7 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-ccu.h" 1
+# 8 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-r-ccu.h" 1
+# 9 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/interrupt-controller/irq.h" 1
+# 10 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun8i-de2.h" 1
+# 11 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-ccu.h" 1
+# 12 "sunxi-d1s-t113.dtsi" 2
+# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-r-ccu.h" 1
+# 13 "sunxi-d1s-t113.dtsi" 2
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dcxo: dcxo-clk {
+  compatible = "fixed-clock";
+  clock-output-names = "dcxo";
+  #clock-cells = <0>;
+ };
+
+ de: display-engine {
+  compatible = "allwinner,sun20i-d1-display-engine";
+  allwinner,pipelines = <&mixer0>, <&mixer1>;
+  status = "disabled";
+ };
+
+ soc {
+  compatible = "simple-bus";
+  ranges;
+  dma-noncoherent;
+  #address-cells = <1>;
+  #size-cells = <1>;
+
+  pio: pinctrl@2000000 {
+   compatible = "allwinner,sun20i-d1-pinctrl";
+   reg = <0x2000000 0x800>;
+   interrupts = <SOC_PERIPHERAL_IRQ(69) 4>,
+         <SOC_PERIPHERAL_IRQ(71) 4>,
+         <SOC_PERIPHERAL_IRQ(73) 4>,
+         <SOC_PERIPHERAL_IRQ(75) 4>,
+         <SOC_PERIPHERAL_IRQ(77) 4>,
+         <SOC_PERIPHERAL_IRQ(79) 4>;
+   clocks = <&ccu 24>,
+     <&dcxo>,
+     <&rtc 0>;
+   clock-names = "apb", "hosc", "losc";
+   gpio-controller;
+   interrupt-controller;
+   #gpio-cells = <3>;
+   #interrupt-cells = <3>;
+
+   /omit-if-no-ref/
+   can0_pins: can0-pins {
+    pins = "PB2", "PB3";
+    function = "can0";
+   };
+
+   /omit-if-no-ref/
+   can1_pins: can1-pins {
+    pins = "PB4", "PB5";
+    function = "can1";
+   };
+
+   /omit-if-no-ref/
+   clk_pg11_pin: clk-pg11-pin {
+    pins = "PG11";
+    function = "clk";
+   };
+
+   /omit-if-no-ref/
+   dsi_4lane_pins: dsi-4lane-pins {
+    pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+           "PD6", "PD7", "PD8", "PD9";
+    drive-strength = <30>;
+    function = "dsi";
+   };
+
+   /omit-if-no-ref/
+   lcd_rgb666_pins: lcd-rgb666-pins {
+    pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+           "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
+           "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
+           "PD18", "PD19", "PD20", "PD21";
+    function = "lcd0";
+   };
+
+   /omit-if-no-ref/
+   mmc0_pins: mmc0-pins {
+    pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+    function = "mmc0";
+   };
+
+   /omit-if-no-ref/
+   mmc1_pins: mmc1-pins {
+    pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+    function = "mmc1";
+   };
+
+   /omit-if-no-ref/
+   mmc2_pins: mmc2-pins {
+    pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
+    function = "mmc2";
+   };
+
+   /omit-if-no-ref/
+   rgmii_pe_pins: rgmii-pe-pins {
+    pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+           "PE5", "PE6", "PE7", "PE8", "PE9",
+           "PE11", "PE12", "PE13", "PE14", "PE15";
+    function = "emac";
+   };
+
+   /omit-if-no-ref/
+   rmii_pe_pins: rmii-pe-pins {
+    pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+           "PE5", "PE6", "PE7", "PE8", "PE9";
+    function = "emac";
+   };
+
+   /omit-if-no-ref/
+   spi0_pins: spi0-pins {
+    pins = "PC2", "PC3", "PC4", "PC5";
+    function = "spi0";
+   };
+
+   /omit-if-no-ref/
+   uart1_pg6_pins: uart1-pg6-pins {
+    pins = "PG6", "PG7";
+    function = "uart1";
+   };
+
+   /omit-if-no-ref/
+   uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
+    pins = "PG8", "PG9";
+    function = "uart1";
+   };
+
+   /omit-if-no-ref/
+   uart3_pb_pins: uart3-pb-pins {
+    pins = "PB6", "PB7";
+    function = "uart3";
+   };
+  };
+
+  ccu: clock-controller@2001000 {
+   compatible = "allwinner,sun20i-d1-ccu";
+   reg = <0x2001000 0x1000>;
+   clocks = <&dcxo>,
+     <&rtc 0>,
+     <&rtc 2>;
+   clock-names = "hosc", "losc", "iosc";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  gpadc: adc@2009000 {
+   compatible = "allwinner,sun20i-d1-gpadc";
+   reg = <0x2009000 0x400>;
+   clocks = <&ccu 80>;
+   resets = <&ccu 32>;
+   interrupts = <SOC_PERIPHERAL_IRQ(57) 4>;
+   status = "disabled";
+   #io-channel-cells = <1>;
+  };
+
+  dmic: dmic@2031000 {
+   compatible = "allwinner,sun20i-d1-dmic",
+         "allwinner,sun50i-h6-dmic";
+   reg = <0x2031000 0x400>;
+   interrupts = <SOC_PERIPHERAL_IRQ(24) 4>;
+   clocks = <&ccu 93>,
+     <&ccu 92>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 38>;
+   dmas = <&dma 8>;
+   dma-names = "rx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  i2s1: i2s@2033000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2033000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(27) 4>;
+   clocks = <&ccu 87>,
+     <&ccu 83>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 35>;
+   dmas = <&dma 4>, <&dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  i2s2: i2s@2034000 {
+   compatible = "allwinner,sun20i-d1-i2s",
+         "allwinner,sun50i-r329-i2s";
+   reg = <0x2034000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(28) 4>;
+   clocks = <&ccu 88>,
+     <&ccu 84>;
+   clock-names = "apb", "mod";
+   resets = <&ccu 36>;
+   dmas = <&dma 5>, <&dma 5>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #sound-dai-cells = <0>;
+  };
+
+  timer: timer@2050000 {
+   compatible = "allwinner,sun20i-d1-timer",
+         "allwinner,sun8i-a23-timer";
+   reg = <0x2050000 0xa0>;
+   interrupts = <SOC_PERIPHERAL_IRQ(59) 4>,
+         <SOC_PERIPHERAL_IRQ(60) 4>;
+   clocks = <&dcxo>;
+  };
+
+  wdt: watchdog@20500a0 {
+   compatible = "allwinner,sun20i-d1-wdt-reset",
+         "allwinner,sun20i-d1-wdt";
+   reg = <0x20500a0 0x20>;
+   interrupts = <SOC_PERIPHERAL_IRQ(63) 4>;
+   clocks = <&dcxo>, <&rtc 0>;
+   clock-names = "hosc", "losc";
+   status = "reserved";
+  };
+
+  uart0: serial@2500000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500000 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <SOC_PERIPHERAL_IRQ(2) 4>;
+   clocks = <&ccu 62>;
+   resets = <&ccu 18>;
+   dmas = <&dma 14>, <&dma 14>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart1: serial@2500400 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500400 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <SOC_PERIPHERAL_IRQ(3) 4>;
+   clocks = <&ccu 63>;
+   resets = <&ccu 19>;
+   dmas = <&dma 15>, <&dma 15>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart2: serial@2500800 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500800 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <SOC_PERIPHERAL_IRQ(4) 4>;
+   clocks = <&ccu 64>;
+   resets = <&ccu 20>;
+   dmas = <&dma 16>, <&dma 16>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart3: serial@2500c00 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2500c00 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <SOC_PERIPHERAL_IRQ(5) 4>;
+   clocks = <&ccu 65>;
+   resets = <&ccu 21>;
+   dmas = <&dma 17>, <&dma 17>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart4: serial@2501000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2501000 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <SOC_PERIPHERAL_IRQ(6) 4>;
+   clocks = <&ccu 66>;
+   resets = <&ccu 22>;
+   dmas = <&dma 18>, <&dma 18>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  uart5: serial@2501400 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2501400 0x400>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+   interrupts = <SOC_PERIPHERAL_IRQ(7) 4>;
+   clocks = <&ccu 67>;
+   resets = <&ccu 23>;
+   dmas = <&dma 19>, <&dma 19>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+  };
+
+  i2c0: i2c@2502000 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502000 0x400>;
+   interrupts = <SOC_PERIPHERAL_IRQ(9) 4>;
+   clocks = <&ccu 68>;
+   resets = <&ccu 24>;
+   dmas = <&dma 43>, <&dma 43>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c1: i2c@2502400 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502400 0x400>;
+   interrupts = <SOC_PERIPHERAL_IRQ(10) 4>;
+   clocks = <&ccu 69>;
+   resets = <&ccu 25>;
+   dmas = <&dma 44>, <&dma 44>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c2: i2c@2502800 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502800 0x400>;
+   interrupts = <SOC_PERIPHERAL_IRQ(11) 4>;
+   clocks = <&ccu 70>;
+   resets = <&ccu 26>;
+   dmas = <&dma 45>, <&dma 45>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  i2c3: i2c@2502c00 {
+   compatible = "allwinner,sun20i-d1-i2c",
+         "allwinner,sun8i-v536-i2c",
+         "allwinner,sun6i-a31-i2c";
+   reg = <0x2502c00 0x400>;
+   interrupts = <SOC_PERIPHERAL_IRQ(12) 4>;
+   clocks = <&ccu 71>;
+   resets = <&ccu 27>;
+   dmas = <&dma 46>, <&dma 46>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  can0: can@2504000 {
+   compatible = "allwinner,sun20i-d1-can";
+   reg = <0x02504000 0x400>;
+   interrupts = <SOC_PERIPHERAL_IRQ(21) 4>;
+   clocks = <&ccu 145>;
+   resets = <&ccu 66>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&can0_pins>;
+   status = "disabled";
+  };
+
+  can1: can@2504400 {
+   compatible = "allwinner,sun20i-d1-can";
+   reg = <0x02504400 0x400>;
+   interrupts = <SOC_PERIPHERAL_IRQ(22) 4>;
+   clocks = <&ccu 146>;
+   resets = <&ccu 67>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&can1_pins>;
+   status = "disabled";
+  };
+
+  syscon: syscon@3000000 {
+   compatible = "allwinner,sun20i-d1-system-control";
+   reg = <0x3000000 0x1000>;
+   ranges;
+   #address-cells = <1>;
+   #size-cells = <1>;
+  };
+
+  dma: dma-controller@3002000 {
+   compatible = "allwinner,sun20i-d1-dma";
+   reg = <0x3002000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(50) 4>;
+   clocks = <&ccu 37>, <&ccu 48>;
+   clock-names = "bus", "mbus";
+   resets = <&ccu 6>;
+   dma-channels = <16>;
+   dma-requests = <48>;
+   #dma-cells = <1>;
+  };
+
+  sid: efuse@3006000 {
+   compatible = "allwinner,sun20i-d1-sid";
+   reg = <0x3006000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+  };
+
+  crypto: crypto@3040000 {
+   compatible = "allwinner,sun20i-d1-crypto";
+   reg = <0x3040000 0x800>;
+   interrupts = <SOC_PERIPHERAL_IRQ(52) 4>;
+   clocks = <&ccu 34>,
+     <&ccu 33>,
+     <&ccu 50>,
+     <&rtc 2>;
+   clock-names = "bus", "mod", "ram", "trng";
+   resets = <&ccu 4>;
+  };
+
+  mbus: dram-controller@3102000 {
+   compatible = "allwinner,sun20i-d1-mbus";
+   reg = <0x3102000 0x1000>,
+         <0x3103000 0x1000>;
+   reg-names = "mbus", "dram";
+   interrupts = <SOC_PERIPHERAL_IRQ(43) 4>;
+   clocks = <&ccu 26>,
+     <&ccu 47>,
+     <&ccu 55>;
+   clock-names = "mbus", "dram", "bus";
+   dma-ranges = <0 0x40000000 0x80000000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   #interconnect-cells = <1>;
+  };
+
+  mmc0: mmc@4020000 {
+   compatible = "allwinner,sun20i-d1-mmc";
+   reg = <0x4020000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(40) 4>;
+   clocks = <&ccu 59>, <&ccu 56>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 15>;
+   reset-names = "ahb";
+   cap-sd-highspeed;
+   max-frequency = <150000000>;
+   no-mmc;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  mmc1: mmc@4021000 {
+   compatible = "allwinner,sun20i-d1-mmc";
+   reg = <0x4021000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(41) 4>;
+   clocks = <&ccu 60>, <&ccu 57>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 16>;
+   reset-names = "ahb";
+   cap-sd-highspeed;
+   max-frequency = <150000000>;
+   no-mmc;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  mmc2: mmc@4022000 {
+   compatible = "allwinner,sun20i-d1-emmc",
+         "allwinner,sun50i-a100-emmc";
+   reg = <0x4022000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(42) 4>;
+   clocks = <&ccu 61>, <&ccu 58>;
+   clock-names = "ahb", "mmc";
+   resets = <&ccu 17>;
+   reset-names = "ahb";
+   cap-mmc-highspeed;
+   max-frequency = <150000000>;
+   mmc-ddr-1_8v;
+   mmc-ddr-3_3v;
+   no-sd;
+   no-sdio;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  spi0: spi@4025000 {
+   compatible = "allwinner,sun20i-d1-spi",
+         "allwinner,sun50i-r329-spi";
+   reg = <0x04025000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(15) 4>;
+   clocks = <&ccu 74>, <&ccu 72>;
+   clock-names = "ahb", "mod";
+   dmas = <&dma 22>, <&dma 22>;
+   dma-names = "rx", "tx";
+   resets = <&ccu 28>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  spi1: spi@4026000 {
+   compatible = "allwinner,sun20i-d1-spi-dbi",
+         "allwinner,sun50i-r329-spi-dbi",
+         "allwinner,sun50i-r329-spi";
+   reg = <0x04026000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(16) 4>;
+   clocks = <&ccu 75>, <&ccu 73>;
+   clock-names = "ahb", "mod";
+   dmas = <&dma 23>, <&dma 23>;
+   dma-names = "rx", "tx";
+   resets = <&ccu 29>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+  };
+
+  usb_otg: usb@4100000 {
+   compatible = "allwinner,sun20i-d1-musb",
+         "allwinner,sun8i-a33-musb";
+   reg = <0x4100000 0x400>;
+   interrupts = <SOC_PERIPHERAL_IRQ(29) 4>;
+   interrupt-names = "mc";
+   clocks = <&ccu 103>;
+   resets = <&ccu 46>;
+   extcon = <&usbphy 0>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  usbphy: phy@4100400 {
+   compatible = "allwinner,sun20i-d1-usb-phy";
+   reg = <0x4100400 0x100>,
+         <0x4101800 0x100>,
+         <0x4200800 0x100>;
+   reg-names = "phy_ctrl",
+        "pmu0",
+        "pmu1";
+   clocks = <&dcxo>,
+     <&dcxo>;
+   clock-names = "usb0_phy",
+          "usb1_phy";
+   resets = <&ccu 40>,
+     <&ccu 41>;
+   reset-names = "usb0_reset",
+          "usb1_reset";
+   status = "disabled";
+   #phy-cells = <1>;
+  };
+
+  ehci0: usb@4101000 {
+   compatible = "allwinner,sun20i-d1-ehci",
+         "generic-ehci";
+   reg = <0x4101000 0x100>;
+   interrupts = <SOC_PERIPHERAL_IRQ(30) 4>;
+   clocks = <&ccu 99>,
+     <&ccu 101>,
+     <&ccu 97>;
+   resets = <&ccu 42>,
+     <&ccu 44>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ohci0: usb@4101400 {
+   compatible = "allwinner,sun20i-d1-ohci",
+         "generic-ohci";
+   reg = <0x4101400 0x100>;
+   interrupts = <SOC_PERIPHERAL_IRQ(31) 4>;
+   clocks = <&ccu 99>,
+     <&ccu 97>;
+   resets = <&ccu 42>;
+   phys = <&usbphy 0>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ehci1: usb@4200000 {
+   compatible = "allwinner,sun20i-d1-ehci",
+         "generic-ehci";
+   reg = <0x4200000 0x100>;
+   interrupts = <SOC_PERIPHERAL_IRQ(33) 4>;
+   clocks = <&ccu 100>,
+     <&ccu 102>,
+     <&ccu 98>;
+   resets = <&ccu 43>,
+     <&ccu 45>;
+   phys = <&usbphy 1>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  ohci1: usb@4200400 {
+   compatible = "allwinner,sun20i-d1-ohci",
+         "generic-ohci";
+   reg = <0x4200400 0x100>;
+   interrupts = <SOC_PERIPHERAL_IRQ(34) 4>;
+   clocks = <&ccu 100>,
+     <&ccu 98>;
+   resets = <&ccu 43>;
+   phys = <&usbphy 1>;
+   phy-names = "usb";
+   status = "disabled";
+  };
+
+  emac: ethernet@4500000 {
+   compatible = "allwinner,sun20i-d1-emac",
+         "allwinner,sun50i-a64-emac";
+   reg = <0x4500000 0x10000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(46) 4>;
+   interrupt-names = "macirq";
+   clocks = <&ccu 77>;
+   clock-names = "stmmaceth";
+   resets = <&ccu 30>;
+   reset-names = "stmmaceth";
+   syscon = <&syscon>;
+   status = "disabled";
+
+   mdio: mdio {
+    compatible = "snps,dwmac-mdio";
+    #address-cells = <1>;
+    #size-cells = <0>;
+   };
+  };
+
+  display_clocks: clock-controller@5000000 {
+   compatible = "allwinner,sun20i-d1-de2-clk",
+         "allwinner,sun50i-h5-de2-clk";
+   reg = <0x5000000 0x10000>;
+   clocks = <&ccu 28>, <&ccu 27>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 1>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  mixer0: mixer@5100000 {
+   compatible = "allwinner,sun20i-d1-de2-mixer-0";
+   reg = <0x5100000 0x100000>;
+   clocks = <&display_clocks 0>,
+     <&display_clocks 6>;
+   clock-names = "bus", "mod";
+   resets = <&display_clocks 0>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mixer0_out: port@1 {
+     reg = <1>;
+
+     mixer0_out_tcon_top_mixer0: endpoint {
+      remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+     };
+    };
+   };
+  };
+
+  mixer1: mixer@5200000 {
+   compatible = "allwinner,sun20i-d1-de2-mixer-1";
+   reg = <0x5200000 0x100000>;
+   clocks = <&display_clocks 1>,
+     <&display_clocks 7>;
+   clock-names = "bus", "mod";
+   resets = <&display_clocks 1>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mixer1_out: port@1 {
+     reg = <1>;
+
+     mixer1_out_tcon_top_mixer1: endpoint {
+      remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+     };
+    };
+   };
+  };
+
+  dsi: dsi@5450000 {
+   compatible = "allwinner,sun20i-d1-mipi-dsi",
+         "allwinner,sun50i-a100-mipi-dsi";
+   reg = <0x5450000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(92) 4>;
+   clocks = <&ccu 111>,
+     <&tcon_top 2>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 51>;
+   phys = <&dphy>;
+   phy-names = "dphy";
+   status = "disabled";
+
+   port {
+    dsi_in_tcon_lcd0: endpoint {
+     remote-endpoint = <&tcon_lcd0_out_dsi>;
+    };
+   };
+  };
+
+  dphy: phy@5451000 {
+   compatible = "allwinner,sun20i-d1-mipi-dphy",
+         "allwinner,sun50i-a100-mipi-dphy";
+   reg = <0x5451000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(92) 4>;
+   clocks = <&ccu 111>,
+     <&ccu 110>;
+   clock-names = "bus", "mod";
+   resets = <&ccu 51>;
+   #phy-cells = <0>;
+  };
+
+  tcon_top: tcon-top@5460000 {
+   compatible = "allwinner,sun20i-d1-tcon-top";
+   reg = <0x5460000 0x1000>;
+   clocks = <&ccu 105>,
+     <&ccu 114>,
+     <&ccu 116>,
+     <&ccu 112>;
+   clock-names = "bus", "tcon-tv0", "tve0", "dsi";
+   clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
+   resets = <&ccu 48>;
+   #clock-cells = <1>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_top_mixer0_in: port@0 {
+     reg = <0>;
+
+     tcon_top_mixer0_in_mixer0: endpoint {
+      remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+     };
+    };
+
+    tcon_top_mixer0_out: port@1 {
+     reg = <1>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
+     };
+
+     tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+      reg = <2>;
+      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+     };
+    };
+
+    tcon_top_mixer1_in: port@2 {
+     reg = <2>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer1_in_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
+     };
+    };
+
+    tcon_top_mixer1_out: port@3 {
+     reg = <3>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
+     };
+
+     tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+      reg = <2>;
+      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+     };
+    };
+
+    tcon_top_hdmi_in: port@4 {
+     reg = <4>;
+
+     tcon_top_hdmi_in_tcon_tv0: endpoint {
+      remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
+     };
+    };
+
+    tcon_top_hdmi_out: port@5 {
+     reg = <5>;
+    };
+   };
+  };
+
+  tcon_lcd0: lcd-controller@5461000 {
+   compatible = "allwinner,sun20i-d1-tcon-lcd";
+   reg = <0x5461000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(90) 4>;
+   clocks = <&ccu 113>,
+     <&ccu 112>;
+   clock-names = "ahb", "tcon-ch0";
+   clock-output-names = "tcon-pixel-clock";
+   resets = <&ccu 52>,
+     <&ccu 54>;
+   reset-names = "lcd", "lvds";
+   #clock-cells = <0>;
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_lcd0_in: port@0 {
+     reg = <0>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
+     };
+
+     tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
+     };
+    };
+
+    tcon_lcd0_out: port@1 {
+     reg = <1>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_lcd0_out_dsi: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&dsi_in_tcon_lcd0>;
+     };
+    };
+   };
+  };
+
+  tcon_tv0: lcd-controller@5470000 {
+   compatible = "allwinner,sun20i-d1-tcon-tv";
+   reg = <0x5470000 0x1000>;
+   interrupts = <SOC_PERIPHERAL_IRQ(91) 4>;
+   clocks = <&ccu 115>,
+     <&tcon_top 0>;
+   clock-names = "ahb", "tcon-ch1";
+   resets = <&ccu 53>;
+   reset-names = "lcd";
+
+   ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    tcon_tv0_in: port@0 {
+     reg = <0>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+
+     tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+      reg = <0>;
+      remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+     };
+
+     tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+      reg = <1>;
+      remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+     };
+    };
+
+    tcon_tv0_out: port@1 {
+     reg = <1>;
+
+     tcon_tv0_out_tcon_top_hdmi: endpoint {
+      remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+     };
+    };
+   };
+  };
+
+  ppu: power-controller@7001000 {
+   compatible = "allwinner,sun20i-d1-ppu";
+   reg = <0x7001000 0x1000>;
+   clocks = <&r_ccu 4>;
+   resets = <&r_ccu 2>;
+   #power-domain-cells = <1>;
+  };
+
+  r_ccu: clock-controller@7010000 {
+   compatible = "allwinner,sun20i-d1-r-ccu";
+   reg = <0x7010000 0x400>;
+   clocks = <&dcxo>,
+     <&rtc 0>,
+     <&rtc 2>,
+     <&ccu 6>;
+   clock-names = "hosc", "losc", "iosc", "pll-periph";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+  };
+
+  rtc: rtc@7090000 {
+   compatible = "allwinner,sun20i-d1-rtc",
+         "allwinner,sun50i-r329-rtc";
+   reg = <0x7090000 0x400>;
+   interrupts = <SOC_PERIPHERAL_IRQ(144) 4>;
+   clocks = <&r_ccu 7>,
+     <&dcxo>,
+     <&r_ccu 0>;
+   clock-names = "bus", "hosc", "ahb";
+   #clock-cells = <1>;
+  };
+ };
+};
diff --git a/ubuntu.24.04.pinctrl.txt b/ubuntu.24.04.pinctrl.txt
deleted file mode 100644
index 87ee6ed..0000000
--- a/ubuntu.24.04.pinctrl.txt
+++ /dev/null
@@ -1,90 +0,0 @@
-Pinmux settings per pin
-Format: pin (name): mux_owner|gpio_owner (strict) hog?
-pin 32 (PB0): device 2502800.i2c function i2c2 group PB0
-pin 33 (PB1): device 2502800.i2c function i2c2 group PB1
-pin 34 (PB2): UNCLAIMED
-pin 35 (PB3): UNCLAIMED
-pin 36 (PB4): UNCLAIMED
-pin 37 (PB5): UNCLAIMED
-pin 38 (PB6): UNCLAIMED
-pin 39 (PB7): UNCLAIMED
-pin 40 (PB8): device 2500000.serial function uart0 group PB8
-pin 41 (PB9): device 2500000.serial function uart0 group PB9
-pin 42 (PB10): UNCLAIMED
-pin 43 (PB11): UNCLAIMED
-pin 44 (PB12): UNCLAIMED
-pin 64 (PC0): device 2008000.led-controller function ledc group PC0
-pin 65 (PC1): UNCLAIMED
-pin 66 (PC2): device 4025000.spi function spi0 group PC2
-pin 67 (PC3): device 4025000.spi function spi0 group PC3
-pin 68 (PC4): device 4025000.spi function spi0 group PC4
-pin 69 (PC5): device 4025000.spi function spi0 group PC5
-pin 70 (PC6): device 4025000.spi function spi0 group PC6
-pin 71 (PC7): device 4025000.spi function spi0 group PC7
-pin 96 (PD0): UNCLAIMED
-pin 97 (PD1): UNCLAIMED
-pin 98 (PD2): UNCLAIMED
-pin 99 (PD3): UNCLAIMED
-pin 100 (PD4): UNCLAIMED
-pin 101 (PD5): UNCLAIMED
-pin 102 (PD6): UNCLAIMED
-pin 103 (PD7): UNCLAIMED
-pin 104 (PD8): UNCLAIMED
-pin 105 (PD9): UNCLAIMED
-pin 106 (PD10): device 4026000.spi function spi1 group PD10
-pin 107 (PD11): device 4026000.spi function spi1 group PD11
-pin 108 (PD12): device 4026000.spi function spi1 group PD12
-pin 109 (PD13): device 4026000.spi function spi1 group PD13
-pin 110 (PD14): device 4026000.spi function spi1 group PD14
-pin 111 (PD15): device 4026000.spi function spi1 group PD15
-pin 112 (PD16): device 2000c00.pwm function pwm0 group PD16
-pin 113 (PD17): UNCLAIMED
-pin 114 (PD18): UNCLAIMED
-pin 115 (PD19): GPIO 2000000.pinctrl:115
-pin 116 (PD20): GPIO 2000000.pinctrl:116
-pin 117 (PD21): GPIO 2000000.pinctrl:117
-pin 118 (PD22): UNCLAIMED
-pin 128 (PE0): UNCLAIMED
-pin 129 (PE1): UNCLAIMED
-pin 130 (PE2): UNCLAIMED
-pin 131 (PE3): UNCLAIMED
-pin 132 (PE4): UNCLAIMED
-pin 133 (PE5): UNCLAIMED
-pin 134 (PE6): UNCLAIMED
-pin 135 (PE7): UNCLAIMED
-pin 136 (PE8): UNCLAIMED
-pin 137 (PE9): UNCLAIMED
-pin 138 (PE10): UNCLAIMED
-pin 139 (PE11): UNCLAIMED
-pin 140 (PE12): UNCLAIMED
-pin 141 (PE13): UNCLAIMED
-pin 142 (PE14): UNCLAIMED
-pin 143 (PE15): UNCLAIMED
-pin 144 (PE16): UNCLAIMED
-pin 145 (PE17): UNCLAIMED
-pin 160 (PF0): device 4020000.mmc function mmc0 group PF0
-pin 161 (PF1): device 4020000.mmc function mmc0 group PF1
-pin 162 (PF2): device 4020000.mmc function mmc0 group PF2
-pin 163 (PF3): device 4020000.mmc function mmc0 group PF3
-pin 164 (PF4): device 4020000.mmc function mmc0 group PF4
-pin 165 (PF5): device 4020000.mmc function mmc0 group PF5
-pin 166 (PF6): GPIO 2000000.pinctrl:166
-pin 192 (PG0): device 4021000.mmc function mmc1 group PG0
-pin 193 (PG1): device 4021000.mmc function mmc1 group PG1
-pin 194 (PG2): device 4021000.mmc function mmc1 group PG2
-pin 195 (PG3): device 4021000.mmc function mmc1 group PG3
-pin 196 (PG4): device 4021000.mmc function mmc1 group PG4
-pin 197 (PG5): device 4021000.mmc function mmc1 group PG5
-pin 198 (PG6): device 2500400.serial function uart1 group PG6
-pin 199 (PG7): device 2500400.serial function uart1 group PG7
-pin 200 (PG8): device 2500400.serial function uart1 group PG8
-pin 201 (PG9): device 2500400.serial function uart1 group PG9
-pin 202 (PG10): UNCLAIMED
-pin 203 (PG11): UNCLAIMED
-pin 204 (PG12): GPIO 2000000.pinctrl:204
-pin 205 (PG13): UNCLAIMED
-pin 206 (PG14): UNCLAIMED
-pin 207 (PG15): UNCLAIMED
-pin 208 (PG16): UNCLAIMED
-pin 209 (PG17): UNCLAIMED
-pin 210 (PG18): UNCLAIMED
diff --git a/ubuntu.24.04.pins.txt b/ubuntu.24.04.pins.txt
deleted file mode 100644
index 5804734..0000000
--- a/ubuntu.24.04.pins.txt
+++ /dev/null
@@ -1,224 +0,0 @@
-pin:   0,  PA0,  input
-pin:   1,  PA1,  input
-pin:   2,  PA2,  input
-pin:   3,  PA3,  input
-pin:   4,  PA4,  input
-pin:   5,  PA5,  input
-pin:   6,  PA6,  input
-pin:   7,  PA7,  input
-pin:   8,  PA8,  input
-pin:   9,  PA9,  input
-pin:  10, PA10,  input
-pin:  11, PA11,  input
-pin:  12, PA12,  input
-pin:  13, PA13,  input
-pin:  14, PA14,  input
-pin:  15, PA15,  input
-pin:  16, PA16,  input
-pin:  17, PA17,  input
-pin:  18, PA18,  input
-pin:  19, PA19,  input
-pin:  20, PA20,  input
-pin:  21, PA21,  input
-pin:  22, PA22,  input
-pin:  23, PA23,  input
-pin:  24, PA24,  input
-pin:  25, PA25,  input
-pin:  26, PA26,  input
-pin:  27, PA27,  input
-pin:  28, PA28,  input
-pin:  29, PA29,  input
-pin:  30, PA30,  input
-pin:  31, PA31,  input
-pin:  32,  PB0,  input, name: pin5 [gpio2/twi2-sck], used by: kernel
-pin:  33,  PB1,  input, name: pin3 [gpio1/twi2-sda], used by: kernel
-pin:  34,  PB2,  input
-pin:  35,  PB3,  input, name: pin38 [gpio24/i2s2-din]
-pin:  36,  PB4,  input, name: pin40 [gpio25/i2s2-dout]
-pin:  37,  PB5,  input, name: pin12 [gpio7/i2s-clk]
-pin:  38,  PB6,  input, name: pin35 [gpio22/i2s2-lrck]
-pin:  39,  PB7,  input
-pin:  40,  PB8,  input, name: pin8 [gpio4/uart0-txd], used by: kernel
-pin:  41,  PB9,  input, name: pin10 [gpio5/uart0-rxd], used by: kernel
-pin:  42, PB10,  input
-pin:  43, PB11,  input
-pin:  44, PB12,  input, name: pin15 [gpio9]
-pin:  45, PB13,  input
-pin:  46, PB14,  input
-pin:  47, PB15,  input
-pin:  48, PB16,  input
-pin:  49, PB17,  input
-pin:  50, PB18,  input
-pin:  51, PB19,  input
-pin:  52, PB20,  input
-pin:  53, PB21,  input
-pin:  54, PB22,  input
-pin:  55, PB23,  input
-pin:  56, PB24,  input
-pin:  57, PB25,  input
-pin:  58, PB26,  input
-pin:  59, PB27,  input
-pin:  60, PB28,  input
-pin:  61, PB29,  input
-pin:  62, PB30,  input
-pin:  63, PB31,  input
-pin:  64,  PC0,  input, used by: kernel
-pin:  65,  PC1,  input
-pin:  66,  PC2,  input, name: pin31 [gpio21], used by: kernel
-pin:  67,  PC3,  input, used by: kernel
-pin:  68,  PC4,  input, used by: kernel
-pin:  69,  PC5,  input, used by: kernel
-pin:  70,  PC6,  input, used by: kernel
-pin:  71,  PC7,  input, used by: kernel
-pin:  72,  PC8,  input
-pin:  73,  PC9,  input
-pin:  74, PC10,  input
-pin:  75, PC11,  input
-pin:  76, PC12,  input
-pin:  77, PC13,  input
-pin:  78, PC14,  input
-pin:  79, PC15,  input
-pin:  80, PC16,  input
-pin:  81, PC17,  input
-pin:  82, PC18,  input
-pin:  83, PC19,  input
-pin:  84, PC20,  input
-pin:  85, PC21,  input
-pin:  86, PC22,  input
-pin:  87, PC23,  input
-pin:  88, PC24,  input
-pin:  89, PC25,  input
-pin:  90, PC26,  input
-pin:  91, PC27,  input
-pin:  92, PC28,  input
-pin:  93, PC29,  input
-pin:  94, PC30,  input
-pin:  95, PC31,  input
-pin:  96,  PD0,  input
-pin:  97,  PD1,  input
-pin:  98,  PD2,  input
-pin:  99,  PD3,  input
-pin: 100,  PD4,  input
-pin: 101,  PD5,  input
-pin: 102,  PD6,  input
-pin: 103,  PD7,  input
-pin: 104,  PD8,  input
-pin: 105,  PD9,  input
-pin: 106, PD10,  input, used by: kernel
-pin: 107, PD11,  input, name: pin24 [gpio16/spi1-ce0], used by: kernel
-pin: 108, PD12,  input, name: pin23 [gpio15/spi1-clk], used by: kernel
-pin: 109, PD13,  input, name: pin19 [gpio12/spi1-mosi], used by: kernel
-pin: 110, PD14,  input, name: pin21 [gpio13/spi1-miso], used by: kernel
-pin: 111, PD15,  input, name: pin27 [gpio18/spi1-hold], used by: kernel
-pin: 112, PD16,  input, name: pin29 [gpio20/spi1-wp], used by: kernel
-pin: 113, PD17,  input
-pin: 114, PD18,  input
-pin: 115, PD19, output, used by: usbvbus
-pin: 116, PD20,  input, used by: usb0_vbus_det
-pin: 117, PD21,  input, used by: usb0_id_det
-pin: 118, PD22,  input
-pin: 119, PD23,  input, name: pin7 [gpio3/pwm]
-pin: 120, PD24,  input
-pin: 121, PD25,  input
-pin: 122, PD26,  input
-pin: 123, PD27,  input
-pin: 124, PD28,  input
-pin: 125, PD29,  input
-pin: 126, PD30,  input
-pin: 127, PD31,  input
-pin: 128,  PE0,  input
-pin: 129,  PE1,  input
-pin: 130,  PE2,  input
-pin: 131,  PE3,  input
-pin: 132,  PE4,  input
-pin: 133,  PE5,  input
-pin: 134,  PE6,  input
-pin: 135,  PE7,  input
-pin: 136,  PE8,  input
-pin: 137,  PE9,  input
-pin: 138, PE10,  input
-pin: 139, PE11,  input
-pin: 140, PE12,  input
-pin: 141, PE13,  input
-pin: 142, PE14,  input
-pin: 143, PE15,  input
-pin: 144, PE16,  input
-pin: 145, PE17,  input
-pin: 146, PE18,  input
-pin: 147, PE19,  input
-pin: 148, PE20,  input
-pin: 149, PE21,  input
-pin: 150, PE22,  input
-pin: 151, PE23,  input
-pin: 152, PE24,  input
-pin: 153, PE25,  input
-pin: 154, PE26,  input
-pin: 155, PE27,  input
-pin: 156, PE28,  input
-pin: 157, PE29,  input
-pin: 158, PE30,  input
-pin: 159, PE31,  input
-pin: 160,  PF0,  input, used by: kernel
-pin: 161,  PF1,  input, used by: kernel
-pin: 162,  PF2,  input, used by: kernel
-pin: 163,  PF3,  input, used by: kernel
-pin: 164,  PF4,  input, used by: kernel
-pin: 165,  PF5,  input, used by: kernel
-pin: 166,  PF6,  input, used by: cd
-pin: 167,  PF7,  input
-pin: 168,  PF8,  input
-pin: 169,  PF9,  input
-pin: 170, PF10,  input
-pin: 171, PF11,  input
-pin: 172, PF12,  input
-pin: 173, PF13,  input
-pin: 174, PF14,  input
-pin: 175, PF15,  input
-pin: 176, PF16,  input
-pin: 177, PF17,  input
-pin: 178, PF18,  input
-pin: 179, PF19,  input
-pin: 180, PF20,  input
-pin: 181, PF21,  input
-pin: 182, PF22,  input
-pin: 183, PF23,  input
-pin: 184, PF24,  input
-pin: 185, PF25,  input
-pin: 186, PF26,  input
-pin: 187, PF27,  input
-pin: 188, PF28,  input
-pin: 189, PF29,  input
-pin: 190, PF30,  input
-pin: 191, PF31,  input
-pin: 192,  PG0,  input, used by: kernel
-pin: 193,  PG1,  input, used by: kernel
-pin: 194,  PG2,  input, used by: kernel
-pin: 195,  PG3,  input, used by: kernel
-pin: 196,  PG4,  input, used by: kernel
-pin: 197,  PG5,  input, used by: kernel
-pin: 198,  PG6,  input, used by: kernel
-pin: 199,  PG7,  input, used by: kernel
-pin: 200,  PG8,  input, used by: kernel
-pin: 201,  PG9,  input, used by: kernel
-pin: 202, PG10,  input
-pin: 203, PG11,  input
-pin: 204, PG12, output, used by: reset
-pin: 205, PG13,  input
-pin: 206, PG14,  input
-pin: 207, PG15,  input
-pin: 208, PG16,  input
-pin: 209, PG17,  input
-pin: 210, PG18,  input
-pin: 211, PG19,  input
-pin: 212, PG20,  input
-pin: 213, PG21,  input
-pin: 214, PG22,  input
-pin: 215, PG23,  input
-pin: 216, PG24,  input
-pin: 217, PG25,  input
-pin: 218, PG26,  input
-pin: 219, PG27,  input
-pin: 220, PG28,  input
-pin: 221, PG29,  input
-pin: 222, PG30,  input
-pin: 223, PG31,  input