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easytarget-MQ-Pro-IO/device-tree/sun20i-d1.dtsi
Owen 2626267ec5 precompiled stuff
2024-05-06 14:00:47 +00:00

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/clock/sun20i-d1-ccu.h>
#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun20i-d1-ccu.h>
#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
timebase-frequency = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
clocks = <&ccu CLK_RISCV>;
clock-frequency = <24000000>;
d-cache-block-size = <64>;
d-cache-sets = <256>;
d-cache-size = <32768>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
#cooling-cells = <2>;
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
de: display-engine {
compatible = "allwinner,sun20i-d1-display-engine";
allwinner,pipelines = <&mixer0>, <&mixer1>;
status = "disabled";
};
osc24M: osc24M-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
#clock-cells = <0>;
};
thermal-zones {
cpu-thermal {
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&ths>;
trips {
cpu_target: cpu-target {
hysteresis = <3000>;
temperature = <85000>;
type = "passive";
};
cpu-crit {
hysteresis = <0>;
temperature = <110000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_target>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
soc {
compatible = "simple-bus";
ranges;
interrupt-parent = <&plic>;
dma-noncoherent;
#address-cells = <1>;
#size-cells = <1>;
dsp_wdt: watchdog@1700400 {
compatible = "allwinner,sun20i-d1-wdt";
reg = <0x1700400 0x20>;
interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
status = "reserved";
};
pio: pinctrl@2000000 {
compatible = "allwinner,sun20i-d1-pinctrl";
reg = <0x2000000 0x800>;
interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
<87 IRQ_TYPE_LEVEL_HIGH>,
<89 IRQ_TYPE_LEVEL_HIGH>,
<91 IRQ_TYPE_LEVEL_HIGH>,
<93 IRQ_TYPE_LEVEL_HIGH>,
<95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB0>,
<&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#gpio-cells = <3>;
#interrupt-cells = <3>;
/omit-if-no-ref/
dsi_4lane_pins: dsi-4lane-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
"PD6", "PD7", "PD8", "PD9";
drive-strength = <30>;
function = "dsi";
};
/omit-if-no-ref/
i2c0_pg12_pins: i2c0-pg12-pins {
pins = "PG12", "PG13";
function = "i2c0";
};
/omit-if-no-ref/
i2c1_pb4_pins: i2c1-pb4-pins {
pins = "PB4", "PB5";
function = "i2c1";
};
/omit-if-no-ref/
i2c2_pc0_pins: i2c2-pc0-pins {
pins = "PC0", "PC1";
function = "i2c2";
};
/omit-if-no-ref/
i2c3_pe16_pins: i2c3-pe16-pins {
pins = "PE16", "PE17";
function = "i2c3";
};
/omit-if-no-ref/
lcd_rgb666_pins: lcd-rgb666-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
"PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
"PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
"PD18", "PD19", "PD20", "PD21";
function = "lcd0";
};
/omit-if-no-ref/
ledc_pc0_pin: ledc-pc0-pin {
pins = "PC0";
function = "ledc";
};
/omit-if-no-ref/
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
function = "mmc0";
};
/omit-if-no-ref/
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
function = "mmc1";
};
/omit-if-no-ref/
mmc2_pins: mmc2-pins {
pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
function = "mmc2";
};
/omit-if-no-ref/
rgmii_pe_pins: rgmii-pe-pins {
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
"PE5", "PE6", "PE7", "PE8", "PE9",
"PE11", "PE12", "PE13", "PE14", "PE15";
function = "emac";
};
/omit-if-no-ref/
rmii_pe_pins: rmii-pe-pins {
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
"PE5", "PE6", "PE7", "PE8", "PE9";
function = "emac";
};
/omit-if-no-ref/
pwm0_pb5_pin: pwm0-pb5-pin {
pins = "PB5";
function = "pwm0";
};
/omit-if-no-ref/
pwm0_pb12_pin: pwm0-pb12-pin {
pins = "PB12";
function = "pwm0";
};
/omit-if-no-ref/
pwm0_pd16_pin: pwm0-pd16-pin {
pins = "PD16";
function = "pwm0";
};
/omit-if-no-ref/
pwm2_pd18_pin: pwm2-pd18-pin {
pins = "PD18";
function = "pwm2";
};
/omit-if-no-ref/
pwm4_pd20_pin: pwm4-pd20-pin {
pins = "PD20";
function = "pwm4";
};
/omit-if-no-ref/
pwm7_pd22_pin: pwm7-pd22-pin {
pins = "PD22";
function = "pwm7";
};
/omit-if-no-ref/
spi0_pins: spi0-pins {
pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
function = "spi0";
};
/omit-if-no-ref/
spi1_pb_pins: spi1-pb-pins {
pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12";
function = "spi1";
};
/omit-if-no-ref/
spi1_pd_pins: spi1-pd-pins {
pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15";
function = "spi1";
};
/omit-if-no-ref/
uart0_pb8_pins: uart0-pb8-pins {
pins = "PB8", "PB9";
function = "uart0";
};
/omit-if-no-ref/
uart1_pg6_pins: uart1-pg6-pins {
pins = "PG6", "PG7";
function = "uart1";
};
/omit-if-no-ref/
uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
pins = "PG8", "PG9";
function = "uart1";
};
/omit-if-no-ref/
uart2_pb0_pins: uart2-pb0-pins {
pins = "PB0", "PB1";
function = "uart2";
};
/omit-if-no-ref/
uart2_pc0_pins: uart2-pc0-pins {
pins = "PC0", "PC1";
function = "uart2";
};
/omit-if-no-ref/
uart3_pd10_pins: uart3-pd10-pins {
pins = "PD10", "PD11";
function = "uart3";
};
/omit-if-no-ref/
uart3_pd13_rts_cts_pins: uart3-pd13-rts-cts-pins {
pins = "PD13", "PD14";
function = "uart3";
};
/omit-if-no-ref/
uart4_pb2_pins: uart4-pb2-pins {
pins = "PB2", "PB3";
function = "uart4";
};
/omit-if-no-ref/
uart5_pb4_pins: uart5-pb4-pins {
pins = "PB4", "PB5";
function = "uart5";
};
};
pwm: pwm@2000c00 {
compatible = "allwinner,sun20i-d1-pwm";
reg = <0x2000c00 0x400>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PWM>, <&osc24M>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_PWM>;
status = "disabled";
#pwm-cells = <3>;
};
ccu: clock-controller@2001000 {
compatible = "allwinner,sun20i-d1-ccu";
reg = <0x2001000 0x1000>;
clocks = <&osc24M>,
<&rtc CLK_OSC32K>,
<&rtc CLK_IOSC>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
ledc: led-controller@2008000 {
compatible = "allwinner,sun20i-d1-ledc",
"allwinner,sun50i-a100-ledc";
reg = <0x2008000 0x400>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_LEDC>;
dmas = <&dma 42>;
dma-names = "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
ths: temperature-sensor@2009400 {
compatible = "allwinner,sun20i-d1-ths";
reg = <0x2009400 0x400>;
interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_THS>, <&osc24M>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_THS>;
nvmem-cells = <&ths_calib>;
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <0>;
};
lradc: keys@2009800 {
compatible = "allwinner,sun20i-d1-lradc",
"allwinner,sun50i-r329-lradc";
reg = <0x2009800 0x400>;
interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_LRADC>;
resets = <&ccu RST_BUS_LRADC>;
status = "disabled";
};
iommu: iommu@2010000 {
compatible = "allwinner,sun20i-d1-iommu";
reg = <0x2010000 0x10000>;
interrupts = <80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_IOMMU>;
#iommu-cells = <1>;
};
codec: audio-codec@2030000 {
compatible = "allwinner,sun20i-d1-codec", "simple-mfd", "syscon";
reg = <0x2030000 0x1000>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_AUDIO>,
<&ccu CLK_AUDIO_ADC>,
<&ccu CLK_AUDIO_DAC>,
<&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "bus", "adc", "dac", "hosc", "losc";
resets = <&ccu RST_BUS_AUDIO>;
dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <1>;
#sound-dai-cells = <0>;
regulators@2030348 {
compatible = "allwinner,sun20i-d1-analog-ldos";
reg = <0x2030348 0x4>;
nvmem-cells = <&bg_trim>;
nvmem-cell-names = "bg_trim";
reg_aldo: aldo {
};
reg_hpldo: hpldo {
};
};
};
dmic: dmic@2031000 {
compatible = "allwinner,sun20i-d1-dmic",
"allwinner,sun50i-h6-dmic";
reg = <0x2031000 0x400>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMIC>,
<&ccu CLK_DMIC>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_DMIC>;
dmas = <&dma 8>;
dma-names = "rx";
status = "disabled";
#sound-dai-cells = <0>;
};
i2s0: i2s@2032000 {
compatible = "allwinner,sun20i-d1-i2s",
"allwinner,sun50i-r329-i2s";
reg = <0x2032000 0x1000>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S0>,
<&ccu CLK_I2S0>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S0>;
dmas = <&dma 3>, <&dma 3>;
dma-names = "rx", "tx";
status = "disabled";
#sound-dai-cells = <0>;
};
i2s1: i2s@2033000 {
compatible = "allwinner,sun20i-d1-i2s",
"allwinner,sun50i-r329-i2s";
reg = <0x2033000 0x1000>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S1>,
<&ccu CLK_I2S1>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S1>;
dmas = <&dma 4>, <&dma 4>;
dma-names = "rx", "tx";
status = "disabled";
#sound-dai-cells = <0>;
};
// TODO: how to integrate ASRC? same or separate node?
i2s2: i2s@2034000 {
compatible = "allwinner,sun20i-d1-i2s",
"allwinner,sun50i-r329-i2s";
reg = <0x2034000 0x1000>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S2>,
<&ccu CLK_I2S2>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S2>;
dmas = <&dma 5>, <&dma 5>;
dma-names = "rx", "tx";
status = "disabled";
#sound-dai-cells = <0>;
};
// TODO: add receive functionality
spdif: spdif@2036000 {
compatible = "allwinner,sun20i-d1-spdif";
reg = <0x2036000 0x400>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPDIF>,
<&ccu CLK_SPDIF_RX>,
<&ccu CLK_SPDIF_TX>;
clock-names = "apb", "rx", "tx";
resets = <&ccu RST_BUS_SPDIF>;
dmas = <&dma 2>, <&dma 2>;
dma-names = "rx", "tx";
status = "disabled";
#sound-dai-cells = <0>;
};
timer: timer@2050000 {
compatible = "allwinner,sun20i-d1-timer",
"allwinner,sun8i-a23-timer";
reg = <0x2050000 0xa0>;
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
<76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
wdt: watchdog@20500a0 {
compatible = "allwinner,sun20i-d1-wdt-reset",
"allwinner,sun20i-d1-wdt";
reg = <0x20500a0 0x20>;
interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
status = "reserved";
};
uart0: serial@2500000 {
compatible = "snps,dw-apb-uart";
reg = <0x2500000 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
dmas = <&dma 14>, <&dma 14>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@2500400 {
compatible = "snps,dw-apb-uart";
reg = <0x2500400 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
dmas = <&dma 15>, <&dma 15>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@2500800 {
compatible = "snps,dw-apb-uart";
reg = <0x2500800 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
dmas = <&dma 16>, <&dma 16>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@2500c00 {
compatible = "snps,dw-apb-uart";
reg = <0x2500c00 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>;
dmas = <&dma 17>, <&dma 17>;
dma-names = "rx", "tx";
status = "disabled";
};
uart4: serial@2501000 {
compatible = "snps,dw-apb-uart";
reg = <0x2501000 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART4>;
resets = <&ccu RST_BUS_UART4>;
dmas = <&dma 18>, <&dma 18>;
dma-names = "rx", "tx";
status = "disabled";
};
uart5: serial@2501400 {
compatible = "snps,dw-apb-uart";
reg = <0x2501400 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART5>;
resets = <&ccu RST_BUS_UART5>;
dmas = <&dma 19>, <&dma 19>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c0: i2c@2502000 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502000 0x400>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
dmas = <&dma 43>, <&dma 43>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@2502400 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502400 0x400>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
dmas = <&dma 44>, <&dma 44>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@2502800 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502800 0x400>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
dmas = <&dma 45>, <&dma 45>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@2502c00 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502c00 0x400>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
dmas = <&dma 46>, <&dma 46>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
syscon: syscon@3000000 {
compatible = "allwinner,sun20i-d1-system-control";
reg = <0x3000000 0x1000>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
regulators@3000150 {
compatible = "allwinner,sun20i-d1-system-ldos";
reg = <0x3000150 0x4>;
reg_ldoa: ldoa {
};
reg_ldob: ldob {
};
};
};
dma: dma-controller@3002000 {
compatible = "allwinner,sun20i-d1-dma";
reg = <0x3002000 0x1000>;
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
clock-names = "bus", "mbus";
resets = <&ccu RST_BUS_DMA>;
dma-channels = <16>;
dma-requests = <48>;
#dma-cells = <1>;
};
sid: efuse@3006000 {
compatible = "allwinner,sun20i-d1-sid";
reg = <0x3006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ths_calib: ths-calib@14 {
reg = <0x14 0x4>;
};
bg_trim: bg-trim@28 {
reg = <0x28 0x4>;
bits = <16 8>;
};
};
crypto: crypto@3040000 {
compatible = "allwinner,sun20i-d1-crypto";
reg = <0x3040000 0x800>;
interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>,
<&ccu CLK_CE>,
<&ccu CLK_MBUS_CE>,
<&rtc CLK_IOSC>;
clock-names = "bus", "mod", "ram", "trng";
resets = <&ccu RST_BUS_CE>;
};
mbus: dram-controller@3102000 {
compatible = "allwinner,sun20i-d1-mbus";
reg = <0x3102000 0x1000>,
<0x3103000 0x1000>;
reg-names = "mbus", "dram";
interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_MBUS>,
<&ccu CLK_DRAM>,
<&ccu CLK_BUS_DRAM>;
clock-names = "mbus", "dram", "bus";
dma-ranges = <0 0x40000000 0x80000000>;
#address-cells = <1>;
#size-cells = <1>;
#interconnect-cells = <1>;
};
mmc0: mmc@4020000 {
compatible = "allwinner,sun20i-d1-mmc";
reg = <0x4020000 0x1000>;
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
cap-sd-highspeed;
max-frequency = <150000000>;
no-mmc;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@4021000 {
compatible = "allwinner,sun20i-d1-mmc";
reg = <0x4021000 0x1000>;
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
cap-sd-highspeed;
max-frequency = <150000000>;
no-mmc;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@4022000 {
compatible = "allwinner,sun20i-d1-emmc",
"allwinner,sun50i-a100-emmc";
reg = <0x4022000 0x1000>;
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
cap-mmc-highspeed;
max-frequency = <150000000>;
mmc-ddr-1_8v;
mmc-ddr-3_3v;
no-sd;
no-sdio;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi0: spi@4025000 {
compatible = "allwinner,sun20i-d1-spi",
"allwinner,sun50i-r329-spi";
reg = <0x4025000 0x1000>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_SPI0>;
dmas = <&dma 22>, <&dma 22>;
dma-names = "rx", "tx";
num-cs = <1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@4026000 {
compatible = "allwinner,sun20i-d1-spi-dbi",
"allwinner,sun50i-r329-spi-dbi",
"allwinner,sun50i-r329-spi";
reg = <0x4026000 0x1000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_SPI1>;
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
num-cs = <1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usb_otg: usb@4100000 {
compatible = "allwinner,sun20i-d1-musb",
"allwinner,sun8i-a33-musb";
reg = <0x4100000 0x400>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
extcon = <&usbphy 0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
usbphy: phy@4100400 {
compatible = "allwinner,sun20i-d1-usb-phy";
reg = <0x4100400 0x100>,
<0x4101800 0x100>,
<0x4200800 0x100>;
reg-names = "phy_ctrl",
"pmu0",
"pmu1";
clocks = <&osc24M>,
<&osc24M>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci0: usb@4101000 {
compatible = "allwinner,sun20i-d1-ehci",
"generic-ehci";
reg = <0x4101000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_BUS_EHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>,
<&ccu RST_BUS_EHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ohci0: usb@4101400 {
compatible = "allwinner,sun20i-d1-ohci",
"generic-ohci";
reg = <0x4101400 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ehci1: usb@4200000 {
compatible = "allwinner,sun20i-d1-ehci",
"generic-ehci";
reg = <0x4200000 0x100>;
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_BUS_EHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>,
<&ccu RST_BUS_EHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci1: usb@4200400 {
compatible = "allwinner,sun20i-d1-ohci",
"generic-ohci";
reg = <0x4200400 0x100>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
emac: ethernet@4500000 {
compatible = "allwinner,sun20i-d1-emac",
"allwinner,sun50i-a64-emac";
reg = <0x4500000 0x10000>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
syscon = <&syscon>;
status = "disabled";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
display_clocks: clock-controller@5000000 {
compatible = "allwinner,sun20i-d1-de2-clk",
"allwinner,sun50i-h5-de2-clk";
reg = <0x5000000 0x10000>;
clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
mixer0: mixer@5100000 {
compatible = "allwinner,sun20i-d1-de2-mixer-0";
reg = <0x5100000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER0>,
<&display_clocks CLK_MIXER0>;
clock-names = "bus", "mod";
resets = <&display_clocks RST_MIXER0>;
iommus = <&iommu 2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer0_out: port@1 {
reg = <1>;
mixer0_out_tcon_top_mixer0: endpoint {
remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
};
};
};
};
mixer1: mixer@5200000 {
compatible = "allwinner,sun20i-d1-de2-mixer-1";
reg = <0x5200000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER1>,
<&display_clocks CLK_MIXER1>;
clock-names = "bus", "mod";
resets = <&display_clocks RST_MIXER1>;
iommus = <&iommu 2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer1_out: port@1 {
reg = <1>;
mixer1_out_tcon_top_mixer1: endpoint {
remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
};
};
};
};
dsi: dsi@5450000 {
compatible = "allwinner,sun20i-d1-mipi-dsi",
"allwinner,sun50i-a100-mipi-dsi";
reg = <0x5450000 0x1000>;
interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&tcon_top CLK_TCON_TOP_DSI>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
phys = <&dphy>;
phy-names = "dphy";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
port {
dsi_in_tcon_lcd0: endpoint {
remote-endpoint = <&tcon_lcd0_out_dsi>;
};
};
};
dphy: phy@5451000 {
compatible = "allwinner,sun20i-d1-mipi-dphy",
"allwinner,sun50i-a100-mipi-dphy";
reg = <0x5451000 0x1000>;
interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_MIPI_DSI>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
#phy-cells = <0>;
};
tcon_top: tcon-top@5460000 {
compatible = "allwinner,sun20i-d1-tcon-top";
reg = <0x5460000 0x1000>;
clocks = <&ccu CLK_BUS_DPSS_TOP>,
<&ccu CLK_TCON_TV>,
<&ccu CLK_TVE>,
<&ccu CLK_TCON_LCD0>;
clock-names = "bus", "tcon-tv0", "tve0", "dsi";
clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
resets = <&ccu RST_BUS_DPSS_TOP>;
#clock-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer0_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer0_in_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
};
};
tcon_top_mixer0_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
};
tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
reg = <2>;
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
};
};
tcon_top_mixer1_in: port@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer1_in_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
};
};
tcon_top_mixer1_out: port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
};
tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
reg = <2>;
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
};
};
tcon_top_hdmi_in: port@4 {
reg = <4>;
tcon_top_hdmi_in_tcon_tv0: endpoint {
remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
};
};
tcon_top_hdmi_out: port@5 {
reg = <5>;
tcon_top_hdmi_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_tcon_top>;
};
};
};
};
tcon_lcd0: lcd-controller@5461000 {
compatible = "allwinner,sun20i-d1-tcon-lcd";
reg = <0x5461000 0x1000>;
interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON_LCD0>,
<&ccu CLK_TCON_LCD0>;
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-pixel-clock";
resets = <&ccu RST_BUS_TCON_LCD0>,
<&ccu RST_BUS_LVDS0>;
reset-names = "lcd", "lvds";
phys = <&dphy>;
phy-names = "lvds0";
#clock-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
};
tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
};
};
tcon_lcd0_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_out_dsi: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in_tcon_lcd0>;
};
};
};
};
tcon_tv0: lcd-controller@5470000 {
compatible = "allwinner,sun20i-d1-tcon-tv";
reg = <0x5470000 0x1000>;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON_TV>,
<&tcon_top CLK_TCON_TOP_TV0>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV>;
reset-names = "lcd";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_tv0_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
};
tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
};
};
tcon_tv0_out: port@1 {
reg = <1>;
tcon_tv0_out_tcon_top_hdmi: endpoint {
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
};
};
};
};
hdmi: hdmi@5500000 {
compatible = "allwinner,sun20i-d1-dw-hdmi";
reg = <0x5500000 0x10000>;
reg-io-width = <1>;
interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>,
<&ccu CLK_HDMI_24M>,
<&ccu CLK_HDMI_CEC>;
clock-names = "iahb", "isfr", "cec";
resets = <&ccu RST_BUS_HDMI_SUB>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
phy-names = "phy";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in_tcon_top: endpoint {
remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
};
};
hdmi_out: port@1 {
reg = <1>;
};
};
};
hdmi_phy: phy@5510000 {
compatible = "allwinner,sun20i-d1-hdmi-phy";
reg = <0x5510000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_24M>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_HDMI_MAIN>;
reset-names = "phy";
status = "disabled";
#phy-cells = <0>;
};
riscv_wdt: watchdog@6011000 {
compatible = "allwinner,sun20i-d1-wdt";
reg = <0x6011000 0x20>;
interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
};
r_ccu: clock-controller@7010000 {
compatible = "allwinner,sun20i-d1-r-ccu";
reg = <0x7010000 0x400>;
clocks = <&osc24M>,
<&rtc CLK_OSC32K>,
<&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0_DIV3>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
};
rtc: rtc@7090000 {
compatible = "allwinner,sun20i-d1-rtc",
"allwinner,sun50i-r329-rtc";
reg = <0x7090000 0x400>;
interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_BUS_R_RTC>,
<&osc24M>,
<&r_ccu CLK_R_AHB>;
clock-names = "bus", "hosc", "ahb";
#clock-cells = <1>;
};
plic: interrupt-controller@10000000 {
compatible = "allwinner,sun20i-d1-plic",
"thead,c900-plic";
reg = <0x10000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>,
<&cpu0_intc 9>;
interrupt-controller;
riscv,ndev = <176>;
#address-cells = <0>;
#interrupt-cells = <2>;
};
};
};
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