random-mirrors/opensbi
1
0
Fork 0
mirror of https://github.com/riscv-software-src/opensbi synced 2025-11-15 19:30:40 +00:00
Code Issues Packages Projects Releases Wiki Activity
778 Commits 3 Branches 19 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Vijai Kumar K
0d49c3bc18 lib: utils: Fix shakti uart implementation 
Fix uart_putc implementation.
Due to a bug in the IP, this went unnoticed.
Use macros instead of magic numbers to make the code
more readable.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
 2021-01-07 10:18:23 +05:30
Vijai Kumar K
db56ef367c platform: Add support for Shakti C-class SoC from IIT-M 
C-Class is a member of the SHAKTI family of processors from Indian
Institute of Technology - Madras(IIT-M).
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md

We add OpenSBI support for Shakti C-class SoC.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
 2020-06-19 09:21:46 +05:30