mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-06 15:00:26 +00:00
e8dfa55f3d
The Ariane framework has a generic PMU that is not used by OpenSBI. Due to OpenSBI’s build system we cannot directly reuse the generic platform functions, so move the Ariane platform to generic. Also due to the generic platform is where new features are added. Signed-off-by: Manuel Hernández Méndez <maherme.dev@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251023090347.30746-1-maherme.dev@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
138 lines
3.3 KiB
C
138 lines
3.3 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2019 FORTH-ICS/CARV
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* Panagiotis Peristerakis <perister@ics.forth.gr>
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*/
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#include <platform_override.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/ipi/aclint_mswi.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/timer/aclint_mtimer.h>
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#define ARIANE_UART_ADDR 0x10000000
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#define ARIANE_UART_FREQ 50000000
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#define ARIANE_UART_BAUDRATE 115200
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#define ARIANE_UART_REG_SHIFT 2
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#define ARIANE_UART_REG_WIDTH 4
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#define ARIANE_UART_REG_OFFSET 0
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#define ARIANE_UART_CAPS 0
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#define ARIANE_PLIC_ADDR 0xc000000
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#define ARIANE_PLIC_SIZE (0x200000 + \
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(ARIANE_HART_COUNT * 0x1000))
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#define ARIANE_PLIC_NUM_SOURCES 3
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#define ARIANE_HART_COUNT 1
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#define ARIANE_CLINT_ADDR 0x2000000
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#define ARIANE_ACLINT_MTIMER_FREQ 1000000
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#define ARIANE_ACLINT_MSWI_ADDR (ARIANE_CLINT_ADDR + \
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CLINT_MSWI_OFFSET)
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#define ARIANE_ACLINT_MTIMER_ADDR (ARIANE_CLINT_ADDR + \
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CLINT_MTIMER_OFFSET)
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static struct plic_data plic = {
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.addr = ARIANE_PLIC_ADDR,
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.size = ARIANE_PLIC_SIZE,
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.num_src = ARIANE_PLIC_NUM_SOURCES,
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.flags = PLIC_FLAG_ARIANE_BUG,
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.context_map = {
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[0] = { 0, 1 },
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},
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};
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static struct aclint_mswi_data mswi = {
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.addr = ARIANE_ACLINT_MSWI_ADDR,
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.size = ACLINT_MSWI_SIZE,
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.first_hartid = 0,
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.hart_count = ARIANE_HART_COUNT,
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};
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static struct aclint_mtimer_data mtimer = {
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.mtime_freq = ARIANE_ACLINT_MTIMER_FREQ,
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.mtime_addr = ARIANE_ACLINT_MTIMER_ADDR +
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ACLINT_DEFAULT_MTIME_OFFSET,
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.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
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.mtimecmp_addr = ARIANE_ACLINT_MTIMER_ADDR +
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ACLINT_DEFAULT_MTIMECMP_OFFSET,
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.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
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.first_hartid = 0,
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.hart_count = ARIANE_HART_COUNT,
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.has_64bit_mmio = true,
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};
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/*
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* Ariane platform early initialization.
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*/
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static int ariane_early_init(bool cold_boot)
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{
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int rc;
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if (!cold_boot)
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return 0;
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rc = uart8250_init(ARIANE_UART_ADDR,
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ARIANE_UART_FREQ,
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ARIANE_UART_BAUDRATE,
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ARIANE_UART_REG_SHIFT,
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ARIANE_UART_REG_WIDTH,
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ARIANE_UART_REG_OFFSET,
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ARIANE_UART_CAPS);
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if (rc)
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return rc;
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return aclint_mswi_cold_init(&mswi);
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}
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/*
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* Ariane platform final initialization.
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*/
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static int ariane_final_init(bool cold_boot)
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{
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt = fdt_get_address_rw();
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fdt_fixups(fdt);
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return 0;
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}
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/*
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* Initialize the ariane interrupt controller during cold boot.
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*/
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static int ariane_irqchip_init(void)
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{
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return plic_cold_irqchip_init(&plic);
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}
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/*
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* Initialize ariane timer during cold boot.
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*/
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static int ariane_timer_init(void)
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{
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return aclint_mtimer_cold_init(&mtimer, NULL);
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}
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static int openhwgroup_ariane_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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generic_platform_ops.early_init = ariane_early_init;
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generic_platform_ops.timer_init = ariane_timer_init;
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generic_platform_ops.irqchip_init = ariane_irqchip_init;
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generic_platform_ops.final_init = ariane_final_init;
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return 0;
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}
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static const struct fdt_match openhwgroup_ariane_match[] = {
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{ .compatible = "eth,ariane-bare-dev" },
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{ },
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};
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const struct fdt_driver openhwgroup_ariane = {
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.match_table = openhwgroup_ariane_match,
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.init = openhwgroup_ariane_platform_init,
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};
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