mirror of
https://github.com/riscv-software-src/opensbi
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1f84ec2ac2
Add initial platform support for the SpacemiT K1 SoC, including early/final init hooks, cold boot handling, and CCI-550 snoop/DVM enablement. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/all/15169E392597D319+aOcKujCl8mz4XK4L@kernel.org/ [1] Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-1-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 SpacemiT
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* Authors:
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* Xianbin Zhu <xianbin.zhu@linux.spacemit.com>
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* Troy Mitchell <troy.mitchell@linux.spacemit.com>
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*/
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#include <platform_override.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_hsm.h>
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#include <spacemit/k1.h>
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/* only use 0-1 cluster in SpacemiT K1 */
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static const int cci_map[] = {
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PLAT_CCI_CLUSTER0_IFACE_IX,
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PLAT_CCI_CLUSTER1_IFACE_IX,
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};
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static void cci_enable_snoop_dvm_reqs(unsigned int master_id)
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{
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int slave_if_id = cci_map[master_id];
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/*
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* Enable Snoops and DVM messages, no need for Read/Modify/Write as
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* rest of bits are write ignore
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*/
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writel(CCI_550_SNOOP_CTRL_ENABLE_DVMS | CCI_550_SNOOP_CTRL_ENABLE_SNOOPS,
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(void *)(u64)CCI_550_PLATFORM_CCI_ADDR +
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CCI_550_SLAVE_IFACE_OFFSET(slave_if_id) + CCI_550_SNOOP_CTRL);
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/*
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* Wait for the completion of the write to the Snoop Control Register
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* before testing the change_pending bit
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*/
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mb();
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/* Wait for the dust to settle down */
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while ((readl((void *)(u64)CCI_550_PLATFORM_CCI_ADDR + CCI_550_STATUS) &
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CCI_550_STATUS_CHANGE_PENDING))
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;
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}
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static void spacemit_k1_pre_init(void)
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{
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unsigned int clusterid, cluster_enabled = 0;
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struct sbi_scratch *scratch;
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int i;
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scratch = sbi_scratch_thishart_ptr();
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writel(scratch->warmboot_addr, (unsigned int *)C0_RVBADDR_LO_ADDR);
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writel(scratch->warmboot_addr >> 32, (unsigned int *)C0_RVBADDR_HI_ADDR);
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writel(scratch->warmboot_addr, (unsigned int *)C1_RVBADDR_LO_ADDR);
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writel(scratch->warmboot_addr >> 32, (unsigned int *)C1_RVBADDR_HI_ADDR);
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for (i = 0; i < PLATFORM_MAX_CPUS; i++) {
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clusterid = CPU_TO_CLUSTER(i);
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if (!(cluster_enabled & (1 << clusterid))) {
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cluster_enabled |= 1 << clusterid;
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cci_enable_snoop_dvm_reqs(clusterid);
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}
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}
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}
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/*
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* Platform early initialization.
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*/
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static int spacemit_k1_early_init(bool cold_boot)
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{
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int rc;
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rc = generic_early_init(cold_boot);
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if (rc)
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return rc;
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csr_set(CSR_MSETUP, MSETUP_DE | MSETUP_IE | MSETUP_BPE |
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MSETUP_PFE | MSETUP_MME | MSETUP_ECCE);
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if (cold_boot)
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spacemit_k1_pre_init();
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return 0;
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}
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static bool spacemit_cold_boot_allowed(u32 hartid)
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{
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csr_set(CSR_ML2SETUP, 1 << (hartid % PLATFORM_MAX_CPUS_PER_CLUSTER));
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return !hartid;
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}
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static int spacemit_k1_platform_init(const void *fdt, int nodeoff,
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const struct fdt_match *match)
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{
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generic_platform_ops.early_init = spacemit_k1_early_init;
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generic_platform_ops.cold_boot_allowed = spacemit_cold_boot_allowed;
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return 0;
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}
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static const struct fdt_match spacemit_k1_match[] = {
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{ .compatible = "spacemit,k1" },
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{ /* sentinel */ }
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};
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const struct fdt_driver spacemit_k1 = {
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.match_table = spacemit_k1_match,
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.init = spacemit_k1_platform_init,
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};
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