mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-03 21:48:45 +00:00
292e6344fa
Emulation of CSR read for misa and mhartid was a workaround for bootloader accessing these CSRs in S-mode. This patch removes CSR read emulation for misa and mhartid. Signed-off-by: Anup Patel <anup.patel@wdc.com>
143 lines
3.2 KiB
C
143 lines
3.2 KiB
C
/*
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* Copyright (c) 2018 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_bits.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_emulate_csr.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_timer.h>
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int sbi_emulate_csr_read(int csr_num,
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u32 hartid, ulong mstatus,
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struct sbi_scratch *scratch,
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ulong *csr_val)
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{
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ulong cen = -1UL;
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if (EXTRACT_FIELD(mstatus, MSTATUS_MPP) == PRV_U)
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cen = csr_read(scounteren);
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switch (csr_num) {
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case CSR_CYCLE:
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if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
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return -1;
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*csr_val = csr_read(mcycle);
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break;
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case CSR_TIME:
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if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
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return -1;
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*csr_val = sbi_timer_value(scratch);
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break;
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case CSR_INSTRET:
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if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
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return -1;
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*csr_val = csr_read(minstret);
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break;
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case CSR_MHPMCOUNTER3:
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if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
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return -1;
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*csr_val = csr_read(mhpmcounter3);
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break;
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case CSR_MHPMCOUNTER4:
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if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
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return -1;
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*csr_val = csr_read(mhpmcounter4);
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break;
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#if __riscv_xlen == 32
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case CSR_CYCLEH:
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if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
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return -1;
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*csr_val = csr_read(mcycleh);
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break;
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case CSR_TIMEH:
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if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
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return -1;
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*csr_val = sbi_timer_value(scratch);
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*csr_val = *csr_val >> 32;
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break;
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case CSR_INSTRETH:
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if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
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return -1;
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*csr_val = csr_read(minstreth);
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break;
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case CSR_MHPMCOUNTER3H:
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if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
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return -1;
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*csr_val = csr_read(mhpmcounter3h);
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break;
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case CSR_MHPMCOUNTER4H:
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if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
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return -1;
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*csr_val = csr_read(mhpmcounter4h);
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break;
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#endif
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case CSR_MHPMEVENT3:
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*csr_val = csr_read(mhpmevent3);
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break;
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case CSR_MHPMEVENT4:
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*csr_val = csr_read(mhpmevent4);
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break;
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default:
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sbi_printf("%s: hartid%d: invalid csr_num=0x%x\n",
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__func__, hartid, csr_num);
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return SBI_ENOTSUPP;
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};
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return 0;
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}
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int sbi_emulate_csr_write(int csr_num,
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u32 hartid, ulong mstatus,
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struct sbi_scratch *scratch,
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ulong csr_val)
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{
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switch (csr_num) {
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case CSR_CYCLE:
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csr_write(mcycle, csr_val);
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break;
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case CSR_INSTRET:
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csr_write(minstret, csr_val);
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break;
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case CSR_MHPMCOUNTER3:
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csr_write(mhpmcounter3, csr_val);
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break;
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case CSR_MHPMCOUNTER4:
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csr_write(mhpmcounter4, csr_val);
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break;
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#if __riscv_xlen == 32
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case CSR_CYCLEH:
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csr_write(mcycleh, csr_val);
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break;
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case CSR_INSTRETH:
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csr_write(minstreth, csr_val);
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break;
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case CSR_MHPMCOUNTER3H:
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csr_write(mhpmcounter3h, csr_val);
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break;
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case CSR_MHPMCOUNTER4H:
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csr_write(mhpmcounter4h, csr_val);
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break;
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#endif
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case CSR_MHPMEVENT3:
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csr_write(mhpmevent3, csr_val);
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break;
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case CSR_MHPMEVENT4:
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csr_write(mhpmevent4, csr_val);
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break;
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default:
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sbi_printf("%s: hartid%d: invalid csr_num=0x%x\n",
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__func__, hartid, csr_num);
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return SBI_ENOTSUPP;
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};
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return 0;
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}
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