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1207c7568f
The current RISC-V CMO only defines how to flush a cache block. However, certain use cases, such as power management, may require flushing the entire cache. Therefore, a framework is being introduced to allow vendors to flush the entire cache using their own methods. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-1-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
8 lines
125 B
Makefile
8 lines
125 B
Makefile
#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2025 SiFive
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#
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libsbiutils-objs-$(CONFIG_CACHE) += cache/cache.o
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