mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-06 15:00:26 +00:00
fb70fe8b98
Add code to bring up all 8 cores during OpenSBI initialization so that the Linux kernel can detect and use all cores properly. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-2-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
141 lines
3.2 KiB
C
141 lines
3.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 SpacemiT
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* Authors:
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* Xianbin Zhu <xianbin.zhu@linux.spacemit.com>
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* Troy Mitchell <troy.mitchell@linux.spacemit.com>
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*/
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#include <platform_override.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_hsm.h>
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#include <spacemit/k1.h>
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static const u64 cpu_wakeup_reg[] = {
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PMU_AP_CORE0_WAKEUP,
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PMU_AP_CORE1_WAKEUP,
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PMU_AP_CORE2_WAKEUP,
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PMU_AP_CORE3_WAKEUP,
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PMU_AP_CORE4_WAKEUP,
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PMU_AP_CORE5_WAKEUP,
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PMU_AP_CORE6_WAKEUP,
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PMU_AP_CORE7_WAKEUP,
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};
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static const u64 cpu_idle_reg[] = {
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PMU_AP_CORE0_IDLE_CFG,
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PMU_AP_CORE1_IDLE_CFG,
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PMU_AP_CORE2_IDLE_CFG,
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PMU_AP_CORE3_IDLE_CFG,
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PMU_AP_CORE4_IDLE_CFG,
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PMU_AP_CORE5_IDLE_CFG,
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PMU_AP_CORE6_IDLE_CFG,
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PMU_AP_CORE7_IDLE_CFG,
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};
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static inline void spacemit_set_cpu_power(u32 hartid, bool enable)
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{
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unsigned int value;
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unsigned int *cpu_idle_base = (unsigned int *)(unsigned long)cpu_idle_reg[hartid];
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value = readl(cpu_idle_base);
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if (enable)
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value &= ~PMU_AP_IDLE_PWRDOWN_MASK;
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else
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value |= PMU_AP_IDLE_PWRDOWN_MASK;
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writel(value, cpu_idle_base);
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}
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static void spacemit_wakeup_cpu(u32 mpidr)
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{
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unsigned int *cpu_reset_base;
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unsigned int cur_hartid = current_hartid();
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cpu_reset_base = (unsigned int *)(unsigned long)cpu_wakeup_reg[cur_hartid];
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writel(1 << mpidr, cpu_reset_base);
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}
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static void spacemit_assert_cpu(void)
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{
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spacemit_set_cpu_power(current_hartid(), false);
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}
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static void spacemit_deassert_cpu(unsigned int hartid)
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{
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spacemit_set_cpu_power(hartid, true);
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}
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/* Start (or power-up) the given hart */
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static int spacemit_hart_start(unsigned int hartid, unsigned long saddr)
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{
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spacemit_deassert_cpu(hartid);
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spacemit_wakeup_cpu(hartid);
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return 0;
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}
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/*
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* Stop (or power-down) the current hart from running. This call
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* doesn't expect to return if success.
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*/
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static int spacemit_hart_stop(void)
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{
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csr_write(CSR_STIMECMP, GENMASK_ULL(63, 0));
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csr_clear(CSR_MIE, MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | MIP_SEIP | MIP_MEIP);
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/* disable data preftch */
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csr_clear(CSR_MSETUP, MSETUP_PFE);
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asm volatile ("fence iorw, iorw");
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/* flush local dcache */
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csr_write(CSR_MRAOP, MRAOP_ICACHE_INVALID);
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asm volatile ("fence iorw, iorw");
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/* disable dcache */
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csr_clear(CSR_MSETUP, MSETUP_DE);
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asm volatile ("fence iorw, iorw");
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/*
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* Core4-7 do not have dedicated bits in ML2SETUP;
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* instead, they reuse the same bits as core0-3.
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*
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* Thereforspacemit_deassert_cpue, use modulo with PLATFORM_MAX_CPUS_PER_CLUSTER
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* to select the proper bit.
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*/
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csr_clear(CSR_ML2SETUP, 1 << (current_hartid() % PLATFORM_MAX_CPUS_PER_CLUSTER));
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asm volatile ("fence iorw, iorw");
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spacemit_assert_cpu();
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wfi();
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return SBI_ENOTSUPP;
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}
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static const struct sbi_hsm_device spacemit_hsm_ops = {
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.name = "spacemit-hsm",
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.hart_start = spacemit_hart_start,
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.hart_stop = spacemit_hart_stop,
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};
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static int spacemit_hsm_probe(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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sbi_hsm_set_device(&spacemit_hsm_ops);
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return 0;
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}
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static const struct fdt_match spacemit_hsm_match[] = {
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{ .compatible = "spacemit,k1" },
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{ },
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};
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const struct fdt_driver fdt_hsm_spacemit = {
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.match_table = spacemit_hsm_match,
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.init = spacemit_hsm_probe,
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};
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