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https://github.com/riscv-software-src/opensbi
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ce7c490719
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.
Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.
dts example (Quad-core AX45MP):
plicsw: interrupt-controller@e6400000 {
compatible = "andestech,plicsw";
reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
interrupts-extended = <&CPU0_intc 3
&CPU1_intc 3
&CPU2_intc 3
&CPU3_intc 3>;
interrupt-controller;
#address-cells = <2>;
#interrupt-cells = <2>;
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
47 lines
1015 B
C
47 lines
1015 B
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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* Leo Yu-Chi Liang <ycliang@andestech.com>
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#ifndef _IPI_ANDES_PLICSW_H_
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#define _IPI_ANDES_PLICSW_H_
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#define PLICSW_PRIORITY_BASE 0x4
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#define PLICSW_PENDING_BASE 0x1000
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#define PLICSW_PENDING_STRIDE 0x8
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#define PLICSW_ENABLE_BASE 0x2000
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#define PLICSW_ENABLE_STRIDE 0x80
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#define PLICSW_CONTEXT_BASE 0x200000
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#define PLICSW_CONTEXT_STRIDE 0x1000
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#define PLICSW_CONTEXT_CLAIM 0x4
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#define PLICSW_HART_MASK 0x01010101
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#define PLICSW_HART_MAX_NR 8
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#define PLICSW_REGION_ALIGN 0x1000
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struct plicsw_data {
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unsigned long addr;
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unsigned long size;
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uint32_t hart_count;
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/* hart id to source id table */
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uint32_t source_id[PLICSW_HART_MAX_NR];
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};
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int plicsw_warm_ipi_init(void);
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int plicsw_cold_ipi_init(struct plicsw_data *plicsw);
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#endif /* _IPI_ANDES_PLICSW_H_ */
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