mirror of
https://github.com/riscv-software-src/opensbi
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db56ef367c
C-Class is a member of the SHAKTI family of processors from Indian Institute of Technology - Madras(IIT-M). It is an extremely configurable and commercial-grade 5-stage in-order core supporting the standard RV64GCSUN ISA extensions. https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md We add OpenSBI support for Shakti C-class SoC. Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
45 lines
924 B
C
45 lines
924 B
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Vijai Kumar K <vijai@behindbytes.com>
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi_utils/serial/shakti-uart.h>
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#define REG_BAUD 0x00
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#define REG_TX 0x04
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#define REG_RX 0x08
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#define REG_STATUS 0x0C
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#define REG_DELAY 0x10
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#define REG_CONTROL 0x14
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#define REG_INT_EN 0x18
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#define REG_IQ_CYCLES 0x1C
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#define REG_RX_THRES 0x20
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static volatile void *uart_base;
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void shakti_uart_putc(char ch)
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{
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while((readw(uart_base + REG_STATUS) & 0x2) == 0);
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writeb(ch, uart_base + REG_TX);
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}
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int shakti_uart_getc(void)
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{
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u16 status = readw(uart_base + REG_STATUS);
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if (status & 0x8)
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return readb(uart_base + REG_RX);
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return -1;
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}
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int shakti_uart_init(unsigned long base, u32 in_freq, u32 baudrate)
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{
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uart_base = (volatile void *)base;
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u16 baud = (u16)(in_freq/(16 * baudrate));
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writew(baud, uart_base + REG_BAUD);
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return 0;
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}
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