mirror of
https://github.com/riscv-software-src/opensbi
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64e8b9f72e
Add Renesas SCIF driver. Based on a patch in the BSP by Takeki Hamada <takeki.hamada.ak@bp.renesas.com> Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org>
117 lines
3.0 KiB
C
117 lines
3.0 KiB
C
// SPDX-License-Identifier: BSD-2-Clause
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/*
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* Copyright (C) 2022 Renesas Electronics Corporation
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_timer.h>
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#include <sbi_utils/serial/renesas-scif.h>
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/* clang-format off */
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#define SCIF_REG_SMR 0x0
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#define SCIF_REG_BRR 0x2
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#define SCIF_REG_SCR 0x4
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#define SCIF_REG_FTDR 0x6
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#define SCIF_REG_FSR 0x8
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#define SCIF_REG_FCR 0xc
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#define SCIF_REG_LSR 0x12
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#define SCIF_REG_SEMR 0x14
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#define SCIF_FCR_RFRST 0x2 /* Reset assert receive-FIFO (bit[1]) */
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#define SCIF_FCR_TFRST 0x4 /* Reset assert transmit-FIFO(bit[2]) */
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#define SCIF_FCR_RST_ASSRT_RFTF (SCIF_FCR_RFRST | SCIF_FCR_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
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#define SCIF_FCR_RST_NGATE_RFTF 0x0 /* Reset negate tx-FIFO & rx-FIFO */
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#define SCIF_SCR_RE 0x10 /* Enable receive (bit[4]) */
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#define SCIF_SCR_TE 0x20 /* Enable transmit(bit[5]) */
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#define SCIF_SCR_RCV_TRN_EN (SCIF_SCR_RE | SCIF_SCR_TE) /* Enable receive & transmit */
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#define SCIF_SCR_RCV_TRN_DIS 0x0 /* Disable receive & transmit */
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#define SCIF_FSR_ER 0x80 /* Receive error flag */
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#define SCIF_FSR_TEND 0x40 /* Transmit End Flag */
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#define SCIF_FSR_TDFE 0x20 /* Transmit FIFO Data Empty Flag */
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#define SCIF_FSR_BRK 0x10 /* Detect break flag */
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#define SCIF_FSR_DR 0x1 /* Receive data ready flag */
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#define SCIF_FSR_TXD_CHK (SCIF_FSR_TEND | SCIF_FSR_TDFE)
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#define SCIF_SEMR_MDDRS 0x10 /* MDDR access enable */
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#define SCIF_REG_8BIT(reg) ((reg == SCIF_REG_BRR) || \
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(reg == SCIF_REG_FTDR) || \
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(reg == SCIF_REG_SEMR))
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#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
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/* clang-format on */
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static volatile char *scif_base;
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static u32 get_reg(u32 offset)
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{
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if (SCIF_REG_8BIT(offset))
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return readb(scif_base + offset);
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return readw(scif_base + offset);
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}
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static void set_reg(u32 offset, u32 val)
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{
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if (SCIF_REG_8BIT(offset))
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writeb(val, scif_base + offset);
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else
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writew(val, scif_base + offset);
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}
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static void renesas_scif_putc(char ch)
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{
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uint16_t reg;
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while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
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;
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set_reg(SCIF_REG_FTDR, ch);
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reg = get_reg(SCIF_REG_FSR);
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reg &= ~SCIF_FSR_TXD_CHK;
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set_reg(SCIF_REG_FSR, reg);
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}
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static struct sbi_console_device renesas_scif_console = {
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.name = "renesas_scif",
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.console_putc = renesas_scif_putc,
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};
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int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
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{
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uint16_t data16;
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scif_base = (volatile char *)base;
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set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS);
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set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_RFTF);
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data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
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set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
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data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
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set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
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set_reg(SCIF_REG_SCR, 0x0);
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set_reg(SCIF_REG_SMR, 0x0);
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data16 = get_reg(SCIF_REG_SEMR);
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set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS));
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set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
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set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_RFTF);
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set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN);
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sbi_console_set_device(&renesas_scif_console);
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return 0;
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}
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