mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-04 05:50:22 +00:00
ef9f02e7fb
Since we can get the PLMT base address and timer frequency from
device tree, move plmt timer device to fdt timer framework.
dts example (Quad-core AX45MP):
cpus {
...
timebase-frequency = <0x3938700>;
...
}
soc {
...
plmt0@e6000000 {
compatible = "andestech,plmt0";
reg = <0x00 0xe6000000 0x00 0x100000>;
interrupts-extended = <&cpu0_intc 0x07
&cpu1_intc 0x07
&cpu2_intc 0x07
&cpu3_intc 0x07>;
};
...
}
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
105 lines
2.2 KiB
C
105 lines
2.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Andes Technology Corporation
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*
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* Authors:
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_timer.h>
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#include <sbi_utils/timer/andes_plmt.h>
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struct plmt_data plmt;
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static u64 plmt_timer_value(void)
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{
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#if __riscv_xlen == 64
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return readq_relaxed(plmt.time_val);
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#else
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u32 lo, hi;
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do {
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hi = readl_relaxed((void *)plmt.time_val + 0x04);
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lo = readl_relaxed(plmt.time_val);
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} while (hi != readl_relaxed((void *)plmt.time_val + 0x04));
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return ((u64)hi << 32) | (u64)lo;
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#endif
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}
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static void plmt_timer_event_stop(void)
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{
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u32 target_hart = current_hartid();
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if (plmt.hart_count <= target_hart)
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ebreak();
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/* Clear PLMT Time Compare */
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#if __riscv_xlen == 64
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writeq_relaxed(-1ULL, &plmt.time_cmp[target_hart]);
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#else
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writel_relaxed(-1UL, &plmt.time_cmp[target_hart]);
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writel_relaxed(-1UL, (void *)(&plmt.time_cmp[target_hart]) + 0x04);
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#endif
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}
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static void plmt_timer_event_start(u64 next_event)
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{
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u32 target_hart = current_hartid();
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if (plmt.hart_count <= target_hart)
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ebreak();
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/* Program PLMT Time Compare */
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#if __riscv_xlen == 64
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writeq_relaxed(next_event, &plmt.time_cmp[target_hart]);
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#else
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u32 mask = -1UL;
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writel_relaxed(next_event & mask, &plmt.time_cmp[target_hart]);
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writel_relaxed(next_event >> 32,
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(void *)(&plmt.time_cmp[target_hart]) + 0x04);
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#endif
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}
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static struct sbi_timer_device plmt_timer = {
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.name = "andes_plmt",
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.timer_freq = DEFAULT_AE350_PLMT_FREQ,
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.timer_value = plmt_timer_value,
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.timer_event_start = plmt_timer_event_start,
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.timer_event_stop = plmt_timer_event_stop
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};
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int plmt_cold_timer_init(struct plmt_data *plmt)
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{
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int rc;
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/* Add PLMT region to the root domain */
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rc = sbi_domain_root_add_memrange(
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(unsigned long)plmt->time_val, plmt->size, PLMT_REGION_ALIGN,
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SBI_DOMAIN_MEMREGION_MMIO | SBI_DOMAIN_MEMREGION_READABLE);
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if (rc)
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return rc;
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plmt_timer.timer_freq = plmt->timer_freq;
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sbi_timer_set_device(&plmt_timer);
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return 0;
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}
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int plmt_warm_timer_init(void)
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{
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if (!plmt.time_val)
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return SBI_ENODEV;
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plmt_timer_event_stop();
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return 0;
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}
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