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				https://github.com/riscv-software-src/opensbi
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	sbi_cppc_write was writing to the a1 register only, which under rv32 would cause the high 32 bits to always be 0. This patch fixes that. Closes: https://github.com/riscv-software-src/opensbi/issues/334 Signed-off-by: Xiang W <wxjstz@126.com> Reported-by: Wesley Norris <repnop@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
		
			
				
	
	
		
			73 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			73 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * SPDX-License-Identifier: BSD-2-Clause
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 *
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 * Copyright (c) 2023 Ventana Micro Systems Inc.
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 *
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 */
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#include <sbi/sbi_ecall.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_trap.h>
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#include <sbi/sbi_cppc.h>
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static int sbi_ecall_cppc_handler(unsigned long extid, unsigned long funcid,
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				  struct sbi_trap_regs *regs,
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				  struct sbi_ecall_return *out)
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{
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	int ret = 0;
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	uint64_t temp;
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	switch (funcid) {
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	case SBI_EXT_CPPC_READ:
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		ret = sbi_cppc_read(regs->a0, &temp);
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		out->value = temp;
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		break;
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	case SBI_EXT_CPPC_READ_HI:
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#if __riscv_xlen == 32
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		ret = sbi_cppc_read(regs->a0, &temp);
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		out->value = temp >> 32;
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#else
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		out->value = 0;
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#endif
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		break;
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	case SBI_EXT_CPPC_WRITE:
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#if __riscv_xlen == 32
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		temp = regs->a2;
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		temp = (temp << 32) | regs->a1;
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#else
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		temp = regs->a1;
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#endif
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		ret = sbi_cppc_write(regs->a0, temp);
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		break;
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	case SBI_EXT_CPPC_PROBE:
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		ret = sbi_cppc_probe(regs->a0);
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		if (ret >= 0) {
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			out->value = ret;
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			ret = 0;
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		}
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		break;
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	default:
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		ret = SBI_ENOTSUPP;
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	}
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	return ret;
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}
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struct sbi_ecall_extension ecall_cppc;
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static int sbi_ecall_cppc_register_extensions(void)
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{
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	if (!sbi_cppc_get_device())
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		return 0;
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	return sbi_ecall_register_extension(&ecall_cppc);
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}
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struct sbi_ecall_extension ecall_cppc = {
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	.extid_start		= SBI_EXT_CPPC,
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	.extid_end		= SBI_EXT_CPPC,
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	.register_extensions	= sbi_ecall_cppc_register_extensions,
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	.handle			= sbi_ecall_cppc_handler,
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};
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