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https://github.com/riscv-software-src/opensbi
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1207c7568f
The current RISC-V CMO only defines how to flush a cache block. However, certain use cases, such as power management, may require flushing the entire cache. Therefore, a framework is being introduced to allow vendors to flush the entire cache using their own methods. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-1-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
70 lines
1.4 KiB
C
70 lines
1.4 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 SiFive Inc.
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*/
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#ifndef __CACHE_H__
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#define __CACHE_H__
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#include <sbi/sbi_list.h>
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#include <sbi/sbi_types.h>
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#define CACHE_NAME_LEN 32
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struct cache_device;
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struct cache_ops {
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/** Warm init **/
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int (*warm_init)(struct cache_device *dev);
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/** Flush entire cache **/
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int (*cache_flush_all)(struct cache_device *dev);
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};
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struct cache_device {
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/** Name of the device **/
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char name[CACHE_NAME_LEN];
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/** List node for search **/
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struct sbi_dlist node;
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/** Point to the next level cache **/
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struct cache_device *next;
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/** Cache Management Operations **/
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struct cache_ops *ops;
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/** CPU private cache **/
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bool cpu_private;
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/** The unique id of this cache device **/
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u32 id;
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};
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/**
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* Find a registered cache device
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*
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* @param id unique ID of the cache device
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*
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* @return the cache device or NULL
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*/
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struct cache_device *cache_find(u32 id);
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/**
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* Register a cache device
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*
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* cache_device->id must be initialized already and must not change during the life
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* of the cache_device object.
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*
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* @param dev the cache device to register
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*
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* @return 0 on success, or a negative error code on failure
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*/
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int cache_add(struct cache_device *dev);
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/**
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* Flush the entire cache
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*
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* @param dev the cache to flush
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*
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* @return 0 on success, or a negative error code on failure
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*/
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int cache_flush_all(struct cache_device *dev);
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#endif
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