mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-04 05:50:22 +00:00
ea6533ada8
Currently, we see following compile error in the designeware GPIO driver
for RV32 systems:
lib/utils/gpio/fdt_gpio_designware.c:115:20: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
115 | chip->dr = (void *)addr + (bank * 0xc);
| ^
lib/utils/gpio/fdt_gpio_designware.c:116:21: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
116 | chip->ext = (void *)addr + (bank * 4) + 0x50;
We fix the above error using an explicit type-cast to 'unsigned long'.
Fixes: 7828eebaaa77 ("gpio/desginware: add Synopsys DesignWare APB GPIO support")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
141 lines
3.3 KiB
C
141 lines
3.3 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 SiFive
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*
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* GPIO driver for Synopsys DesignWare APB GPIO
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*
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* Authors:
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* Ben Dooks <ben.dooks@sifive.com>
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*/
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#include <libfdt.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_error.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/gpio/fdt_gpio.h>
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#define DW_GPIO_CHIP_MAX 4 /* need 1 per bank in use */
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#define DW_GPIO_PINS_MAX 32
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#define DW_GPIO_DDR 0x4
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#define DW_GPIO_DR 0x0
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#define DW_GPIO_BIT(_b) (1UL << (_b))
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struct dw_gpio_chip {
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void *dr;
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void *ext;
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struct gpio_chip chip;
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};
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extern struct fdt_gpio fdt_gpio_designware;
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static unsigned int dw_gpio_chip_count;
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static struct dw_gpio_chip dw_gpio_chip_array[DW_GPIO_CHIP_MAX];
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#define pin_to_chip(__p) container_of((__p)->chip, struct dw_gpio_chip, chip);
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static int dw_gpio_direction_output(struct gpio_pin *gp, int value)
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{
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struct dw_gpio_chip *chip = pin_to_chip(gp);
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unsigned long v;
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v = readl(chip->dr + DW_GPIO_DR);
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if (!value)
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v &= ~DW_GPIO_BIT(gp->offset);
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else
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v |= DW_GPIO_BIT(gp->offset);
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writel(v, chip->dr + DW_GPIO_DR);
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/* the DR is output only so we can set it then the DDR to set
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* the data direction, to avoid glitches.
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*/
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v = readl(chip->dr + DW_GPIO_DDR);
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v |= DW_GPIO_BIT(gp->offset);
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writel(v, chip->dr + DW_GPIO_DDR);
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return 0;
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}
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static void dw_gpio_set(struct gpio_pin *gp, int value)
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{
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struct dw_gpio_chip *chip = pin_to_chip(gp);
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unsigned long v;
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v = readl(chip->dr + DW_GPIO_DR);
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if (!value)
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v &= ~DW_GPIO_BIT(gp->offset);
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else
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v |= DW_GPIO_BIT(gp->offset);
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writel(v, chip->dr + DW_GPIO_DR);
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}
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/* notes:
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* each sub node is a bank and has ngpios or snpns,nr-gpios and a reg property
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* with the compatible `snps,dw-apb-gpio-port`.
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* bank A is the only one with irq support but we're not using it here
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*/
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static int dw_gpio_init_bank(void *fdt, int nodeoff, u32 phandle,
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const struct fdt_match *match)
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{
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struct dw_gpio_chip *chip;
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const fdt32_t *val;
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uint64_t addr;
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int rc, poff, nr_pins, bank, len;
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if (dw_gpio_chip_count >= DW_GPIO_CHIP_MAX)
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return SBI_ENOSPC;
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/* need to get parent for the address property */
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poff = fdt_parent_offset(fdt, nodeoff);
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if (poff < 0)
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return SBI_EINVAL;
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rc = fdt_get_node_addr_size(fdt, poff, 0, &addr, NULL);
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if (rc)
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return rc;
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val = fdt_getprop(fdt, nodeoff, "reg", &len);
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if (!val || len <= 0)
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return SBI_EINVAL;
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bank = fdt32_to_cpu(*val);
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val = fdt_getprop(fdt, nodeoff, "snps,nr-gpios", &len);
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if (!val)
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val = fdt_getprop(fdt, nodeoff, "ngpios", &len);
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if (!val || len <= 0)
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return SBI_EINVAL;
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nr_pins = fdt32_to_cpu(*val);
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chip = &dw_gpio_chip_array[dw_gpio_chip_count];
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chip->dr = (void *)(uintptr_t)addr + (bank * 0xc);
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chip->ext = (void *)(uintptr_t)addr + (bank * 4) + 0x50;
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chip->chip.driver = &fdt_gpio_designware;
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chip->chip.id = phandle;
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chip->chip.ngpio = nr_pins;
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chip->chip.set = dw_gpio_set;
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chip->chip.direction_output = dw_gpio_direction_output;
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rc = gpio_chip_add(&chip->chip);
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if (rc)
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return rc;
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dw_gpio_chip_count++;
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return 0;
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}
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/* since we're only probed when used, match on port not main controller node */
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static const struct fdt_match dw_gpio_match[] = {
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{ .compatible = "snps,dw-apb-gpio-port" },
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{ },
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};
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struct fdt_gpio fdt_gpio_designware = {
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.match_table = dw_gpio_match,
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.xlate = fdt_gpio_simple_xlate,
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.init = dw_gpio_init_bank,
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};
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