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https://github.com/riscv-software-src/opensbi
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OpenPiton is a research platform from Princeton University [1]. "OpenPiton is the world's first open source, general purpose, multithreaded manycore processor. It is a tiled manycore framework scalable from one to 1/2 billion cores." Add OpenSBI support for OpenPiton. As it is based on ariane core, it reuses the platform code from arine project. [1]. https://github.com/PrincetonUniversity/openpiton Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
36 lines
790 B
Makefile
36 lines
790 B
Makefile
#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2020 Western Digital Corporation or its affiliates.
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#
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#for more infos, check out /platform/template/config.mk
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PLATFORM_RISCV_XLEN = 64
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# Blobs to build
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FW_TEXT_START=0x80000000
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FW_JUMP=n
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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# This needs to be 4MB aligned for 32-bit support
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FW_JUMP_ADDR=0x80400000
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else
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# This needs to be 2MB aligned for 64-bit support
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FW_JUMP_ADDR=0x80200000
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endif
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FW_JUMP_FDT_ADDR=0x82200000
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# Firmware with payload configuration.
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FW_PAYLOAD=y
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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# This needs to be 4MB aligned for 32-bit support
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FW_PAYLOAD_OFFSET=0x400000
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else
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# This needs to be 2MB aligned for 64-bit support
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FW_PAYLOAD_OFFSET=0x200000
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endif
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FW_PAYLOAD_FDT_ADDR=0x82200000
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FW_PAYLOAD_ALIGN=0x1000
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