mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-04 05:50:22 +00:00
6585fabbcc
This patch factor-out SiFive test device related stuff into it's own source file from qemu/virt platform. In future, we can find SiFive test device address from device tree as well. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
45 lines
853 B
C
45 lines
853 B
C
/*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/sys/sifive_test.h>
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#define FINISHER_FAIL 0x3333
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#define FINISHER_PASS 0x5555
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#define FINISHER_RESET 0x7777
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static void *sifive_test_base;
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int sifive_test_system_reset(u32 type)
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{
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/*
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* Tell the "finisher" that the simulation
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* was successful so that QEMU exits
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*/
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switch (type) {
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case SBI_PLATFORM_RESET_SHUTDOWN:
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writew(FINISHER_PASS, sifive_test_base);
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break;
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case SBI_PLATFORM_RESET_COLD:
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case SBI_PLATFORM_RESET_WARM:
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writew(FINISHER_RESET, sifive_test_base);
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break;
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}
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return 0;
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}
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int sifive_test_init(unsigned long base)
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{
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sifive_test_base = (void *)base;
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return 0;
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}
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