mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-03 21:48:45 +00:00
9eb8f0f90d
platform should be a read-only variable, if it is placed in the data segment, it may be exploited. Signed-off-by: Xiang Wang <wxjstz@126.com>
112 lines
2.6 KiB
C
112 lines
2.6 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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* Nick Kossifidis <mick@ics.forth.gr>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_barrier.h>
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#include <sbi/riscv_atomic.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_timer.h>
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#include <sbi/sbi_unpriv.h>
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static int sbi_ipi_send(struct sbi_scratch *scratch, u32 hartid, u32 event)
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{
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struct sbi_scratch *remote_scratch = NULL;
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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if (sbi_platform_hart_disabled(plat, hartid))
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return -1;
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/* Set IPI type on remote hart's scratch area and
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* trigger the interrupt
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*/
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remote_scratch = sbi_hart_id_to_scratch(scratch, hartid);
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atomic_raw_set_bit(event, &remote_scratch->ipi_type);
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mb();
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sbi_platform_ipi_send(plat, hartid);
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if (event != SBI_IPI_EVENT_SOFT)
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sbi_platform_ipi_sync(plat, hartid);
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return 0;
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}
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int sbi_ipi_send_many(struct sbi_scratch *scratch,
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ulong *pmask, u32 event)
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{
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ulong i, m;
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ulong mask = sbi_hart_available_mask();
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u32 hartid = sbi_current_hartid();
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if (pmask)
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mask &= load_ulong(pmask, csr_read(CSR_MEPC));
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/* send IPIs to every other hart on the set */
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for (i = 0, m = mask; m; i++, m >>= 1)
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if ((m & 1UL) && (i != hartid))
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sbi_ipi_send(scratch, i, event);
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/* If the current hart is on the set, send an IPI
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* to it as well
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*/
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if (mask & (1UL << hartid))
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sbi_ipi_send(scratch, hartid, event);
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return 0;
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}
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void sbi_ipi_clear_smode(struct sbi_scratch *scratch)
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{
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csr_clear(CSR_MIP, MIP_SSIP);
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}
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void sbi_ipi_process(struct sbi_scratch *scratch)
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{
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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volatile unsigned long ipi_type;
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unsigned int ipi_event;
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u32 hartid = sbi_current_hartid();
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sbi_platform_ipi_clear(plat, hartid);
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do {
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ipi_type = scratch->ipi_type;
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rmb();
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ipi_event = __ffs(ipi_type);
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switch (ipi_event) {
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case SBI_IPI_EVENT_SOFT:
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csr_set(CSR_MIP, MIP_SSIP);
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break;
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case SBI_IPI_EVENT_FENCE_I:
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__asm__ __volatile("fence.i");
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break;
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case SBI_IPI_EVENT_SFENCE_VMA:
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__asm__ __volatile("sfence.vma");
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break;
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case SBI_IPI_EVENT_HALT:
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sbi_hart_hang();
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break;
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};
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ipi_type = atomic_raw_clear_bit(ipi_event, &scratch->ipi_type);
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} while(ipi_type > 0);
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}
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int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot)
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{
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/* Enable software interrupts */
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csr_set(CSR_MIE, MIP_MSIP);
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return sbi_platform_ipi_init(sbi_platform_ptr(scratch),
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cold_boot);
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}
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