mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-03 21:48:45 +00:00
9eb8f0f90d
platform should be a read-only variable, if it is placed in the data segment, it may be exploited. Signed-off-by: Xiang Wang <wxjstz@126.com>
161 lines
3.3 KiB
C
161 lines
3.3 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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* Nick Kossifidis <mick@ics.forth.gr>
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*/
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <plat/irqchip/plic.h>
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#include <plat/serial/uart8250.h>
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#include <plat/sys/clint.h>
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#define VIRT_HART_COUNT 8
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#define VIRT_HART_STACK_SIZE 8192
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#define VIRT_TEST_ADDR 0x100000
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#define VIRT_TEST_FINISHER_FAIL 0x3333
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#define VIRT_TEST_FINISHER_PASS 0x5555
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#define VIRT_CLINT_ADDR 0x2000000
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#define VIRT_PLIC_ADDR 0xc000000
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#define VIRT_PLIC_NUM_SOURCES 127
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#define VIRT_PLIC_NUM_PRIORITIES 7
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#define VIRT_UART16550_ADDR 0x10000000
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#define VIRT_UART_BAUDRATE 115200
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#define VIRT_UART_SHIFTREG_ADDR 1843200
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static int virt_final_init(bool cold_boot)
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{
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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plic_fdt_fixup(fdt, "riscv,plic0");
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return 0;
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}
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static u32 virt_pmp_region_count(u32 hartid)
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{
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return 1;
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}
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static int virt_pmp_region_info(u32 hartid, u32 index,
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ulong *prot, ulong *addr, ulong *log2size)
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{
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int ret = 0;
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switch (index) {
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case 0:
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*prot = PMP_R | PMP_W | PMP_X;
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*addr = 0;
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*log2size = __riscv_xlen;
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break;
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default:
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ret = -1;
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break;
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};
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return ret;
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}
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static int virt_console_init(void)
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{
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return uart8250_init(VIRT_UART16550_ADDR,
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VIRT_UART_SHIFTREG_ADDR,
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VIRT_UART_BAUDRATE, 0, 1);
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}
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static int virt_irqchip_init(bool cold_boot)
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{
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int rc;
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u32 hartid = sbi_current_hartid();
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if (cold_boot) {
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rc = plic_cold_irqchip_init(VIRT_PLIC_ADDR,
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VIRT_PLIC_NUM_SOURCES,
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VIRT_HART_COUNT);
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if (rc)
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return rc;
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}
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return plic_warm_irqchip_init(hartid,
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(2 * hartid),
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(2 * hartid + 1));
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}
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static int virt_ipi_init(bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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rc = clint_cold_ipi_init(VIRT_CLINT_ADDR,
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VIRT_HART_COUNT);
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if (rc)
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return rc;
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}
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return clint_warm_ipi_init();
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}
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static int virt_timer_init(bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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rc = clint_cold_timer_init(VIRT_CLINT_ADDR,
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VIRT_HART_COUNT);
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if (rc)
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return rc;
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}
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return clint_warm_timer_init();
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}
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static int virt_system_down(u32 type)
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{
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/* Tell the "finisher" that the simulation
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* was successful so that QEMU exits
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*/
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writew(VIRT_TEST_FINISHER_PASS, (void *)VIRT_TEST_ADDR);
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return 0;
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}
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const struct sbi_platform platform = {
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.name = "QEMU Virt Machine",
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.features = SBI_PLATFORM_DEFAULT_FEATURES,
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.hart_count = VIRT_HART_COUNT,
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.hart_stack_size = VIRT_HART_STACK_SIZE,
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.disabled_hart_mask = 0,
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.pmp_region_count = virt_pmp_region_count,
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.pmp_region_info = virt_pmp_region_info,
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.final_init = virt_final_init,
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.console_putc = uart8250_putc,
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.console_getc = uart8250_getc,
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.console_init = virt_console_init,
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.irqchip_init = virt_irqchip_init,
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.ipi_send = clint_ipi_send,
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.ipi_sync = clint_ipi_sync,
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.ipi_clear = clint_ipi_clear,
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.ipi_init = virt_ipi_init,
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.timer_value = clint_timer_value,
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.timer_event_stop = clint_timer_event_stop,
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.timer_event_start = clint_timer_event_start,
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.timer_init = virt_timer_init,
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.system_reboot = virt_system_down,
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.system_shutdown = virt_system_down
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};
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