mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-03 21:48:45 +00:00
a88e424f6c
We can get a page/access trap when doing unpriv load/store in get_insn() function because on a SMP system Linux swapper running on HART A can unmap pages from page table used by HART B. To tackle this we extend get_insn() implementation so that if we get trap in get_insn() then we redirect it to S-mode as fetch page/access fault. Signed-off-by: Anup Patel <anup.patel@wdc.com>
155 lines
5.3 KiB
C
155 lines
5.3 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_unpriv.h>
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#include <sbi/sbi_bits.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_scratch.h>
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#define DEFINE_UNPRIVILEGED_LOAD_FUNCTION(type, insn, insnlen) \
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type load_##type(const type *addr, \
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struct sbi_scratch *scratch, \
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struct unpriv_trap *trap) \
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{ \
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register ulong __mstatus asm("a2"); \
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type val = 0; \
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trap->ilen = insnlen; \
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trap->cause = 0; \
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trap->tval = 0; \
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sbi_hart_set_trap_info(scratch, trap); \
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asm volatile( \
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"csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \
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#insn " %1, %2\n" \
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"csrw " STR(CSR_MSTATUS) ", %0" \
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: "+&r"(__mstatus), "=&r"(val) \
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: "m"(*addr), "r"(MSTATUS_MPRV)); \
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sbi_hart_set_trap_info(scratch, NULL); \
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return val; \
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}
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#define DEFINE_UNPRIVILEGED_STORE_FUNCTION(type, insn, insnlen) \
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void store_##type(type *addr, type val, \
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struct sbi_scratch *scratch, \
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struct unpriv_trap *trap) \
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{ \
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register ulong __mstatus asm("a3"); \
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trap->ilen = insnlen; \
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trap->cause = 0; \
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trap->tval = 0; \
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sbi_hart_set_trap_info(scratch, trap); \
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asm volatile( \
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"csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \
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#insn " %1, %2\n" \
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"csrw " STR(CSR_MSTATUS) ", %0" \
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: "+&r"(__mstatus) \
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: "r"(val), "m"(*addr), "r"(MSTATUS_MPRV)); \
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sbi_hart_set_trap_info(scratch, NULL); \
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}
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw, 2)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u8, sb, 4)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u16, sh, 4)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u32, sw, 2)
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#if __riscv_xlen == 64
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu, 4)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld, 2)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u64, sd, 2)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld, 2)
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#else
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw, 2)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw, 2)
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u64 load_u64(const u64 *addr,
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struct sbi_scratch *scratch, struct unpriv_trap *trap)
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{
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u64 ret = load_u32((u32 *)addr, scratch, trap);
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if (trap->cause)
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return 0;
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ret |= ((u64)load_u32((u32 *)addr + 1, scratch, trap) << 32);
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if (trap->cause)
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return 0;
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return ret;
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}
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void store_u64(u64 *addr, u64 val,
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struct sbi_scratch *scratch, struct unpriv_trap *trap)
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{
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store_u32((u32 *)addr, val, scratch, trap);
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if (trap->cause)
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return;
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store_u32((u32 *)addr + 1, val >> 32, scratch, trap);
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if (trap->cause)
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return;
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}
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#endif
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ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
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struct unpriv_trap *trap)
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{
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ulong __mstatus = 0, val = 0;
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#ifdef __riscv_compressed
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ulong rvc_mask = 3, tmp;
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#endif
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if (trap) {
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trap->ilen = 4;
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trap->cause = 0;
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trap->tval = 0;
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sbi_hart_set_trap_info(scratch, trap);
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}
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#ifndef __riscv_compressed
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asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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#if __riscv_xlen == 64
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STR(LWU) " %[insn], (%[addr])\n"
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#else
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STR(LW) " %[insn], (%[addr])\n"
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#endif
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"csrw " STR(CSR_MSTATUS) ", %[mstatus]"
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: [mstatus] "+&r"(__mstatus), [insn] "=&r"(val)
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: [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(mepc));
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#else
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asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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"lhu %[insn], (%[addr])\n"
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"and %[tmp], %[insn], %[rvc_mask]\n"
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"bne %[tmp], %[rvc_mask], 2f\n"
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"lhu %[tmp], 2(%[addr])\n"
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"sll %[tmp], %[tmp], 16\n"
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"add %[insn], %[insn], %[tmp]\n"
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"2: csrw " STR(CSR_MSTATUS) ", %[mstatus]"
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: [mstatus] "+&r"(__mstatus), [insn] "=&r"(val), [tmp] "=&r"(tmp)
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: [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(mepc),
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[rvc_mask] "r"(rvc_mask));
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#endif
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if (trap) {
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sbi_hart_set_trap_info(scratch, NULL);
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switch (trap->cause) {
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case CAUSE_LOAD_ACCESS:
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trap->cause = CAUSE_FETCH_ACCESS;
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trap->tval = mepc;
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break;
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case CAUSE_LOAD_PAGE_FAULT:
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trap->cause = CAUSE_FETCH_PAGE_FAULT;
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trap->tval = mepc;
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break;
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default:
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break;
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};
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}
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return val;
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}
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