mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-04 05:50:22 +00:00
7a3a0cce4d
We add "index" parameter to fdt_get_node_addr_size() API so that calling function can specify index of desired register set. This will allow fdt_get_node_addr_size() to handle DT nodes with multiple register sets. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
108 lines
2.6 KiB
C
108 lines
2.6 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 SiFive
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*
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* Authors:
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* Green Wan <green.wan@sifive.com>
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_error.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/gpio/fdt_gpio.h>
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#define SIFIVE_GPIO_CHIP_MAX 2
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#define SIFIVE_GPIO_PINS_MIN 1
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#define SIFIVE_GPIO_PINS_MAX 32
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#define SIFIVE_GPIO_PINS_DEF 16
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#define SIFIVE_GPIO_OUTEN 0x8
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#define SIFIVE_GPIO_OUTVAL 0xc
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#define SIFIVE_GPIO_BIT(b) (1U << (b))
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struct sifive_gpio_chip {
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unsigned long addr;
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struct gpio_chip chip;
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};
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static unsigned int sifive_gpio_chip_count;
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static struct sifive_gpio_chip sifive_gpio_chip_array[SIFIVE_GPIO_CHIP_MAX];
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static int sifive_gpio_direction_output(struct gpio_pin *gp, int value)
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{
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unsigned int v;
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struct sifive_gpio_chip *chip =
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container_of(gp->chip, struct sifive_gpio_chip, chip);
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v = readl((volatile void *)(chip->addr + SIFIVE_GPIO_OUTEN));
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v |= SIFIVE_GPIO_BIT(gp->offset);
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writel(v, (volatile void *)(chip->addr + SIFIVE_GPIO_OUTEN));
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v = readl((volatile void *)(chip->addr + SIFIVE_GPIO_OUTVAL));
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if (!value)
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v &= ~SIFIVE_GPIO_BIT(gp->offset);
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else
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v |= SIFIVE_GPIO_BIT(gp->offset);
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writel(v, (volatile void *)(chip->addr + SIFIVE_GPIO_OUTVAL));
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return 0;
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}
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static void sifive_gpio_set(struct gpio_pin *gp, int value)
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{
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unsigned int v;
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struct sifive_gpio_chip *chip =
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container_of(gp->chip, struct sifive_gpio_chip, chip);
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v = readl((volatile void *)(chip->addr + SIFIVE_GPIO_OUTVAL));
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if (!value)
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v &= ~SIFIVE_GPIO_BIT(gp->offset);
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else
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v |= SIFIVE_GPIO_BIT(gp->offset);
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writel(v, (volatile void *)(chip->addr + SIFIVE_GPIO_OUTVAL));
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}
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extern struct fdt_gpio fdt_gpio_sifive;
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static int sifive_gpio_init(void *fdt, int nodeoff, u32 phandle,
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const struct fdt_match *match)
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{
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int rc;
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struct sifive_gpio_chip *chip;
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uint64_t addr;
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if (SIFIVE_GPIO_CHIP_MAX <= sifive_gpio_chip_count)
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return SBI_ENOSPC;
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chip = &sifive_gpio_chip_array[sifive_gpio_chip_count];
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rc = fdt_get_node_addr_size(fdt, nodeoff, 0, &addr, NULL);
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if (rc)
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return rc;
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chip->addr = addr;
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chip->chip.driver = &fdt_gpio_sifive;
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chip->chip.id = phandle;
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chip->chip.ngpio = SIFIVE_GPIO_PINS_DEF;
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chip->chip.direction_output = sifive_gpio_direction_output;
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chip->chip.set = sifive_gpio_set;
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rc = gpio_chip_add(&chip->chip);
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if (rc)
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return rc;
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sifive_gpio_chip_count++;
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return 0;
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}
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static const struct fdt_match sifive_gpio_match[] = {
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{ .compatible = "sifive,gpio0" },
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{ },
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};
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struct fdt_gpio fdt_gpio_sifive = {
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.match_table = sifive_gpio_match,
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.xlate = fdt_gpio_simple_xlate,
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.init = sifive_gpio_init,
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};
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