mirror of
https://github.com/riscv-software-src/opensbi
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ce7c490719
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.
Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.
dts example (Quad-core AX45MP):
plicsw: interrupt-controller@e6400000 {
compatible = "andestech,plicsw";
reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
interrupts-extended = <&CPU0_intc 3
&CPU1_intc 3
&CPU2_intc 3
&CPU3_intc 3>;
interrupt-controller;
#address-cells = <2>;
#interrupt-cells = <2>;
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
138 lines
3.2 KiB
C
138 lines
3.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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* Leo Yu-Chi Liang <ycliang@andestech.com>
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi_utils/ipi/andes_plicsw.h>
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struct plicsw_data plicsw;
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static inline void plicsw_claim(void)
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{
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u32 hartid = current_hartid();
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if (plicsw.hart_count <= hartid)
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ebreak();
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plicsw.source_id[hartid] =
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readl((void *)plicsw.addr + PLICSW_CONTEXT_BASE +
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PLICSW_CONTEXT_CLAIM + PLICSW_CONTEXT_STRIDE * hartid);
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}
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static inline void plicsw_complete(void)
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{
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u32 hartid = current_hartid();
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u32 source = plicsw.source_id[hartid];
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writel(source, (void *)plicsw.addr + PLICSW_CONTEXT_BASE +
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PLICSW_CONTEXT_CLAIM +
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PLICSW_CONTEXT_STRIDE * hartid);
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}
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static inline void plic_sw_pending(u32 target_hart)
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{
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/*
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* The pending array registers are w1s type.
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* IPI pending array mapping as following:
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*
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* Pending array start address: base + 0x1000
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* ---------------------------------
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* | hart3 | hart2 | hart1 | hart0 |
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* ---------------------------------
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* Each hartX can send IPI to another hart by setting the
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* bitY to its own region (see the below).
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*
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* In each hartX region:
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* <---------- PICSW_PENDING_STRIDE -------->
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* | bit7 | ... | bit3 | bit2 | bit1 | bit0 |
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* ------------------------------------------
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* The bitY of hartX region indicates that hartX sends an
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* IPI to hartY.
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*/
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u32 hartid = current_hartid();
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u32 word_index = hartid / 4;
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u32 per_hart_offset = PLICSW_PENDING_STRIDE * hartid;
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u32 val = 1 << target_hart << per_hart_offset;
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writel(val, (void *)plicsw.addr + PLICSW_PENDING_BASE + word_index * 4);
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}
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static void plicsw_ipi_send(u32 target_hart)
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{
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if (plicsw.hart_count <= target_hart)
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ebreak();
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/* Set PLICSW IPI */
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plic_sw_pending(target_hart);
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}
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static void plicsw_ipi_clear(u32 target_hart)
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{
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if (plicsw.hart_count <= target_hart)
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ebreak();
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/* Clear PLICSW IPI */
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plicsw_claim();
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plicsw_complete();
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}
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static struct sbi_ipi_device plicsw_ipi = {
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.name = "andes_plicsw",
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.ipi_send = plicsw_ipi_send,
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.ipi_clear = plicsw_ipi_clear
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};
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int plicsw_warm_ipi_init(void)
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{
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u32 hartid = current_hartid();
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/* Clear PLICSW IPI */
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plicsw_ipi_clear(hartid);
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return 0;
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}
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int plicsw_cold_ipi_init(struct plicsw_data *plicsw)
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{
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int rc;
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/* Setup source priority */
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uint32_t *priority = (void *)plicsw->addr + PLICSW_PRIORITY_BASE;
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for (int i = 0; i < plicsw->hart_count; i++)
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writel(1, &priority[i]);
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/* Setup target enable */
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uint32_t enable_mask = PLICSW_HART_MASK;
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for (int i = 0; i < plicsw->hart_count; i++) {
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uint32_t *enable = (void *)plicsw->addr + PLICSW_ENABLE_BASE +
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PLICSW_ENABLE_STRIDE * i;
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writel(enable_mask, enable);
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writel(enable_mask, enable + 1);
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enable_mask <<= 1;
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}
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/* Add PLICSW region to the root domain */
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rc = sbi_domain_root_add_memrange(plicsw->addr, plicsw->size,
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PLICSW_REGION_ALIGN,
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SBI_DOMAIN_MEMREGION_MMIO);
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if (rc)
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return rc;
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sbi_ipi_set_device(&plicsw_ipi);
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return 0;
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}
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