mirror of
https://github.com/riscv-software-src/opensbi
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516161c46f
To support different handlers for different types of resets, we are adding a sbi_list of restart handlers. Instead of sbi_system_reset_set_device we use sbi_system_reset_add_device to reflect the actual meaning. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
66 lines
1.4 KiB
C
66 lines
1.4 KiB
C
/*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_system.h>
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#include <sbi_utils/sys/sifive_test.h>
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#define FINISHER_FAIL 0x3333
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#define FINISHER_PASS 0x5555
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#define FINISHER_RESET 0x7777
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static void *sifive_test_base;
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static int sifive_test_system_reset_check(u32 type, u32 reason)
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{
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switch (type) {
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case SBI_SRST_RESET_TYPE_SHUTDOWN:
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case SBI_SRST_RESET_TYPE_COLD_REBOOT:
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case SBI_SRST_RESET_TYPE_WARM_REBOOT:
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return 1;
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}
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return 0;
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}
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static void sifive_test_system_reset(u32 type, u32 reason)
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{
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/*
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* Tell the "finisher" that the simulation
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* was successful so that QEMU exits
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*/
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switch (type) {
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case SBI_SRST_RESET_TYPE_SHUTDOWN:
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if (reason == SBI_SRST_RESET_REASON_NONE)
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writew(FINISHER_PASS, sifive_test_base);
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else
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writew(FINISHER_FAIL, sifive_test_base);
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break;
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case SBI_SRST_RESET_TYPE_COLD_REBOOT:
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case SBI_SRST_RESET_TYPE_WARM_REBOOT:
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writew(FINISHER_RESET, sifive_test_base);
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break;
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}
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}
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static struct sbi_system_reset_device sifive_test_reset = {
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.name = "sifive_test",
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.system_reset_check = sifive_test_system_reset_check,
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.system_reset = sifive_test_system_reset
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};
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int sifive_test_init(unsigned long base)
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{
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sifive_test_base = (void *)base;
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sbi_system_reset_add_device(&sifive_test_reset);
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return 0;
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}
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