mirror of
				https://github.com/riscv-software-src/opensbi
				synced 2025-10-31 20:18:23 +00:00 
			
		
		
		
	Signed-off-by: Atish Patra <atish.patra@wdc.com> Acked-by: Anup Patel <anup.patel@wdc.com>
		
			
				
	
	
		
			46 lines
		
	
	
		
			773 B
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			46 lines
		
	
	
		
			773 B
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * SPDX-License-Identifier: BSD-2-Clause
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|  *
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|  * Copyright (c) 2019 Western Digital Corporation or its affiliates.
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|  *
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|  * Authors:
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|  *   Anup Patel <anup.patel@wdc.com>
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|  */
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| 
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| #include <sbi/riscv_barrier.h>
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| #include <sbi/riscv_locks.h>
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| 
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| int spin_lock_check(spinlock_t *lock)
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| {
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| 	return (lock->lock == __RISCV_SPIN_UNLOCKED) ? 0 : 1;
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| }
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| 
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| int spin_trylock(spinlock_t *lock)
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| {
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| 	int tmp = 1, busy;
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| 
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| 	__asm__ __volatile__(
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| 		"	amoswap.w %0, %2, %1\n" RISCV_ACQUIRE_BARRIER
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| 		: "=r"(busy), "+A"(lock->lock)
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| 		: "r"(tmp)
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| 		: "memory");
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| 
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| 	return !busy;
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| }
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| 
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| void spin_lock(spinlock_t *lock)
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| {
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| 	while (1) {
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| 		if (spin_lock_check(lock))
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| 			continue;
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| 
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| 		if (spin_trylock(lock))
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| 			break;
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| 	}
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| }
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| 
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| void spin_unlock(spinlock_t *lock)
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| {
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| 	__smp_store_release(&lock->lock, __RISCV_SPIN_UNLOCKED);
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| }
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