mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-03 21:48:45 +00:00
791704cd09
Each APLIC CLRIE register allows disabling 32 interrupt sources at
a time by writing -1 so no need to write CLRIE register separately
for each interrupt source.
Fixes: 99792653de29 ("lib: utils/irqchip: Add APLIC initialization library")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
283 lines
8.2 KiB
C
283 lines
8.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_error.h>
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#include <sbi_utils/irqchip/aplic.h>
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#define APLIC_MAX_IDC (1UL << 14)
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#define APLIC_MAX_SOURCE 1024
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#define APLIC_DOMAINCFG 0x0000
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#define APLIC_DOMAINCFG_IE (1 << 8)
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#define APLIC_DOMAINCFG_DM (1 << 2)
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#define APLIC_DOMAINCFG_BE (1 << 0)
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#define APLIC_SOURCECFG_BASE 0x0004
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#define APLIC_SOURCECFG_D (1 << 10)
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#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
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#define APLIC_SOURCECFG_SM_MASK 0x00000007
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#define APLIC_SOURCECFG_SM_INACTIVE 0x0
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#define APLIC_SOURCECFG_SM_DETACH 0x1
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#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
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#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
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#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6
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#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7
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#define APLIC_MMSICFGADDR 0x1bc0
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#define APLIC_MMSICFGADDRH 0x1bc4
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#define APLIC_SMSICFGADDR 0x1bc8
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#define APLIC_SMSICFGADDRH 0x1bcc
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#define APLIC_xMSICFGADDRH_L (1UL << 31)
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#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f
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#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24
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#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7
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#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20
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#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7
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#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16
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#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf
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#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12
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#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff
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#define APLIC_xMSICFGADDR_PPN_SHIFT 12
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#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
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((1UL << (__lhxs)) - 1)
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#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
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((1UL << (__lhxw)) - 1)
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#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
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((__lhxs))
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#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
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(APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
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APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
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#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
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((1UL << (__hhxw)) - 1)
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#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
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((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
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#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
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(APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
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APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
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#define APLIC_SETIP_BASE 0x1c00
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#define APLIC_SETIPNUM 0x1cdc
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#define APLIC_CLRIP_BASE 0x1d00
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#define APLIC_CLRIPNUM 0x1ddc
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#define APLIC_SETIE_BASE 0x1e00
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#define APLIC_SETIENUM 0x1edc
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#define APLIC_CLRIE_BASE 0x1f00
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#define APLIC_CLRIENUM 0x1fdc
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#define APLIC_SETIPNUM_LE 0x2000
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#define APLIC_SETIPNUM_BE 0x2004
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#define APLIC_TARGET_BASE 0x3004
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#define APLIC_TARGET_HART_IDX_SHIFT 18
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#define APLIC_TARGET_HART_IDX_MASK 0x3fff
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#define APLIC_TARGET_GUEST_IDX_SHIFT 12
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#define APLIC_TARGET_GUEST_IDX_MASK 0x3f
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#define APLIC_TARGET_IPRIO_MASK 0xff
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#define APLIC_TARGET_EIID_MASK 0x7ff
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#define APLIC_IDC_BASE 0x4000
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#define APLIC_IDC_SIZE 32
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#define APLIC_IDC_IDELIVERY 0x00
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#define APLIC_IDC_IFORCE 0x04
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#define APLIC_IDC_ITHRESHOLD 0x08
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#define APLIC_IDC_TOPI 0x18
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#define APLIC_IDC_TOPI_ID_SHIFT 16
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#define APLIC_IDC_TOPI_ID_MASK 0x3ff
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#define APLIC_IDC_TOPI_PRIO_MASK 0xff
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#define APLIC_IDC_CLAIMI 0x1c
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#define APLIC_DEFAULT_PRIORITY 1
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#define APLIC_DISABLE_IDELIVERY 0
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#define APLIC_ENABLE_IDELIVERY 1
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#define APLIC_DISABLE_ITHRESHOLD 1
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#define APLIC_ENABLE_ITHRESHOLD 0
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static void aplic_writel_msicfg(struct aplic_msicfg_data *msicfg,
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void *msicfgaddr, void *msicfgaddrH)
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{
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u32 val;
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unsigned long base_ppn;
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/* Check if MSI config is already locked */
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if (readl(msicfgaddrH) & APLIC_xMSICFGADDRH_L)
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return;
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/* Compute the MSI base PPN */
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base_ppn = msicfg->base_addr >> APLIC_xMSICFGADDR_PPN_SHIFT;
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base_ppn &= ~APLIC_xMSICFGADDR_PPN_HART(msicfg->lhxs);
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base_ppn &= ~APLIC_xMSICFGADDR_PPN_LHX(msicfg->lhxw, msicfg->lhxs);
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base_ppn &= ~APLIC_xMSICFGADDR_PPN_HHX(msicfg->hhxw, msicfg->hhxs);
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/* Write the lower MSI config register */
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writel((u32)base_ppn, msicfgaddr);
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/* Write the upper MSI config register */
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val = (((u64)base_ppn) >> 32) &
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APLIC_xMSICFGADDRH_BAPPN_MASK;
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val |= (msicfg->lhxw & APLIC_xMSICFGADDRH_LHXW_MASK)
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<< APLIC_xMSICFGADDRH_LHXW_SHIFT;
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val |= (msicfg->hhxw & APLIC_xMSICFGADDRH_HHXW_MASK)
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<< APLIC_xMSICFGADDRH_HHXW_SHIFT;
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val |= (msicfg->lhxs & APLIC_xMSICFGADDRH_LHXS_MASK)
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<< APLIC_xMSICFGADDRH_LHXS_SHIFT;
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val |= (msicfg->hhxs & APLIC_xMSICFGADDRH_HHXS_MASK)
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<< APLIC_xMSICFGADDRH_HHXS_SHIFT;
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writel(val, msicfgaddrH);
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}
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static int aplic_check_msicfg(struct aplic_msicfg_data *msicfg)
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{
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if (APLIC_xMSICFGADDRH_LHXS_MASK < msicfg->lhxs)
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return SBI_EINVAL;
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if (APLIC_xMSICFGADDRH_LHXW_MASK < msicfg->lhxw)
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return SBI_EINVAL;
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if (APLIC_xMSICFGADDRH_HHXS_MASK < msicfg->hhxs)
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return SBI_EINVAL;
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if (APLIC_xMSICFGADDRH_HHXW_MASK < msicfg->hhxw)
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return SBI_EINVAL;
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return 0;
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}
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int aplic_cold_irqchip_init(struct aplic_data *aplic)
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{
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int rc;
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u32 i, j, tmp;
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struct sbi_domain_memregion reg;
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struct aplic_delegate_data *deleg;
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u32 first_deleg_irq, last_deleg_irq;
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/* Sanity checks */
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if (!aplic ||
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!aplic->num_source || APLIC_MAX_SOURCE <= aplic->num_source ||
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APLIC_MAX_IDC <= aplic->num_idc)
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return SBI_EINVAL;
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if (aplic->targets_mmode && aplic->has_msicfg_mmode) {
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rc = aplic_check_msicfg(&aplic->msicfg_mmode);
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if (rc)
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return rc;
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}
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if (aplic->targets_mmode && aplic->has_msicfg_smode) {
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rc = aplic_check_msicfg(&aplic->msicfg_smode);
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if (rc)
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return rc;
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}
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/* Set domain configuration to 0 */
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writel(0, (void *)(aplic->addr + APLIC_DOMAINCFG));
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/* Disable all interrupts */
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for (i = 0; i <= aplic->num_source; i += 32)
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writel(-1U, (void *)(aplic->addr + APLIC_CLRIE_BASE +
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(i / 32) * sizeof(u32)));
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/* Set interrupt type and priority for all interrupts */
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for (i = 1; i <= aplic->num_source; i++) {
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/* Set IRQ source configuration to 0 */
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writel(0, (void *)(aplic->addr + APLIC_SOURCECFG_BASE +
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(i - 1) * sizeof(u32)));
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/* Set IRQ target hart index and priority to 1 */
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writel(APLIC_DEFAULT_PRIORITY, (void *)(aplic->addr +
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APLIC_TARGET_BASE +
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(i - 1) * sizeof(u32)));
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}
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/* Configure IRQ delegation */
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first_deleg_irq = -1U;
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last_deleg_irq = 0;
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for (i = 0; i < APLIC_MAX_DELEGATE; i++) {
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deleg = &aplic->delegate[i];
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if (!deleg->first_irq || !deleg->last_irq)
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continue;
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if (aplic->num_source < deleg->first_irq ||
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aplic->num_source < deleg->last_irq)
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continue;
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if (APLIC_SOURCECFG_CHILDIDX_MASK < deleg->child_index)
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continue;
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if (deleg->first_irq > deleg->last_irq) {
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tmp = deleg->first_irq;
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deleg->first_irq = deleg->last_irq;
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deleg->last_irq = tmp;
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}
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if (deleg->first_irq < first_deleg_irq)
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first_deleg_irq = deleg->first_irq;
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if (last_deleg_irq < deleg->last_irq)
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last_deleg_irq = deleg->last_irq;
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for (j = deleg->first_irq; j <= deleg->last_irq; j++)
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writel(APLIC_SOURCECFG_D | deleg->child_index,
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(void *)(aplic->addr + APLIC_SOURCECFG_BASE +
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(j - 1) * sizeof(u32)));
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}
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/* Default initialization of IDC structures */
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for (i = 0; i < aplic->num_idc; i++) {
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writel(0, (void *)(aplic->addr + APLIC_IDC_BASE +
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i * APLIC_IDC_SIZE + APLIC_IDC_IDELIVERY));
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writel(0, (void *)(aplic->addr + APLIC_IDC_BASE +
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i * APLIC_IDC_SIZE + APLIC_IDC_IFORCE));
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writel(APLIC_DISABLE_ITHRESHOLD, (void *)(aplic->addr +
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APLIC_IDC_BASE +
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(i * APLIC_IDC_SIZE) +
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APLIC_IDC_ITHRESHOLD));
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}
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/* MSI configuration */
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if (aplic->targets_mmode && aplic->has_msicfg_mmode) {
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aplic_writel_msicfg(&aplic->msicfg_mmode,
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(void *)(aplic->addr + APLIC_MMSICFGADDR),
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(void *)(aplic->addr + APLIC_MMSICFGADDRH));
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}
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if (aplic->targets_mmode && aplic->has_msicfg_smode) {
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aplic_writel_msicfg(&aplic->msicfg_smode,
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(void *)(aplic->addr + APLIC_SMSICFGADDR),
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(void *)(aplic->addr + APLIC_SMSICFGADDRH));
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}
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/*
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* Add APLIC region to the root domain if:
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* 1) It targets M-mode of any HART directly or via MSIs
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* 2) All interrupts are delegated to some child APLIC
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*/
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if (aplic->targets_mmode ||
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((first_deleg_irq < last_deleg_irq) &&
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(last_deleg_irq == aplic->num_source) &&
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(first_deleg_irq == 1))) {
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sbi_domain_memregion_init(aplic->addr, aplic->size,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE),
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®);
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rc = sbi_domain_root_add_memregion(®);
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if (rc)
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return rc;
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}
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return 0;
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}
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