mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-04 05:50:22 +00:00
e8bc1621c6
The serial driver regions used by OpenSBI should be marked as a shared read-write regions between M-mode and SU-mode as those are accessed by earlycon and the corresponding tty serial drivers running in 'S' mode. When the smepmp extension is enabled, PMP entries for these shared regions will get programmed. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
133 lines
3.0 KiB
C
133 lines
3.0 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 StarFive Technology Co., Ltd.
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*
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* Author: Jun Liang Tan <junliang.tan@linux.starfivetech.com>
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*/
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#include <sbi/sbi_domain.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi_utils/serial/cadence-uart.h>
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/* clang-format off */
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#define UART_REG_CTRL 0x00
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#define UART_REG_MODE 0x04
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#define UART_REG_IDR 0x0C
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#define UART_REG_BRGR 0x18
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#define UART_REG_CSR 0x2C
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#define UART_REG_RFIFO_TFIFO 0x30
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#define UART_REG_BDIVR 0x34
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#define UART_CTRL_RXRES 0x00000001
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#define UART_CTRL_TXRES 0x00000002
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#define UART_CTRL_RXEN 0x00000004
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#define UART_CTRL_RXDIS 0x00000008
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#define UART_CTRL_TXEN 0x00000010
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#define UART_CTRL_TXDIS 0x00000020
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#define UART_MODE_PAR_NONE 0x00000020 /* No parity set */
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#define UART_BRGR_CD_CLKDIVISOR 0x00000001 /* baud_sample = sel_clk */
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#define UART_CSR_REMPTY 0x00000002
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#define UART_CSR_TFUL 0x00000010
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/* clang-format on */
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static volatile void *uart_base;
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static u32 uart_in_freq;
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static u32 uart_baudrate;
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/*
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* Find minimum divisor divides in_freq to max_target_hz;
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* Based on SiFive UART driver (sifive-uart.c)
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*/
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static inline unsigned int uart_min_clk_divisor(uint64_t in_freq,
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uint64_t max_target_hz)
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{
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uint64_t quotient = (in_freq + max_target_hz - 1) / (max_target_hz);
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/* Avoid underflow */
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if (quotient == 0)
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return 0;
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else
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return quotient - 1;
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}
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static u32 get_reg(u32 offset)
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{
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return readl(uart_base + offset);
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}
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static void set_reg(u32 offset, u32 val)
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{
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writel(val, uart_base + offset);
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}
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static void cadence_uart_putc(char ch)
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{
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while (get_reg(UART_REG_CSR) & UART_CSR_TFUL)
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;
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set_reg(UART_REG_RFIFO_TFIFO, ch);
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}
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static int cadence_uart_getc(void)
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{
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u32 ret = get_reg(UART_REG_CSR);
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if (!(ret & UART_CSR_REMPTY))
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return get_reg(UART_REG_RFIFO_TFIFO);
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return -1;
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}
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static struct sbi_console_device cadence_console = {
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.name = "cadence_uart",
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.console_putc = cadence_uart_putc,
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.console_getc = cadence_uart_getc
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};
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int cadence_uart_init(unsigned long base, u32 in_freq, u32 baudrate)
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{
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uart_base = (volatile void *)base;
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uart_in_freq = in_freq;
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uart_baudrate = baudrate;
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/* Disable interrupts */
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set_reg(UART_REG_IDR, 0xFFFFFFFF);
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/* Disable TX RX */
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set_reg(UART_REG_CTRL, UART_CTRL_TXDIS | UART_CTRL_RXDIS);
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/* Configure baudrate */
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if (in_freq && baudrate) {
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set_reg(UART_REG_BRGR, UART_BRGR_CD_CLKDIVISOR);
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set_reg(UART_REG_BDIVR,
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uart_min_clk_divisor(in_freq, baudrate));
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}
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/* Software reset TX RX data path and enable TX RX */
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set_reg(UART_REG_CTRL, UART_CTRL_TXRES | UART_CTRL_RXRES
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| UART_CTRL_TXEN | UART_CTRL_RXEN);
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/*
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* Set:
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* 1 stop bit, bits[07:06] = 0x00,
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* no parity set, bits[05:03] = 0x100,
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* 8 bits character length, bits[02:01] = 0x00,
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* sel_clk = uart_clk, bit[0] = 0x0
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*/
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set_reg(UART_REG_MODE, UART_MODE_PAR_NONE);
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sbi_console_set_device(&cadence_console);
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return sbi_domain_root_add_memrange(base, PAGE_SIZE, PAGE_SIZE,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW));
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}
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