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	The CSR encoding for t-head c9xx cores is shared across all the platforms with these cores. So move header thead_c9xx.h to the thead subdir. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Acked-by: Guo Ren <guoren@kernel.org> Reviewed-by: Anup Patel <anup@brainfault.org>
		
			
				
	
	
		
			128 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			128 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| #ifndef __RISCV_THEAD_C9XX_ENCODING_H____
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| #define __RISCV_THEAD_C9XX_ENCODING_H____
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| 
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| /* T-HEAD C9xx M mode CSR.  */
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| #define THEAD_C9XX_CSR_MXSTATUS		0x7c0
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| #define THEAD_C9XX_CSR_MHCR		0x7c1
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| #define THEAD_C9XX_CSR_MCOR		0x7c2
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| #define THEAD_C9XX_CSR_MCCR2		0x7c3
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| #define THEAD_C9XX_CSR_MCER2		0x7c4
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| #define THEAD_C9XX_CSR_MHINT		0x7c5
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| #define THEAD_C9XX_CSR_MRMR		0x7c6
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| #define THEAD_C9XX_CSR_MRVBR		0x7c7
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| #define THEAD_C9XX_CSR_MCER		0x7c8
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| #define THEAD_C9XX_CSR_MCOUNTERWEN	0x7c9
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| #define THEAD_C9XX_CSR_MCOUNTERINTEN	0x7ca
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| #define THEAD_C9XX_CSR_MCOUNTEROF	0x7cb
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| #define THEAD_C9XX_CSR_MHINT2		0x7cc
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| #define THEAD_C9XX_CSR_MHINT3		0x7cd
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| #define THEAD_C9XX_CSR_MRADDR		0x7e0
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| #define THEAD_C9XX_CSR_MEXSTATUS	0x7e1
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| #define THEAD_C9XX_CSR_MNMICAUSE	0x7e2
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| #define THEAD_C9XX_CSR_MNMIPC		0x7e3
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| #define THEAD_C9XX_CSR_MHPMCR		0x7f0
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| #define THEAD_C9XX_CSR_MHPMSR		0x7f1
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| #define THEAD_C9XX_CSR_MHPMER		0x7f2
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| #define THEAD_C9XX_CSR_MSMPR		0x7f3
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| #define THEAD_C9XX_CSR_MTEECFG		0x7f4
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| #define THEAD_C9XX_CSR_MZONEID		0x7f5
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| #define THEAD_C9XX_CSR_ML2CPID		0x7f6
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| #define THEAD_C9XX_CSR_ML2WP		0x7f7
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| #define THEAD_C9XX_CSR_MDTCMCR		0x7f8
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| #define THEAD_C9XX_CSR_USP		0x7d1
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| #define THEAD_C9XX_CSR_MCINS		0x7d2
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| #define THEAD_C9XX_CSR_MCINDEX		0x7d3
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| #define THEAD_C9XX_CSR_MCDATA0		0x7d4
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| #define THEAD_C9XX_CSR_MCDATA1		0x7d5
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| #define THEAD_C9XX_CSR_MEICR		0x7d6
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| #define THEAD_C9XX_CSR_MEICR2		0x7d7
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| #define THEAD_C9XX_CSR_MBEADDR		0x7d8
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| #define THEAD_C9XX_CSR_MCPUID		0xfc0
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| #define THEAD_C9XX_CSR_MAPBADDR		0xfc1
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| #define THEAD_C9XX_CSR_MWMSR		0xfc2
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| #define THEAD_C9XX_CSR_MHALTCAUSE	0xfe0
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| #define THEAD_C9XX_CSR_MDBGINFO		0xfe1
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| #define THEAD_C9XX_CSR_MPCFIFO		0xfe2
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| 
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| /* T-HEAD C9xx S mode CSR.  */
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| #define THEAD_C9XX_CSR_SXSTATUS		0x5c0
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| #define THEAD_C9XX_CSR_SHCR		0x5c1
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| #define THEAD_C9XX_CSR_SCER2		0x5c2
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| #define THEAD_C9XX_CSR_SCER		0x5c3
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| #define THEAD_C9XX_CSR_SCOUNTERINTEN	0x5c4
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| #define THEAD_C9XX_CSR_SCOUNTEROF	0x5c5
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| #define THEAD_C9XX_CSR_SHINT		0x5c6
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| #define THEAD_C9XX_CSR_SHINT2		0x5c7
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| #define THEAD_C9XX_CSR_SHPMINHIBIT	0x5c8
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| #define THEAD_C9XX_CSR_SHPMCR		0x5c9
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| #define THEAD_C9XX_CSR_SHPMSR		0x5ca
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| #define THEAD_C9XX_CSR_SHPMER		0x5cb
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| #define THEAD_C9XX_CSR_SL2CPID		0x5cc
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| #define THEAD_C9XX_CSR_SL2WP		0x5cd
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| #define THEAD_C9XX_CSR_SBEADDR		0x5d0
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| #define THEAD_C9XX_CSR_SCYCLE		0x5e0
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| #define THEAD_C9XX_CSR_SHPMCOUNTER1	0x5e1
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| #define THEAD_C9XX_CSR_SHPMCOUNTER2	0x5e2
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| #define THEAD_C9XX_CSR_SHPMCOUNTER3	0x5e3
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| #define THEAD_C9XX_CSR_SHPMCOUNTER4	0x5e4
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| #define THEAD_C9XX_CSR_SHPMCOUNTER5	0x5e5
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| #define THEAD_C9XX_CSR_SHPMCOUNTER6	0x5e6
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| #define THEAD_C9XX_CSR_SHPMCOUNTER7	0x5e7
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| #define THEAD_C9XX_CSR_SHPMCOUNTER8	0x5e8
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| #define THEAD_C9XX_CSR_SHPMCOUNTER9	0x5e9
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| #define THEAD_C9XX_CSR_SHPMCOUNTER10	0x5ea
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| #define THEAD_C9XX_CSR_SHPMCOUNTER11	0x5eb
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| #define THEAD_C9XX_CSR_SHPMCOUNTER12	0x5ec
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| #define THEAD_C9XX_CSR_SHPMCOUNTER13	0x5ed
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| #define THEAD_C9XX_CSR_SHPMCOUNTER14	0x5ee
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| #define THEAD_C9XX_CSR_SHPMCOUNTER15	0x5ef
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| #define THEAD_C9XX_CSR_SHPMCOUNTER16	0x5f0
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| #define THEAD_C9XX_CSR_SHPMCOUNTER17	0x5f1
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| #define THEAD_C9XX_CSR_SHPMCOUNTER18	0x5f2
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| #define THEAD_C9XX_CSR_SHPMCOUNTER19	0x5f3
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| #define THEAD_C9XX_CSR_SHPMCOUNTER20	0x5f4
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| #define THEAD_C9XX_CSR_SHPMCOUNTER21	0x5f5
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| #define THEAD_C9XX_CSR_SHPMCOUNTER22	0x5f6
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| #define THEAD_C9XX_CSR_SHPMCOUNTER23	0x5f7
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| #define THEAD_C9XX_CSR_SHPMCOUNTER24	0x5f8
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| #define THEAD_C9XX_CSR_SHPMCOUNTER25	0x5f9
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| #define THEAD_C9XX_CSR_SHPMCOUNTER26	0x5fa
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| #define THEAD_C9XX_CSR_SHPMCOUNTER27	0x5fb
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| #define THEAD_C9XX_CSR_SHPMCOUNTER28	0x5fc
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| #define THEAD_C9XX_CSR_SHPMCOUNTER29	0x5fd
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| #define THEAD_C9XX_CSR_SHPMCOUNTER30	0x5fe
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| #define THEAD_C9XX_CSR_SHPMCOUNTER31	0x5ff
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| 
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| /* T-HEAD C9xx U mode CSR.  */
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| #define THEAD_C9XX_CSR_FXCR		0x800
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| 
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| /* T-HEAD C9xx MMU extentions.  */
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| #define THEAD_C9XX_CSR_SMIR		0x9c0
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| #define THEAD_C9XX_CSR_SMEL		0x9c1
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| #define THEAD_C9XX_CSR_SMEH		0x9c2
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| #define THEAD_C9XX_CSR_SMCIR		0x9c3
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| 
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| /* T-HEAD C9xx Security CSR(May be droped).  */
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| #define THEAD_C9XX_CSR_MEBR		0xbe0
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| #define THEAD_C9XX_CSR_NT_MSTATUS	0xbe1
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| #define THEAD_C9XX_CSR_NT_MIE		0xbe2
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| #define THEAD_C9XX_CSR_NT_MTVEC		0xbe3
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| #define THEAD_C9XX_CSR_NT_MTVT		0xbe4
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| #define THEAD_C9XX_CSR_NT_MEPC		0xbe5
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| #define THEAD_C9XX_CSR_NT_MCAUSE	0xbe6
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| #define THEAD_C9XX_CSR_NT_MIP		0xbe7
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| #define THEAD_C9XX_CSR_NT_MINTSTATE	0xbe8
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| #define THEAD_C9XX_CSR_NT_MXSTATUS	0xbe9
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| #define THEAD_C9XX_CSR_NT_MEBR		0xbea
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| #define THEAD_C9XX_CSR_NT_MSP		0xbeb
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| #define THEAD_C9XX_CSR_T_USP		0xbec
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| #define THEAD_C9XX_CSR_T_MDCR		0xbed
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| #define THEAD_C9XX_CSR_T_MPCR		0xbee
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| #define THEAD_C9XX_CSR_PMPTEECFG	0xbef
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| 
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| /* T-HEAD C9xx MIP CSR extension */
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| #define THEAD_C9XX_IRQ_PMU_OVF		17
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| #define THEAD_C9XX_MIP_MOIP		(_UL(1) << THEAD_C9XX_IRQ_PMU_OVF)
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| 
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| #endif
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