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				https://github.com/riscv-software-src/opensbi
				synced 2025-11-04 05:50:22 +00:00 
			
		
		
		
	This driver is for T-HEAD test chip, fpga. It could work with
all T-HEAD riscv processors: C9xx series.
example1: (Using io-regs for reset)
reset: reset-sample {
	compatible = "thead,reset-sample";
	plic-delegate = <0xff 0xd81ffffc>;
	entry-reg = <0xff 0xff019050>;
	entry-cnt = <4>;
	control-reg = <0xff 0xff015004>;
	control-val = <0x1c>;
	csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
};
example2: (Using csr-regs for reset)
reset: reset-sample {
	compatible = "thead,reset-sample";
	plic-delegate = <0xff 0xd81ffffc>;
	using-csr-reset;
	csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
		    0x3b0 0x3b1 0x3b2 0x3b3
		    0x3b4 0x3b5 0x3b6 0x3b7
		    0x3a0>;
};
example3: (Only delegate plic enable to S-mode)
reset: reset-sample {
	compatible = "thead,reset-sample";
	plic-delegate = <0xff 0xd81ffffc>;
};
After this patch, all T-HEAD c9xx would use platform/generic with fw_dynamic
as default:
CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make
The platform/thead will be deprecated.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
		
	
			
		
			
				
	
	
		
			48 lines
		
	
	
		
			771 B
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
			
		
		
	
	
			48 lines
		
	
	
		
			771 B
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
/*
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 * SPDX-License-Identifier: BSD-2-Clause
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 */
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#include <sbi/riscv_asm.h>
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#include "fdt_reset_thead.h"
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/*
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 * csrrs rd, csr, rs1
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 * |31   20|19   15|14   12|11  7|6       0|
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 *    csr     rs1     010     rd   1110011
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 */
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#define CSR_STUB	addi    x0, x0, 0
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	.option norvc
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	.align 3
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	.global __fdt_reset_thead_csrr
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__fdt_reset_thead_csrr:
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	csrrs a0, 0, x0
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	ret
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	.align 3
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	.global __thead_pre_start_warm
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__thead_pre_start_warm:
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	/*
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	 * Clear L1 cache & BTB & BHT ...
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	 */
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	li	t1, 0x70013
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	csrw	0x7c2, t1
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	fence rw,rw
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	lla	t1, custom_csr
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	.global __reset_thead_csr_stub
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__reset_thead_csr_stub:
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.rept	MAX_CUSTOM_CSR
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	REG_L	t2, 8(t1)
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	CSR_STUB
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	addi	t1, t1, 16
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.endr
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	/*
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	 * Clear L1 cache & BTB & BHT ...
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	 */
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	li	t1, 0x70013
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	csrw	0x7c2, t1
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	fence rw,rw
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	j _start_warm
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