mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-03 21:48:45 +00:00
59a08cd7d6
Add the M-mode readable/writable flags to mmio regions of various drivers. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org>
330 lines
7.5 KiB
C
330 lines
7.5 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_hartmask.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_irqchip.h>
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#include <sbi/sbi_error.h>
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#include <sbi_utils/irqchip/imsic.h>
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#define IMSIC_MMIO_PAGE_LE 0x00
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#define IMSIC_MMIO_PAGE_BE 0x04
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#define IMSIC_MIN_ID 63
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#define IMSIC_MAX_ID 2047
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#define IMSIC_EIDELIVERY 0x70
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#define IMSIC_EITHRESHOLD 0x72
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#define IMSIC_TOPEI 0x76
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#define IMSIC_TOPEI_ID_SHIFT 16
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#define IMSIC_TOPEI_ID_MASK 0x7ff
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#define IMSIC_TOPEI_PRIO_MASK 0x7ff
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#define IMSIC_EIP0 0x80
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#define IMSIC_EIP63 0xbf
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#define IMSIC_EIPx_BITS 32
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#define IMSIC_EIE0 0xc0
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#define IMSIC_EIE63 0xff
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#define IMSIC_EIEx_BITS 32
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#define IMSIC_DISABLE_EIDELIVERY 0
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#define IMSIC_ENABLE_EIDELIVERY 1
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#define IMSIC_DISABLE_EITHRESHOLD 1
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#define IMSIC_ENABLE_EITHRESHOLD 0
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#define IMSIC_IPI_ID 1
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#define imsic_csr_write(__c, __v) \
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do { \
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csr_write(CSR_MISELECT, __c); \
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csr_write(CSR_MIREG, __v); \
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} while (0)
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#define imsic_csr_read(__c) \
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({ \
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unsigned long __v; \
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csr_write(CSR_MISELECT, __c); \
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__v = csr_read(CSR_MIREG); \
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__v; \
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})
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#define imsic_csr_set(__c, __v) \
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do { \
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csr_write(CSR_MISELECT, __c); \
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csr_set(CSR_MIREG, __v); \
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} while (0)
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#define imsic_csr_clear(__c, __v) \
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do { \
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csr_write(CSR_MISELECT, __c); \
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csr_clear(CSR_MIREG, __v); \
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} while (0)
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static struct imsic_data *imsic_hartid2data[SBI_HARTMASK_MAX_BITS];
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static int imsic_hartid2file[SBI_HARTMASK_MAX_BITS];
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int imsic_map_hartid_to_data(u32 hartid, struct imsic_data *imsic, int file)
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{
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if (!imsic || !imsic->targets_mmode ||
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(SBI_HARTMASK_MAX_BITS <= hartid))
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return SBI_EINVAL;
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imsic_hartid2data[hartid] = imsic;
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imsic_hartid2file[hartid] = file;
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return 0;
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}
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struct imsic_data *imsic_get_data(u32 hartid)
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{
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if (SBI_HARTMASK_MAX_BITS <= hartid)
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return NULL;
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return imsic_hartid2data[hartid];
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}
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int imsic_get_target_file(u32 hartid)
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{
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if ((SBI_HARTMASK_MAX_BITS <= hartid) ||
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!imsic_hartid2data[hartid])
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return SBI_ENOENT;
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return imsic_hartid2file[hartid];
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}
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static int imsic_external_irqfn(struct sbi_trap_regs *regs)
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{
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ulong mirq;
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while ((mirq = csr_swap(CSR_MTOPEI, 0))) {
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mirq = (mirq >> IMSIC_TOPEI_ID_SHIFT);
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switch (mirq) {
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case IMSIC_IPI_ID:
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sbi_ipi_process();
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break;
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default:
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sbi_printf("%s: unhandled IRQ%d\n",
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__func__, (u32)mirq);
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break;
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}
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}
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return 0;
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}
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static void imsic_ipi_send(u32 target_hart)
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{
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unsigned long reloff;
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struct imsic_regs *regs;
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struct imsic_data *data = imsic_hartid2data[target_hart];
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int file = imsic_hartid2file[target_hart];
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if (!data || !data->targets_mmode)
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return;
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regs = &data->regs[0];
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reloff = file * (1UL << data->guest_index_bits) * IMSIC_MMIO_PAGE_SZ;
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while (regs->size && (regs->size <= reloff)) {
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reloff -= regs->size;
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regs++;
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}
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if (regs->size && (reloff < regs->size))
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writel(IMSIC_IPI_ID,
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(void *)(regs->addr + reloff + IMSIC_MMIO_PAGE_LE));
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}
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static struct sbi_ipi_device imsic_ipi_device = {
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.name = "aia-imsic",
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.ipi_send = imsic_ipi_send
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};
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static void imsic_local_eix_update(unsigned long base_id,
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unsigned long num_id, bool pend, bool val)
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{
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unsigned long i, isel, ireg;
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unsigned long id = base_id, last_id = base_id + num_id;
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while (id < last_id) {
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isel = id / __riscv_xlen;
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isel *= __riscv_xlen / IMSIC_EIPx_BITS;
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isel += (pend) ? IMSIC_EIP0 : IMSIC_EIE0;
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ireg = 0;
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for (i = id & (__riscv_xlen - 1);
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(id < last_id) && (i < __riscv_xlen); i++) {
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ireg |= BIT(i);
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id++;
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}
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if (val)
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imsic_csr_set(isel, ireg);
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else
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imsic_csr_clear(isel, ireg);
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}
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}
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void imsic_local_irqchip_init(void)
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{
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/*
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* This function is expected to be called from:
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* 1) nascent_init() platform callback which is called
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* very early on each HART in boot-up path and and
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* HSM resume path.
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* 2) irqchip_init() platform callback which is called
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* in boot-up path.
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*/
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/* Setup threshold to allow all enabled interrupts */
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imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD);
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/* Enable interrupt delivery */
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imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY);
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/* Enable IPI */
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imsic_local_eix_update(IMSIC_IPI_ID, 1, false, true);
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}
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int imsic_warm_irqchip_init(void)
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{
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struct imsic_data *imsic = imsic_hartid2data[current_hartid()];
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/* Sanity checks */
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if (!imsic || !imsic->targets_mmode)
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return SBI_EINVAL;
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/* Disable all interrupts */
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imsic_local_eix_update(1, imsic->num_ids, false, false);
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/* Clear IPI pending */
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imsic_local_eix_update(IMSIC_IPI_ID, 1, true, false);
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/* Local IMSIC initialization */
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imsic_local_irqchip_init();
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return 0;
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}
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int imsic_data_check(struct imsic_data *imsic)
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{
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u32 i, tmp;
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unsigned long base_addr, addr, mask;
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/* Sanity checks */
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if (!imsic ||
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(imsic->num_ids < IMSIC_MIN_ID) ||
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(IMSIC_MAX_ID < imsic->num_ids))
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return SBI_EINVAL;
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tmp = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT;
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if (tmp < imsic->guest_index_bits)
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return SBI_EINVAL;
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tmp = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT -
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imsic->guest_index_bits;
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if (tmp < imsic->hart_index_bits)
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return SBI_EINVAL;
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tmp = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT -
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imsic->guest_index_bits - imsic->hart_index_bits;
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if (tmp < imsic->group_index_bits)
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return SBI_EINVAL;
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tmp = IMSIC_MMIO_PAGE_SHIFT + imsic->guest_index_bits +
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imsic->hart_index_bits;
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if (imsic->group_index_shift < tmp)
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return SBI_EINVAL;
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tmp = imsic->group_index_bits + imsic->group_index_shift - 1;
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if (tmp >= BITS_PER_LONG)
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return SBI_EINVAL;
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/*
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* Number of interrupt identities should be 1 less than
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* multiple of 63
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*/
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if ((imsic->num_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)
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return SBI_EINVAL;
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/* We should have at least one regset */
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if (!imsic->regs[0].size)
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return SBI_EINVAL;
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/* Match patter of each regset */
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base_addr = imsic->regs[0].addr;
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base_addr &= ~((1UL << (imsic->guest_index_bits +
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imsic->hart_index_bits +
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IMSIC_MMIO_PAGE_SHIFT)) - 1);
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base_addr &= ~(((1UL << imsic->group_index_bits) - 1) <<
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imsic->group_index_shift);
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for (i = 0; i < IMSIC_MAX_REGS && imsic->regs[i].size; i++) {
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mask = (1UL << imsic->guest_index_bits) * IMSIC_MMIO_PAGE_SZ;
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mask -= 1UL;
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if (imsic->regs[i].size & mask)
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return SBI_EINVAL;
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addr = imsic->regs[i].addr;
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addr &= ~((1UL << (imsic->guest_index_bits +
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imsic->hart_index_bits +
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IMSIC_MMIO_PAGE_SHIFT)) - 1);
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addr &= ~(((1UL << imsic->group_index_bits) - 1) <<
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imsic->group_index_shift);
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if (base_addr != addr)
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return SBI_EINVAL;
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}
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return 0;
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}
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int imsic_cold_irqchip_init(struct imsic_data *imsic)
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{
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int i, rc;
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struct sbi_domain_memregion reg;
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/* Sanity checks */
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rc = imsic_data_check(imsic);
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if (rc)
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return rc;
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/* We only initialize M-mode IMSIC */
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if (!imsic->targets_mmode)
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return SBI_EINVAL;
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/* Setup external interrupt function for IMSIC */
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sbi_irqchip_set_irqfn(imsic_external_irqfn);
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/* Add IMSIC regions to the root domain */
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for (i = 0; i < IMSIC_MAX_REGS && imsic->regs[i].size; i++) {
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sbi_domain_memregion_init(imsic->regs[i].addr,
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imsic->regs[i].size,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE),
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®);
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rc = sbi_domain_root_add_memregion(®);
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if (rc)
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return rc;
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}
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/* Register IPI device */
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sbi_ipi_set_device(&imsic_ipi_device);
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return 0;
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}
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