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The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
29 lines
430 B
Plaintext
29 lines
430 B
Plaintext
# SPDX-License-Identifier: BSD-2-Clause
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menu "HSM Device Support"
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config FDT_HSM
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bool "FDT based HSM drivers"
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depends on FDT
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default n
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if FDT_HSM
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config FDT_HSM_RPMI
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bool "FDT RPMI HSM driver"
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depends on FDT_MAILBOX && RPMI_MAILBOX
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default n
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config FDT_HSM_SIFIVE_TMC0
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bool "FDT SiFive TMC v0 driver"
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depends on FDT_CACHE
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default n
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config FDT_HSM_SPACEMIT
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bool "FDT SPACEMIT HSM driver"
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default n
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endif
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endmenu
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