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The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
24 lines
422 B
Plaintext
24 lines
422 B
Plaintext
# SPDX-License-Identifier: BSD-2-Clause
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menu "System Suspend Support"
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config FDT_SUSPEND
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bool "FDT based suspend drivers"
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depends on FDT
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default n
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if FDT_SUSPEND
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config FDT_SUSPEND_RPMI
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bool "FDT RPMI suspend driver"
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depends on FDT_MAILBOX && RPMI_MAILBOX
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default n
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config FDT_SUSPEND_SIFIVE_SMC0
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bool "FDT SIFIVE SMC0 suspend driver"
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depends on FDT_HSM_SIFIVE_TMC0 && IRQCHIP_APLIC
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default n
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endif
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endmenu
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