mirror of
https://github.com/riscv-software-src/opensbi
synced 2025-11-03 21:48:45 +00:00
10baa64c02
Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
115 lines
3.1 KiB
C
115 lines
3.1 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __RISCV_IO_H__
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#define __RISCV_IO_H__
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#include <sbi/riscv_barrier.h>
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#include <sbi/sbi_types.h>
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static inline void __raw_writeb(u8 val, volatile void *addr)
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{
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asm volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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static inline void __raw_writew(u16 val, volatile void *addr)
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{
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asm volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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static inline void __raw_writel(u32 val, volatile void *addr)
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{
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asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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#if __riscv_xlen != 32
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static inline void __raw_writeq(u64 val, volatile void *addr)
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{
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asm volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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#endif
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static inline u8 __raw_readb(const volatile void *addr)
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{
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u8 val;
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asm volatile("lb %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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static inline u16 __raw_readw(const volatile void *addr)
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{
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u16 val;
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asm volatile("lh %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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static inline u32 __raw_readl(const volatile void *addr)
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{
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u32 val;
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asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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#if __riscv_xlen != 32
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static inline u64 __raw_readq(const volatile void *addr)
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{
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u64 val;
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asm volatile("ld %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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#endif
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/* FIXME: These are now the same as asm-generic */
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/* clang-format off */
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#define __io_rbr() do {} while (0)
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#define __io_rar() do {} while (0)
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#define __io_rbw() do {} while (0)
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#define __io_raw() do {} while (0)
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#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; })
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#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; })
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#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; })
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#define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); })
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#define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); })
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#define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); })
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#if __riscv_xlen != 32
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#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; })
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#define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); })
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#endif
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#define __io_br() do {} while (0)
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#define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory");
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#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
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#define __io_aw() do {} while (0)
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#define readb(c) ({ u8 __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; })
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#define readw(c) ({ u16 __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; })
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#define readl(c) ({ u32 __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; })
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#define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); })
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#define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); })
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#define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); })
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#if __riscv_xlen != 32
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#define readq(c) ({ u64 __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; })
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#define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); })
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#endif
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/* clang-format on */
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#endif
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