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ram: sun20i_d1: Fix DRAM init with caches enabled

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On D1/D1s, the boot ROM enables the data cache, and it is left enabled
throughout SPL. Some DRAM controller settings affect the mapping of the
CPU address space, so the data cache must be flushed when changing them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland 2023-12-09 11:53:39 -06:00
parent 6b5d53a885
commit 00ed9c9999
1 changed files with 3 additions and 0 deletions
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3
drivers/ram/sunxi/dram_sun20i_d1.c
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@ -14,6 +14,7 @@
#include <asm/io.h> #include <asm/io.h>
#include <config.h> #include <config.h>
#include <cpu_func.h>
#ifdef CONFIG_RAM #ifdef CONFIG_RAM
#include <dm.h> #include <dm.h>
#include <ram.h> #include <ram.h>
@ -1098,6 +1099,7 @@ static int auto_scan_dram_size(const dram_para_t *para, dram_config_t *config)
/* Set bank mode for current rank */ /* Set bank mode for current rank */
clrsetbits_le32(mc_work_mode, 0xffc, 0x6a4); clrsetbits_le32(mc_work_mode, 0xffc, 0x6a4);
udelay(1); udelay(1);
flush_dcache_all();
// Test if bit A23 is BA2 or mirror XXX A22? // Test if bit A23 is BA2 or mirror XXX A22?
chk = CFG_SYS_SDRAM_BASE + (1U << 11); chk = CFG_SYS_SDRAM_BASE + (1U << 11);
@ -1126,6 +1128,7 @@ static int auto_scan_dram_size(const dram_para_t *para, dram_config_t *config)
/* Set page mode for current rank */ /* Set page mode for current rank */
clrsetbits_le32(mc_work_mode, 0xffc, 0xaa0); clrsetbits_le32(mc_work_mode, 0xffc, 0xaa0);
udelay(1); udelay(1);
flush_dcache_all();
// Scan per address line, until address wraps (i.e. see shadow) // Scan per address line, until address wraps (i.e. see shadow)
for (i = 9; i < 14; i++) { for (i = 9; i < 14; i++) {