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Remove unwanted ';' at end of define.

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Currently this is not creating any problem. But it will result
in compilation error when used as below.

printf("CFG_SDRAM_CFG2 - %08x\n", CFG_SDRAM_CFG2);

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>

continuation of the theme based on git grep "^#define CFG_.*;$" include/

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Selvamuthukumar 2008-10-08 18:12:20 -05:00 committed by Wolfgang Denk
parent b2934a5665
commit 03e2dbb18e
7 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/configs/EB+MCF-EV123.h
View File

@ -252,7 +252,7 @@
#define CFG_PEHLPAR 0xC0 #define CFG_PEHLPAR 0xC0
#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
#define CFG_DDRUA 0x05 #define CFG_DDRUA 0x05
#define CFG_PJPAR 0xFF; #define CFG_PJPAR 0xFF
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* CCM configuration * CCM configuration

4
include/configs/M5272C3.h
View File

@ -156,8 +156,8 @@
* You should know what you are doing if you make changes here. * You should know what you are doing if you make changes here.
*/ */
#define CFG_MBAR 0x10000000 /* Register Base Addrs */ #define CFG_MBAR 0x10000000 /* Register Base Addrs */
#define CFG_SCR 0x0003; #define CFG_SCR 0x0003
#define CFG_SPR 0xffff; #define CFG_SPR 0xffff
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM) * Definitions for initial stack pointer and data area (in DPRAM)

2
include/configs/M5282EVB.h
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@ -246,6 +246,6 @@
#define CFG_PEHLPAR 0xC0 #define CFG_PEHLPAR 0xC0
#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
#define CFG_DDRUA 0x05 #define CFG_DDRUA 0x05
#define CFG_PJPAR 0xFF; #define CFG_PJPAR 0xFF
#endif /* _CONFIG_M5282EVB_H */ #endif /* _CONFIG_M5282EVB_H */

4
include/configs/MPC8313ERDB.h
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@ -153,12 +153,12 @@
| SDRAM_CFG_32_BE ) | SDRAM_CFG_32_BE )
/* 0x43080000 */ /* 0x43080000 */
#endif #endif
#define CFG_SDRAM_CFG2 0x00401000; #define CFG_SDRAM_CFG2 0x00401000
/* set burst length to 8 for 32-bit data path */ /* set burst length to 8 for 32-bit data path */
#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ #define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
/* 0x44480632 */ /* 0x44480632 */
#define CFG_DDR_MODE_2 0x8000C000; #define CFG_DDR_MODE_2 0x8000C000
#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/*0x02000000*/ /*0x02000000*/

2
include/configs/MPC837XERDB.h
View File

@ -207,7 +207,7 @@
#define CFG_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ #define CFG_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
| (0x0442 << SDRAM_MODE_SD_SHIFT)) | (0x0442 << SDRAM_MODE_SD_SHIFT))
/* 0x04400442 */ /* DDR400 */ /* 0x04400442 */ /* DDR400 */
#define CFG_DDR_MODE2 0x00000000; #define CFG_DDR_MODE2 0x00000000
/* /*
* Memory test * Memory test

4
include/configs/cobra5272.h
View File

@ -262,8 +262,8 @@ from which user programs will be started */
* --- * ---
*/ */
#define CFG_SCR 0x0003; #define CFG_SCR 0x0003
#define CFG_SPR 0xffff; #define CFG_SPR 0xffff
/* --- /* ---
* Ethernet settings * Ethernet settings

6
include/configs/spc1920.h
View File

@ -374,7 +374,7 @@
#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \ #define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
BR_MS_UPMA | \ BR_MS_UPMA | \
BR_PS_16 | \ BR_PS_16 | \
BR_V); BR_V)
#define CFG_MAMR (MAMR_GPL_A4DIS | \ #define CFG_MAMR (MAMR_GPL_A4DIS | \
MAMR_RLFA_5X | \ MAMR_RLFA_5X | \
@ -405,7 +405,7 @@
OR_SCY_4_CLK | \ OR_SCY_4_CLK | \
OR_TRLX) OR_TRLX)
#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); #define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
/* /*
* PLD CS5 * PLD CS5
@ -420,7 +420,7 @@
OR_SCY_0_CLK | \ OR_SCY_0_CLK | \
OR_TRLX) OR_TRLX)
#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); #define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
/* /*
* Internal Definitions * Internal Definitions