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OMAP3: workaround for ARM Cortex-A8 erratum 725233

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725233: PLD instructions executed with PLD data forwarding
enabled can result in a processor deadlock

This deadlock can happen when NEON load instructions are used together
with cache preload instructions (PLD). The problematic conditions
can be triggered in-the-wild by NEON optimized functions from pixman
library (http://cgit.freedesktop.org/pixman), which perform dynamic
adjustment of prefetch distance.

The workaround disables PLD data forwarding by setting PLD_FWD bit
in L2 Cache Auxiliary Control Register as recommended in ARM Cortex-A8
errata list.

The deadlock can only happen on r1pX revisions of Cortex-A8 (used in
OMAP34xx/OMAP35xx). Performance impact of the workaround is practically
non-existant.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Siarhei Siamashka 2010-02-23 23:56:36 -05:00 committed by Tom Rix
parent 7c966a8bdf
commit 041d42e789
1 changed files with 6 additions and 0 deletions
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6
cpu/arm_cortexa8/omap3/board.c
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@ -146,6 +146,12 @@ void setup_auxcr()
__asm__ __volatile__("orr r0, r0, #1 << 5"); __asm__ __volatile__("orr r0, r0, #1 << 5");
/* SMI instruction to call ROM Code API */ /* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070"); __asm__ __volatile__(".word 0xE1600070");
/* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */
__asm__ __volatile__("mov r12, #0x2");
__asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2");
__asm__ __volatile__("orr r0, r0, #1 << 27");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
__asm__ __volatile__("mov r0, %0":"=r"(i)); __asm__ __volatile__("mov r0, %0":"=r"(i));
__asm__ __volatile__("mov r12, %0":"=r"(j)); __asm__ __volatile__("mov r12, %0":"=r"(j));
} }