mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-26 22:01:10 +00:00
ARM: dts: uniphier: Sync DT with Linux v6.2
Synchronize devicetree sources with Linux v6.2. - Use GIC interrupt definitions - Add reg properties in USB-glue and SoC-glue node - Fix node names to follow the generic names list in DT specification - Add L2 cache and AHCI nodes - Update nand and pcie nodes - And some trivial fixes Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Kunihiko Hayashi
Tom Rini
parent
e800263d56
commit
051451ad83
@ -164,4 +164,8 @@
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&nand {
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status = "okay";
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nand@0 {
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reg = <0>;
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};
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};
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@ -39,11 +39,11 @@
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};
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ðsc {
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interrupts = <0 8>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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};
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&serialsc {
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interrupts = <0 8>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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};
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&serial0 {
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@ -51,7 +51,7 @@
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};
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&gpio {
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xirq0 {
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xirq0-hog {
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gpio-hog;
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gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
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input;
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@ -7,6 +7,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "socionext,uniphier-ld11";
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@ -35,6 +36,7 @@
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reg = <0 0x000>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cluster0_opp>;
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};
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@ -44,8 +46,13 @@
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reg = <0 0x001>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cluster0_opp>;
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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cluster0_opp: opp-table {
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@ -102,10 +109,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 4>,
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<1 14 4>,
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<1 11 4>,
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<1 10 4>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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reserved-memory {
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@ -131,7 +138,7 @@
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reg = <0x54006000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 39 4>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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@ -144,7 +151,7 @@
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reg = <0x54006100 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 216 4>;
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interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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clocks = <&peri_clk 12>;
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@ -155,7 +162,7 @@
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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@ -166,7 +173,7 @@
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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@ -177,7 +184,7 @@
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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@ -188,7 +195,7 @@
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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@ -223,7 +230,7 @@
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audio@56000000 {
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compatible = "socionext,uniphier-ld11-aio";
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reg = <0x56000000 0x80000>;
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interrupts = <0 144 4>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_aout1>,
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<&pinctrl_aoutiec1>;
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@ -306,12 +313,12 @@
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};
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};
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adamv@57920000 {
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syscon@57920000 {
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compatible = "socionext,uniphier-ld11-adamv",
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"simple-mfd", "syscon";
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reg = <0x57920000 0x1000>;
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adamv_rst: reset {
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adamv_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-adamv-reset";
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#reset-cells = <1>;
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};
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@ -323,7 +330,7 @@
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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@ -337,7 +344,7 @@
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 4>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&peri_clk 5>;
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@ -350,7 +357,7 @@
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reg = <0x58782000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 4>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&peri_clk 6>;
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resets = <&peri_rst 6>;
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clock-frequency = <400000>;
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@ -362,7 +369,7 @@
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reg = <0x58783000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 4>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&peri_clk 7>;
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@ -376,7 +383,7 @@
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reg = <0x58784000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 45 4>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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clocks = <&peri_clk 8>;
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@ -389,7 +396,7 @@
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reg = <0x58785000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 25 4>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&peri_clk 9>;
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resets = <&peri_rst 9>;
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clock-frequency = <400000>;
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@ -410,28 +417,28 @@
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reg = <0x59801000 0x400>;
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};
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sdctrl@59810000 {
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syscon@59810000 {
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compatible = "socionext,uniphier-ld11-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x400>;
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sd_rst: reset {
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sd_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-sd-reset";
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#reset-cells = <1>;
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};
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};
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perictrl@59820000 {
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syscon@59820000 {
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compatible = "socionext,uniphier-ld11-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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peri_clk: clock {
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peri_clk: clock-controller {
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compatible = "socionext,uniphier-ld11-peri-clock";
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#clock-cells = <1>;
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};
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peri_rst: reset {
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peri_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-peri-reset";
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#reset-cells = <1>;
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};
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@ -440,7 +447,7 @@
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emmc: mmc@5a000000 {
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compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
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reg = <0x5a000000 0x400>;
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interrupts = <0 78 4>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc>;
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clocks = <&sys_clk 4>;
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@ -460,7 +467,7 @@
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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interrupts = <0 243 4>;
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
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@ -476,7 +483,7 @@
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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interrupts = <0 244 4>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
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@ -492,7 +499,7 @@
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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interrupts = <0 245 4>;
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interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
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@ -504,24 +511,24 @@
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has-transaction-translator;
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};
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mioctrl@5b3e0000 {
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syscon@5b3e0000 {
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compatible = "socionext,uniphier-ld11-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x5b3e0000 0x800>;
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mio_clk: clock {
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mio_clk: clock-controller {
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compatible = "socionext,uniphier-ld11-mio-clock";
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#clock-cells = <1>;
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};
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mio_rst: reset {
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mio_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-mio-reset";
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#reset-cells = <1>;
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resets = <&sys_rst 7>;
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};
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};
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soc_glue: soc-glue@5f800000 {
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soc_glue: syscon@5f800000 {
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compatible = "socionext,uniphier-ld11-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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@ -530,7 +537,7 @@
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compatible = "socionext,uniphier-ld11-pinctrl";
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};
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usb-phy {
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usb-hub {
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compatible = "socionext,uniphier-ld11-usb2-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -552,9 +559,10 @@
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};
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};
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soc-glue@5f900000 {
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syscon@5f900000 {
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compatible = "socionext,uniphier-ld11-soc-glue-debug",
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"simple-mfd";
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"simple-mfd", "syscon";
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reg = <0x5f900000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x5f900000 0x2000>;
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@ -573,7 +581,7 @@
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xdmac: dma-controller@5fc10000 {
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compatible = "socionext,uniphier-xdmac";
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reg = <0x5fc10000 0x5300>;
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interrupts = <0 188 4>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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dma-channels = <16>;
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#dma-cells = <2>;
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};
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@ -591,20 +599,20 @@
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<0x5fe40000 0x80000>; /* GICR */
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <1 9 4>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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sysctrl@61840000 {
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syscon@61840000 {
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compatible = "socionext,uniphier-ld11-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x10000>;
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sys_clk: clock {
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sys_clk: clock-controller {
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compatible = "socionext,uniphier-ld11-clock";
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#clock-cells = <1>;
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};
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sys_rst: reset {
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sys_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-reset";
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#reset-cells = <1>;
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};
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@ -618,7 +626,7 @@
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compatible = "socionext,uniphier-ld11-ave4";
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status = "disabled";
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reg = <0x65000000 0x8500>;
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interrupts = <0 66 4>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "ether";
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clocks = <&sys_clk 6>;
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reset-names = "ether";
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@ -638,7 +646,9 @@
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status = "disabled";
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reg-names = "nand_data", "denali_reg";
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reg = <0x68000000 0x20>, <0x68100000 0x1000>;
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interrupts = <0 65 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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clock-names = "nand", "nand_x", "ecc";
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@ -7,6 +7,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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@ -45,6 +46,7 @@
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reg = <0 0x000>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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next-level-cache = <&a72_l2>;
|
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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};
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@ -55,6 +57,7 @@
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reg = <0 0x001>;
|
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clocks = <&sys_clk 32>;
|
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enable-method = "psci";
|
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next-level-cache = <&a72_l2>;
|
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operating-points-v2 = <&cluster0_opp>;
|
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#cooling-cells = <2>;
|
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};
|
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@ -65,6 +68,7 @@
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reg = <0 0x100>;
|
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clocks = <&sys_clk 33>;
|
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enable-method = "psci";
|
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next-level-cache = <&a53_l2>;
|
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operating-points-v2 = <&cluster1_opp>;
|
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#cooling-cells = <2>;
|
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};
|
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@ -75,12 +79,21 @@
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reg = <0 0x101>;
|
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clocks = <&sys_clk 33>;
|
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enable-method = "psci";
|
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next-level-cache = <&a53_l2>;
|
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operating-points-v2 = <&cluster1_opp>;
|
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#cooling-cells = <2>;
|
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};
|
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|
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a72_l2: l2-cache0 {
|
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compatible = "cache";
|
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};
|
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|
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a53_l2: l2-cache1 {
|
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compatible = "cache";
|
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};
|
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};
|
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|
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cluster0_opp: opp-table0 {
|
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cluster0_opp: opp-table-0 {
|
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compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
@ -118,7 +131,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp-table1 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
@ -176,10 +189,10 @@
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 4>,
|
||||
<1 14 4>,
|
||||
<1 11 4>,
|
||||
<1 10 4>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
@ -236,7 +249,7 @@
|
||||
reg = <0x54006000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 39 4>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
@ -249,7 +262,7 @@
|
||||
reg = <0x54006100 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 216 4>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 12>;
|
||||
@ -262,7 +275,7 @@
|
||||
reg = <0x54006200 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 229 4>;
|
||||
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi2>;
|
||||
clocks = <&peri_clk 13>;
|
||||
@ -275,7 +288,7 @@
|
||||
reg = <0x54006300 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 230 4>;
|
||||
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi3>;
|
||||
clocks = <&peri_clk 14>;
|
||||
@ -286,7 +299,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
@ -297,7 +310,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
@ -308,7 +321,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
@ -319,7 +332,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 177 4>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
@ -348,7 +361,7 @@
|
||||
audio@56000000 {
|
||||
compatible = "socionext,uniphier-ld20-aio";
|
||||
reg = <0x56000000 0x80000>;
|
||||
interrupts = <0 144 4>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_aout1>,
|
||||
<&pinctrl_aoutiec1>;
|
||||
@ -431,12 +444,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
adamv@57920000 {
|
||||
syscon@57920000 {
|
||||
compatible = "socionext,uniphier-ld20-adamv",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x57920000 0x1000>;
|
||||
|
||||
adamv_rst: reset {
|
||||
adamv_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-ld20-adamv-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -448,7 +461,7 @@
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 4>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&peri_clk 4>;
|
||||
@ -462,7 +475,7 @@
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 4>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&peri_clk 5>;
|
||||
@ -475,7 +488,7 @@
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 6>;
|
||||
resets = <&peri_rst 6>;
|
||||
clock-frequency = <400000>;
|
||||
@ -487,7 +500,7 @@
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 4>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&peri_clk 7>;
|
||||
@ -501,7 +514,7 @@
|
||||
reg = <0x58784000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 45 4>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
clocks = <&peri_clk 8>;
|
||||
@ -514,7 +527,7 @@
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 9>;
|
||||
resets = <&peri_rst 9>;
|
||||
clock-frequency = <400000>;
|
||||
@ -535,33 +548,33 @@
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
sdctrl@59810000 {
|
||||
sdctrl: syscon@59810000 {
|
||||
compatible = "socionext,uniphier-ld20-sdctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x400>;
|
||||
|
||||
sd_clk: clock {
|
||||
sd_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-ld20-sd-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sd_rst: reset {
|
||||
sd_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-ld20-sd-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
syscon@59820000 {
|
||||
compatible = "socionext,uniphier-ld20-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
peri_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-ld20-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
peri_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-ld20-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -570,7 +583,7 @@
|
||||
emmc: mmc@5a000000 {
|
||||
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
|
||||
reg = <0x5a000000 0x400>;
|
||||
interrupts = <0 78 4>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&sys_clk 4>;
|
||||
@ -590,7 +603,7 @@
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x800>;
|
||||
interrupts = <0 76 4>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
clocks = <&sd_clk 0>;
|
||||
@ -598,9 +611,10 @@
|
||||
resets = <&sd_rst 0>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
socionext,syscon-uhs-mode = <&sdctrl 0>;
|
||||
};
|
||||
|
||||
soc_glue: soc-glue@5f800000 {
|
||||
soc_glue: syscon@5f800000 {
|
||||
compatible = "socionext,uniphier-ld20-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
@ -610,9 +624,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
|
||||
syscon@5f900000 {
|
||||
compatible = "socionext,uniphier-ld20-soc-glue-debug",
|
||||
"simple-mfd";
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f900000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x5f900000 0x2000>;
|
||||
@ -675,7 +690,7 @@
|
||||
xdmac: dma-controller@5fc10000 {
|
||||
compatible = "socionext,uniphier-xdmac";
|
||||
reg = <0x5fc10000 0x5300>;
|
||||
interrupts = <0 188 4>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
@ -693,20 +708,20 @@
|
||||
<0x5fe80000 0x80000>; /* GICR */
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <1 9 4>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
syscon@61840000 {
|
||||
compatible = "socionext,uniphier-ld20-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
sys_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-ld20-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
sys_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-ld20-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -715,9 +730,9 @@
|
||||
compatible = "socionext,uniphier-wdt";
|
||||
};
|
||||
|
||||
pvtctl: pvtctl {
|
||||
pvtctl: thermal-sensor {
|
||||
compatible = "socionext,uniphier-ld20-thermal";
|
||||
interrupts = <0 3 4>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
socionext,tmod-calibration = <0x0f22 0x68ee>;
|
||||
};
|
||||
@ -727,7 +742,7 @@
|
||||
compatible = "socionext,uniphier-ld20-ave4";
|
||||
status = "disabled";
|
||||
reg = <0x65000000 0x8500>;
|
||||
interrupts = <0 66 4>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ether_rgmii>;
|
||||
clock-names = "ether";
|
||||
@ -749,7 +764,7 @@
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host";
|
||||
interrupts = <0 134 4>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
|
||||
<&pinctrl_usb2>, <&pinctrl_usb3>;
|
||||
@ -762,14 +777,15 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
usb-controller@65b00000 {
|
||||
compatible = "socionext,uniphier-ld20-dwc3-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65b00000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb_rst: reset@0 {
|
||||
usb_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
@ -815,7 +831,7 @@
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb_hsphy0: hs-phy@200 {
|
||||
usb_hsphy0: phy@200 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -829,7 +845,7 @@
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb_hsphy1: hs-phy@210 {
|
||||
usb_hsphy1: phy@210 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -843,7 +859,7 @@
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb_hsphy2: hs-phy@220 {
|
||||
usb_hsphy2: phy@220 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-hsphy";
|
||||
reg = <0x220 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -857,7 +873,7 @@
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb_hsphy3: hs-phy@230 {
|
||||
usb_hsphy3: phy@230 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-hsphy";
|
||||
reg = <0x230 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -871,7 +887,7 @@
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb_ssphy0: ss-phy@300 {
|
||||
usb_ssphy0: phy@300 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -882,7 +898,7 @@
|
||||
vbus-supply = <&usb_vbus0>;
|
||||
};
|
||||
|
||||
usb_ssphy1: ss-phy@310 {
|
||||
usb_ssphy1: phy@310 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-ssphy";
|
||||
reg = <0x310 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -895,7 +911,7 @@
|
||||
};
|
||||
|
||||
pcie: pcie@66000000 {
|
||||
compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
|
||||
compatible = "socionext,uniphier-pcie";
|
||||
status = "disabled";
|
||||
reg-names = "dbi", "link", "config";
|
||||
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
|
||||
@ -915,7 +931,8 @@
|
||||
<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-names = "dma", "msi";
|
||||
interrupts = <0 224 4>, <0 225 4>;
|
||||
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
|
||||
<0 0 0 2 &pcie_intc 1>, /* INTB */
|
||||
@ -928,7 +945,7 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 226 4>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -948,7 +965,9 @@
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
|
||||
@ -36,11 +36,11 @@
|
||||
};
|
||||
|
||||
ðsc {
|
||||
interrupts = <1 8>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
&serialsc {
|
||||
interrupts = <1 8>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
@ -56,7 +56,7 @@
|
||||
};
|
||||
|
||||
&gpio {
|
||||
xirq1 {
|
||||
xirq1-hog {
|
||||
gpio-hog;
|
||||
gpios = <UNIPHIER_GPIO_IRQ(1) 0>;
|
||||
input;
|
||||
@ -81,4 +81,8 @@
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
#include <dt-bindings/gpio/uniphier-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-ld4";
|
||||
@ -55,7 +56,8 @@
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-size = <(512 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
@ -69,7 +71,7 @@
|
||||
reg = <0x54006000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 39 4>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
@ -80,7 +82,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
@ -91,7 +93,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
@ -102,7 +104,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
@ -113,7 +115,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 29 4>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
@ -140,7 +142,7 @@
|
||||
reg = <0x58400000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 1>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&peri_clk 4>;
|
||||
@ -154,7 +156,7 @@
|
||||
reg = <0x58480000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 1>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&peri_clk 5>;
|
||||
@ -168,7 +170,7 @@
|
||||
reg = <0x58500000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 1>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&peri_clk 6>;
|
||||
@ -182,7 +184,7 @@
|
||||
reg = <0x58580000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 1>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&peri_clk 7>;
|
||||
@ -205,33 +207,33 @@
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
mioctrl@59810000 {
|
||||
syscon@59810000 {
|
||||
compatible = "socionext,uniphier-ld4-mioctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x800>;
|
||||
|
||||
mio_clk: clock {
|
||||
mio_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-ld4-mio-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mio_rst: reset {
|
||||
mio_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-ld4-mio-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
syscon@59820000 {
|
||||
compatible = "socionext,uniphier-ld4-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
peri_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-ld4-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
peri_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-ld4-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -240,8 +242,13 @@
|
||||
dmac: dma-controller@5a000000 {
|
||||
compatible = "socionext,uniphier-mio-dmac";
|
||||
reg = <0x5a000000 0x1000>;
|
||||
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
|
||||
<0 71 4>, <0 72 4>, <0 73 4>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mio_clk 7>;
|
||||
resets = <&mio_rst 7>;
|
||||
#dma-cells = <1>;
|
||||
@ -251,7 +258,7 @@
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x200>;
|
||||
interrupts = <0 76 4>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
@ -271,7 +278,7 @@
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a500000 0x200>;
|
||||
interrupts = <0 78 4>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&mio_clk 1>;
|
||||
@ -289,7 +296,7 @@
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
|
||||
@ -303,7 +310,7 @@
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
|
||||
@ -317,7 +324,7 @@
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a820100 0x100>;
|
||||
interrupts = <0 82 4>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
|
||||
@ -327,7 +334,7 @@
|
||||
has-transaction-translator;
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
syscon@5f800000 {
|
||||
compatible = "socionext,uniphier-ld4-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
@ -337,9 +344,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
|
||||
syscon@5f900000 {
|
||||
compatible = "socionext,uniphier-ld4-soc-glue-debug",
|
||||
"simple-mfd";
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f900000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x5f900000 0x2000>;
|
||||
@ -358,14 +366,16 @@
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x104>;
|
||||
interrupts = <GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x104>;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
@ -384,17 +394,17 @@
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
syscon@61840000 {
|
||||
compatible = "socionext,uniphier-ld4-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
sys_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-ld4-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
sys_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-ld4-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -405,7 +415,9 @@
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
|
||||
@ -99,3 +99,11 @@
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ahci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ahci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -40,11 +40,11 @@
|
||||
};
|
||||
|
||||
ðsc {
|
||||
interrupts = <2 8>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
&serialsc {
|
||||
interrupts = <2 8>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
@ -60,7 +60,7 @@
|
||||
};
|
||||
|
||||
&gpio {
|
||||
xirq2 {
|
||||
xirq2-hog {
|
||||
gpio-hog;
|
||||
gpios = <UNIPHIER_GPIO_IRQ(2) 0>;
|
||||
input;
|
||||
@ -104,4 +104,16 @@
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ahci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ahci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -64,10 +64,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -76,6 +72,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
phy-handle = <ðphy>;
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
#include <dt-bindings/gpio/uniphier-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-pro4";
|
||||
@ -63,7 +64,8 @@
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-size = <(768 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
@ -77,7 +79,7 @@
|
||||
reg = <0x54006000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 39 4>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
@ -88,7 +90,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
@ -99,7 +101,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
@ -110,7 +112,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
@ -121,7 +123,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 177 4>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
@ -148,7 +150,7 @@
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 4>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&peri_clk 4>;
|
||||
@ -162,7 +164,7 @@
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 4>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&peri_clk 5>;
|
||||
@ -176,7 +178,7 @@
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&peri_clk 6>;
|
||||
@ -190,7 +192,7 @@
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 4>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&peri_clk 7>;
|
||||
@ -206,7 +208,7 @@
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 9>;
|
||||
resets = <&peri_rst 9>;
|
||||
clock-frequency = <400000>;
|
||||
@ -218,7 +220,7 @@
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 10>;
|
||||
resets = <&peri_rst 10>;
|
||||
clock-frequency = <400000>;
|
||||
@ -239,33 +241,33 @@
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
mioctrl@59810000 {
|
||||
mioctrl: syscon@59810000 {
|
||||
compatible = "socionext,uniphier-pro4-mioctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x800>;
|
||||
|
||||
mio_clk: clock {
|
||||
mio_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pro4-mio-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mio_rst: reset {
|
||||
mio_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pro4-mio-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
syscon@59820000 {
|
||||
compatible = "socionext,uniphier-pro4-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
peri_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pro4-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
peri_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pro4-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -274,8 +276,14 @@
|
||||
dmac: dma-controller@5a000000 {
|
||||
compatible = "socionext,uniphier-mio-dmac";
|
||||
reg = <0x5a000000 0x1000>;
|
||||
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
|
||||
<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mio_clk 7>;
|
||||
resets = <&mio_rst 7>;
|
||||
#dma-cells = <1>;
|
||||
@ -285,7 +293,7 @@
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x200>;
|
||||
interrupts = <0 76 4>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
@ -299,13 +307,14 @@
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
socionext,syscon-uhs-mode = <&mioctrl 0>;
|
||||
};
|
||||
|
||||
emmc: mmc@5a500000 {
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a500000 0x200>;
|
||||
interrupts = <0 78 4>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&mio_clk 1>;
|
||||
@ -323,7 +332,7 @@
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a600000 0x200>;
|
||||
interrupts = <0 85 4>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sd1>;
|
||||
clocks = <&mio_clk 2>;
|
||||
@ -339,7 +348,7 @@
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
|
||||
@ -355,7 +364,7 @@
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb3>;
|
||||
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
|
||||
@ -367,7 +376,7 @@
|
||||
has-transaction-translator;
|
||||
};
|
||||
|
||||
soc_glue: soc-glue@5f800000 {
|
||||
soc_glue: syscon@5f800000 {
|
||||
compatible = "socionext,uniphier-pro4-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
@ -376,7 +385,7 @@
|
||||
compatible = "socionext,uniphier-pro4-pinctrl";
|
||||
};
|
||||
|
||||
usb-phy {
|
||||
usb-hub {
|
||||
compatible = "socionext,uniphier-pro4-usb2-phy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -403,11 +412,17 @@
|
||||
vbus-supply = <&usb1_vbus>;
|
||||
};
|
||||
};
|
||||
|
||||
sg_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pro4-sg-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
|
||||
syscon@5f900000 {
|
||||
compatible = "socionext,uniphier-pro4-soc-glue-debug",
|
||||
"simple-mfd";
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f900000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x5f900000 0x2000>;
|
||||
@ -431,7 +446,7 @@
|
||||
xdmac: dma-controller@5fc10000 {
|
||||
compatible = "socionext,uniphier-xdmac";
|
||||
reg = <0x5fc10000 0x5300>;
|
||||
interrupts = <0 188 4>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
@ -446,14 +461,16 @@
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x304>;
|
||||
interrupts = <GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
@ -465,17 +482,17 @@
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
syscon@61840000 {
|
||||
compatible = "socionext,uniphier-pro4-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
sys_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pro4-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
sys_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pro4-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -485,7 +502,7 @@
|
||||
compatible = "socionext,uniphier-pro4-ave4";
|
||||
status = "disabled";
|
||||
reg = <0x65000000 0x8500>;
|
||||
interrupts = <0 66 4>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ether_rgmii>;
|
||||
clock-names = "gio", "ether", "ether-gb", "ether-phy";
|
||||
@ -503,12 +520,107 @@
|
||||
};
|
||||
};
|
||||
|
||||
ahci0: sata@65600000 {
|
||||
compatible = "socionext,uniphier-pro4-ahci",
|
||||
"generic-ahci";
|
||||
status = "disabled";
|
||||
reg = <0x65600000 0x10000>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sys_clk 12>, <&sys_clk 28>;
|
||||
resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>;
|
||||
ports-implemented = <1>;
|
||||
phys = <&ahci0_phy>;
|
||||
assigned-clocks = <&sg_clk 0>;
|
||||
assigned-clock-rates = <25000000>;
|
||||
};
|
||||
|
||||
sata-controller@65700000 {
|
||||
compatible = "socionext,uniphier-pxs2-ahci-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65700000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65700000 0x100>;
|
||||
|
||||
ahci0_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pro4-ahci-reset";
|
||||
reg = <0x0 0x4>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 28>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 28>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
ahci0_phy: phy@10 {
|
||||
compatible = "socionext,uniphier-pro4-ahci-phy";
|
||||
reg = <0x10 0x40>;
|
||||
clock-names = "link", "gio";
|
||||
clocks = <&sys_clk 28>, <&sys_clk 12>;
|
||||
reset-names = "link", "gio", "phy",
|
||||
"pm", "tx", "rx";
|
||||
resets = <&sys_rst 28>, <&sys_rst 12>,
|
||||
<&sys_rst 30>,
|
||||
<&ahci0_rst 0>, <&ahci0_rst 1>,
|
||||
<&ahci0_rst 2>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ahci1: sata@65800000 {
|
||||
compatible = "socionext,uniphier-pro4-ahci",
|
||||
"generic-ahci";
|
||||
status = "disabled";
|
||||
reg = <0x65800000 0x10000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sys_clk 12>, <&sys_clk 29>;
|
||||
resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>;
|
||||
ports-implemented = <1>;
|
||||
phys = <&ahci1_phy>;
|
||||
assigned-clocks = <&sg_clk 0>;
|
||||
assigned-clock-rates = <25000000>;
|
||||
};
|
||||
|
||||
sata-controller@65900000 {
|
||||
compatible = "socionext,uniphier-pro4-ahci-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65900000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65900000 0x100>;
|
||||
|
||||
ahci1_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pro4-ahci-reset";
|
||||
reg = <0x0 0x4>;
|
||||
clock-names = "gio", "link";
|
||||
clocks = <&sys_clk 12>, <&sys_clk 29>;
|
||||
reset-names = "gio", "link";
|
||||
resets = <&sys_rst 12>, <&sys_rst 29>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
ahci1_phy: phy@10 {
|
||||
compatible = "socionext,uniphier-pro4-ahci-phy";
|
||||
reg = <0x10 0x40>;
|
||||
clock-names = "link", "gio";
|
||||
clocks = <&sys_clk 29>, <&sys_clk 12>;
|
||||
reset-names = "link", "gio", "phy",
|
||||
"pm", "tx", "rx";
|
||||
resets = <&sys_rst 29>, <&sys_rst 12>,
|
||||
<&sys_rst 30>,
|
||||
<&ahci1_rst 0>, <&ahci1_rst 1>,
|
||||
<&ahci1_rst 2>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 134 4>, <0 135 4>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
@ -518,9 +630,10 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
usb-controller@65b00000 {
|
||||
compatible = "socionext,uniphier-pro4-dwc3-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65b00000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x100>;
|
||||
@ -534,7 +647,7 @@
|
||||
resets = <&sys_rst 12>, <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_ssphy: ss-phy@10 {
|
||||
usb0_ssphy: phy@10 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-ssphy";
|
||||
reg = <0x10 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -545,7 +658,7 @@
|
||||
vbus-supply = <&usb0_vbus>;
|
||||
};
|
||||
|
||||
usb0_rst: reset@40 {
|
||||
usb0_rst: reset-controller@40 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-reset";
|
||||
reg = <0x40 0x4>;
|
||||
#reset-cells = <1>;
|
||||
@ -561,7 +674,8 @@
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 137 4>, <0 138 4>;
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
@ -571,9 +685,10 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
usb-controller@65d00000 {
|
||||
compatible = "socionext,uniphier-pro4-dwc3-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65d00000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x100>;
|
||||
@ -587,7 +702,7 @@
|
||||
resets = <&sys_rst 12>, <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_rst: reset@40 {
|
||||
usb1_rst: reset-controller@40 {
|
||||
compatible = "socionext,uniphier-pro4-usb3-reset";
|
||||
reg = <0x40 0x4>;
|
||||
#reset-cells = <1>;
|
||||
@ -603,7 +718,9 @@
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
|
||||
@ -5,6 +5,8 @@
|
||||
// Copyright (C) 2015-2016 Socionext Inc.
|
||||
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-pro5";
|
||||
#address-cells = <1>;
|
||||
@ -135,7 +137,8 @@
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 190 4>, <0 191 4>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-size = <(2 * 1024 * 1024)>;
|
||||
cache-sets = <512>;
|
||||
@ -148,7 +151,8 @@
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
|
||||
<0x506c8000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-size = <(2 * 1024 * 1024)>;
|
||||
cache-sets = <512>;
|
||||
@ -162,7 +166,7 @@
|
||||
reg = <0x54006000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 39 4>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
@ -175,7 +179,7 @@
|
||||
reg = <0x54006100 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 216 4>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 11>; /* common with spi0 */
|
||||
@ -186,7 +190,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
@ -197,7 +201,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
@ -208,7 +212,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
@ -219,7 +223,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 177 4>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
@ -246,7 +250,7 @@
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 4>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&peri_clk 4>;
|
||||
@ -260,7 +264,7 @@
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 4>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&peri_clk 5>;
|
||||
@ -274,7 +278,7 @@
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&peri_clk 6>;
|
||||
@ -288,7 +292,7 @@
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 4>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&peri_clk 7>;
|
||||
@ -304,7 +308,7 @@
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 9>;
|
||||
resets = <&peri_rst 9>;
|
||||
clock-frequency = <400000>;
|
||||
@ -316,7 +320,7 @@
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 10>;
|
||||
resets = <&peri_rst 10>;
|
||||
clock-frequency = <400000>;
|
||||
@ -337,39 +341,39 @@
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
sdctrl@59810000 {
|
||||
sdctrl: syscon@59810000 {
|
||||
compatible = "socionext,uniphier-pro5-sdctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x400>;
|
||||
|
||||
sd_clk: clock {
|
||||
sd_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pro5-sd-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sd_rst: reset {
|
||||
sd_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pro5-sd-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
syscon@59820000 {
|
||||
compatible = "socionext,uniphier-pro5-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
peri_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pro5-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
peri_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pro5-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
syscon@5f800000 {
|
||||
compatible = "socionext,uniphier-pro5-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
@ -379,9 +383,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
|
||||
syscon@5f900000 {
|
||||
compatible = "socionext,uniphier-pro5-soc-glue-debug",
|
||||
"simple-mfd";
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f900000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x5f900000 0x2000>;
|
||||
@ -415,7 +420,7 @@
|
||||
xdmac: dma-controller@5fc10000 {
|
||||
compatible = "socionext,uniphier-xdmac";
|
||||
reg = <0x5fc10000 0x5300>;
|
||||
interrupts = <0 188 4>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
@ -430,14 +435,16 @@
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x304>;
|
||||
interrupts = <GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
@ -449,17 +456,17 @@
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
syscon@61840000 {
|
||||
compatible = "socionext,uniphier-pro5-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
sys_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pro5-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
sys_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pro5-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -470,7 +477,7 @@
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host";
|
||||
interrupts = <0 134 4>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
@ -480,14 +487,15 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
usb-controller@65b00000 {
|
||||
compatible = "socionext,uniphier-pro5-dwc3-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65b00000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb0_rst: reset@0 {
|
||||
usb0_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pro5-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
@ -506,7 +514,7 @@
|
||||
resets = <&sys_rst 12>, <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_hsphy0: hs-phy@280 {
|
||||
usb0_hsphy0: phy@280 {
|
||||
compatible = "socionext,uniphier-pro5-usb3-hsphy";
|
||||
reg = <0x280 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -517,7 +525,7 @@
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_ssphy0: ss-phy@380 {
|
||||
usb0_ssphy0: phy@380 {
|
||||
compatible = "socionext,uniphier-pro5-usb3-ssphy";
|
||||
reg = <0x380 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -534,7 +542,7 @@
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host";
|
||||
interrupts = <0 137 4>;
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
@ -544,14 +552,15 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
usb-controller@65d00000 {
|
||||
compatible = "socionext,uniphier-pro5-dwc3-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65d00000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x400>;
|
||||
|
||||
usb1_rst: reset@0 {
|
||||
usb1_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pro5-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
@ -579,7 +588,7 @@
|
||||
resets = <&sys_rst 12>, <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_hsphy0: hs-phy@280 {
|
||||
usb1_hsphy0: phy@280 {
|
||||
compatible = "socionext,uniphier-pro5-usb3-hsphy";
|
||||
reg = <0x280 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -590,7 +599,7 @@
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
};
|
||||
|
||||
usb1_hsphy1: hs-phy@290 {
|
||||
usb1_hsphy1: phy@290 {
|
||||
compatible = "socionext,uniphier-pro5-usb3-hsphy";
|
||||
reg = <0x290 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -601,7 +610,7 @@
|
||||
vbus-supply = <&usb1_vbus1>;
|
||||
};
|
||||
|
||||
usb1_ssphy0: ss-phy@380 {
|
||||
usb1_ssphy0: phy@380 {
|
||||
compatible = "socionext,uniphier-pro5-usb3-ssphy";
|
||||
reg = <0x380 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -614,8 +623,7 @@
|
||||
};
|
||||
|
||||
pcie_ep: pcie-ep@66000000 {
|
||||
compatible = "socionext,uniphier-pro5-pcie-ep",
|
||||
"snps,dw-pcie-ep";
|
||||
compatible = "socionext,uniphier-pro5-pcie-ep";
|
||||
status = "disabled";
|
||||
reg-names = "dbi", "dbi2", "link", "addr_space";
|
||||
reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
|
||||
@ -648,7 +656,9 @@
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
@ -661,7 +671,7 @@
|
||||
compatible = "socionext,uniphier-sd-v3.1";
|
||||
status = "disabled";
|
||||
reg = <0x68400000 0x800>;
|
||||
interrupts = <0 78 4>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&sd_clk 1>;
|
||||
@ -677,7 +687,7 @@
|
||||
compatible = "socionext,uniphier-sd-v3.1";
|
||||
status = "disabled";
|
||||
reg = <0x68800000 0x800>;
|
||||
interrupts = <0 76 4>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
@ -689,6 +699,7 @@
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
socionext,syscon-uhs-mode = <&sdctrl 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -99,3 +99,7 @@
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ahci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
#include <dt-bindings/gpio/uniphier-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
@ -161,7 +162,10 @@
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-size = <(1280 * 1024)>;
|
||||
cache-sets = <512>;
|
||||
@ -175,7 +179,7 @@
|
||||
reg = <0x54006000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 39 4>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
@ -188,7 +192,7 @@
|
||||
reg = <0x54006100 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 216 4>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 12>;
|
||||
@ -199,7 +203,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
@ -210,7 +214,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
@ -221,7 +225,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
@ -232,7 +236,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 177 4>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
@ -259,7 +263,7 @@
|
||||
audio@56000000 {
|
||||
compatible = "socionext,uniphier-pxs2-aio";
|
||||
reg = <0x56000000 0x80000>;
|
||||
interrupts = <0 144 4>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ain1>,
|
||||
<&pinctrl_ain2>,
|
||||
@ -317,7 +321,7 @@
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 4>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&peri_clk 4>;
|
||||
@ -331,7 +335,7 @@
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 4>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&peri_clk 5>;
|
||||
@ -345,7 +349,7 @@
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&peri_clk 6>;
|
||||
@ -359,7 +363,7 @@
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 4>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&peri_clk 7>;
|
||||
@ -373,7 +377,7 @@
|
||||
reg = <0x58784000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 45 4>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 8>;
|
||||
resets = <&peri_rst 8>;
|
||||
clock-frequency = <400000>;
|
||||
@ -385,7 +389,7 @@
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 9>;
|
||||
resets = <&peri_rst 9>;
|
||||
clock-frequency = <400000>;
|
||||
@ -397,7 +401,7 @@
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 10>;
|
||||
resets = <&peri_rst 10>;
|
||||
clock-frequency = <400000>;
|
||||
@ -418,33 +422,33 @@
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
sdctrl@59810000 {
|
||||
sdctrl: syscon@59810000 {
|
||||
compatible = "socionext,uniphier-pxs2-sdctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x400>;
|
||||
|
||||
sd_clk: clock {
|
||||
sd_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pxs2-sd-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sd_rst: reset {
|
||||
sd_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pxs2-sd-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
syscon@59820000 {
|
||||
compatible = "socionext,uniphier-pxs2-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
peri_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pxs2-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
peri_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pxs2-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -454,7 +458,7 @@
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a000000 0x800>;
|
||||
interrupts = <0 78 4>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&sd_clk 1>;
|
||||
@ -470,7 +474,7 @@
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x800>;
|
||||
interrupts = <0 76 4>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
@ -482,9 +486,10 @@
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
socionext,syscon-uhs-mode = <&sdctrl 0>;
|
||||
};
|
||||
|
||||
soc_glue: soc-glue@5f800000 {
|
||||
soc_glue: syscon@5f800000 {
|
||||
compatible = "socionext,uniphier-pxs2-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
@ -494,9 +499,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
|
||||
syscon@5f900000 {
|
||||
compatible = "socionext,uniphier-pxs2-soc-glue-debug",
|
||||
"simple-mfd";
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f900000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x5f900000 0x2000>;
|
||||
@ -515,7 +521,7 @@
|
||||
xdmac: dma-controller@5fc10000 {
|
||||
compatible = "socionext,uniphier-xdmac";
|
||||
reg = <0x5fc10000 0x5300>;
|
||||
interrupts = <0 188 4>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
@ -530,14 +536,16 @@
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0xf04>;
|
||||
interrupts = <GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
@ -549,24 +557,24 @@
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
syscon@61840000 {
|
||||
compatible = "socionext,uniphier-pxs2-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
sys_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pxs2-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
sys_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pxs2-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pvtctl: pvtctl {
|
||||
pvtctl: thermal-sensor {
|
||||
compatible = "socionext,uniphier-pxs2-thermal";
|
||||
interrupts = <0 3 4>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
socionext,tmod-calibration = <0x0f86 0x6844>;
|
||||
};
|
||||
@ -576,7 +584,7 @@
|
||||
compatible = "socionext,uniphier-pxs2-ave4";
|
||||
status = "disabled";
|
||||
reg = <0x65000000 0x8500>;
|
||||
interrupts = <0 66 4>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ether_rgmii>;
|
||||
clock-names = "ether";
|
||||
@ -593,12 +601,53 @@
|
||||
};
|
||||
};
|
||||
|
||||
ahci: sata@65600000 {
|
||||
compatible = "socionext,uniphier-pxs2-ahci",
|
||||
"generic-ahci";
|
||||
status = "disabled";
|
||||
reg = <0x65600000 0x10000>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sys_clk 28>;
|
||||
resets = <&sys_rst 28>, <&ahci_rst 0>;
|
||||
ports-implemented = <1>;
|
||||
phys = <&ahci_phy>;
|
||||
};
|
||||
|
||||
sata-controller@65700000 {
|
||||
compatible = "socionext,uniphier-pxs2-ahci-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65700000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65700000 0x100>;
|
||||
|
||||
ahci_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pxs2-ahci-reset";
|
||||
reg = <0x0 0x4>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 28>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 28>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
ahci_phy: phy@10 {
|
||||
compatible = "socionext,uniphier-pxs2-ahci-phy";
|
||||
reg = <0x10 0x10>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 28>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 28>, <&sys_rst 30>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 134 4>, <0 135 4>;
|
||||
interrupt-names = "dwc_usb3";
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
@ -609,14 +658,15 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
usb-controller@65b00000 {
|
||||
compatible = "socionext,uniphier-pxs2-dwc3-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65b00000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb0_rst: reset@0 {
|
||||
usb0_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
@ -644,7 +694,7 @@
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
usb0_hsphy0: hs-phy@200 {
|
||||
usb0_hsphy0: phy@200 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -655,7 +705,7 @@
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_hsphy1: hs-phy@210 {
|
||||
usb0_hsphy1: phy@210 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -666,7 +716,7 @@
|
||||
vbus-supply = <&usb0_vbus1>;
|
||||
};
|
||||
|
||||
usb0_ssphy0: ss-phy@300 {
|
||||
usb0_ssphy0: phy@300 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -677,7 +727,7 @@
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_ssphy1: ss-phy@310 {
|
||||
usb0_ssphy1: phy@310 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
||||
reg = <0x310 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -693,8 +743,8 @@
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 137 4>, <0 138 4>;
|
||||
interrupt-names = "dwc_usb3";
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
@ -704,14 +754,15 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
usb-controller@65d00000 {
|
||||
compatible = "socionext,uniphier-pxs2-dwc3-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65d00000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x400>;
|
||||
|
||||
usb1_rst: reset@0 {
|
||||
usb1_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
@ -739,7 +790,7 @@
|
||||
resets = <&sys_rst 15>;
|
||||
};
|
||||
|
||||
usb1_hsphy0: hs-phy@200 {
|
||||
usb1_hsphy0: phy@200 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -750,7 +801,7 @@
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
};
|
||||
|
||||
usb1_hsphy1: hs-phy@210 {
|
||||
usb1_hsphy1: phy@210 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -761,7 +812,7 @@
|
||||
vbus-supply = <&usb1_vbus1>;
|
||||
};
|
||||
|
||||
usb1_ssphy0: ss-phy@300 {
|
||||
usb1_ssphy0: phy@300 {
|
||||
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -778,7 +829,9 @@
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
|
||||
@ -40,11 +40,11 @@
|
||||
};
|
||||
|
||||
ðsc {
|
||||
interrupts = <4 8>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
&serialsc {
|
||||
interrupts = <4 8>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
@ -68,7 +68,7 @@
|
||||
};
|
||||
|
||||
&gpio {
|
||||
xirq4 {
|
||||
xirq4-hog {
|
||||
gpio-hog;
|
||||
gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
|
||||
input;
|
||||
@ -131,6 +131,18 @@
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ahci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ahci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl_ether_rgmii {
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/gpio/uniphier-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
@ -42,6 +43,7 @@
|
||||
reg = <0 0x000>;
|
||||
clocks = <&sys_clk 33>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
@ -52,6 +54,7 @@
|
||||
reg = <0 0x001>;
|
||||
clocks = <&sys_clk 33>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
@ -62,6 +65,7 @@
|
||||
reg = <0 0x002>;
|
||||
clocks = <&sys_clk 33>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
@ -72,9 +76,14 @@
|
||||
reg = <0 0x003>;
|
||||
clocks = <&sys_clk 33>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
cluster0_opp: opp-table {
|
||||
@ -135,10 +144,10 @@
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 4>,
|
||||
<1 14 4>,
|
||||
<1 11 4>,
|
||||
<1 10 4>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
@ -195,7 +204,7 @@
|
||||
reg = <0x54006000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 39 4>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
@ -208,7 +217,7 @@
|
||||
reg = <0x54006100 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 216 4>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&peri_clk 12>;
|
||||
@ -219,7 +228,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
@ -230,7 +239,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
@ -241,7 +250,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
@ -252,7 +261,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 177 4>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
@ -284,7 +293,7 @@
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 4>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&peri_clk 4>;
|
||||
@ -298,7 +307,7 @@
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 4>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&peri_clk 5>;
|
||||
@ -312,7 +321,7 @@
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&peri_clk 6>;
|
||||
@ -326,7 +335,7 @@
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 4>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&peri_clk 7>;
|
||||
@ -340,7 +349,7 @@
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&peri_clk 10>;
|
||||
resets = <&peri_rst 10>;
|
||||
clock-frequency = <400000>;
|
||||
@ -361,33 +370,33 @@
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
sdctrl@59810000 {
|
||||
sdctrl: syscon@59810000 {
|
||||
compatible = "socionext,uniphier-pxs3-sdctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x400>;
|
||||
|
||||
sd_clk: clock {
|
||||
sd_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pxs3-sd-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sd_rst: reset {
|
||||
sd_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pxs3-sd-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
syscon@59820000 {
|
||||
compatible = "socionext,uniphier-pxs3-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
peri_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pxs3-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
peri_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pxs3-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -396,7 +405,7 @@
|
||||
emmc: mmc@5a000000 {
|
||||
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
|
||||
reg = <0x5a000000 0x400>;
|
||||
interrupts = <0 78 4>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&sys_clk 4>;
|
||||
@ -416,7 +425,7 @@
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x800>;
|
||||
interrupts = <0 76 4>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
@ -428,9 +437,10 @@
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
socionext,syscon-uhs-mode = <&sdctrl 0>;
|
||||
};
|
||||
|
||||
soc_glue: soc-glue@5f800000 {
|
||||
soc_glue: syscon@5f800000 {
|
||||
compatible = "socionext,uniphier-pxs3-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
@ -440,9 +450,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
|
||||
syscon@5f900000 {
|
||||
compatible = "socionext,uniphier-pxs3-soc-glue-debug",
|
||||
"simple-mfd";
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f900000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x5f900000 0x2000>;
|
||||
@ -505,7 +516,7 @@
|
||||
xdmac: dma-controller@5fc10000 {
|
||||
compatible = "socionext,uniphier-xdmac";
|
||||
reg = <0x5fc10000 0x5300>;
|
||||
interrupts = <0 188 4>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
@ -523,20 +534,20 @@
|
||||
<0x5fe80000 0x80000>; /* GICR */
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <1 9 4>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
syscon@61840000 {
|
||||
compatible = "socionext,uniphier-pxs3-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
sys_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-pxs3-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
sys_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-pxs3-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -545,9 +556,9 @@
|
||||
compatible = "socionext,uniphier-wdt";
|
||||
};
|
||||
|
||||
pvtctl: pvtctl {
|
||||
pvtctl: thermal-sensor {
|
||||
compatible = "socionext,uniphier-pxs3-thermal";
|
||||
interrupts = <0 3 4>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
socionext,tmod-calibration = <0x0f22 0x68ee>;
|
||||
};
|
||||
@ -557,7 +568,7 @@
|
||||
compatible = "socionext,uniphier-pxs3-ave4";
|
||||
status = "disabled";
|
||||
reg = <0x65000000 0x8500>;
|
||||
interrupts = <0 66 4>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ether_rgmii>;
|
||||
clock-names = "ether";
|
||||
@ -578,7 +589,7 @@
|
||||
compatible = "socionext,uniphier-pxs3-ave4";
|
||||
status = "disabled";
|
||||
reg = <0x65200000 0x8500>;
|
||||
interrupts = <0 67 4>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ether1_rgmii>;
|
||||
clock-names = "ether";
|
||||
@ -595,12 +606,94 @@
|
||||
};
|
||||
};
|
||||
|
||||
ahci0: sata@65600000 {
|
||||
compatible = "socionext,uniphier-pxs3-ahci",
|
||||
"generic-ahci";
|
||||
status = "disabled";
|
||||
reg = <0x65600000 0x10000>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sys_clk 28>;
|
||||
resets = <&sys_rst 28>, <&ahci0_rst 0>;
|
||||
ports-implemented = <1>;
|
||||
phys = <&ahci0_phy>;
|
||||
};
|
||||
|
||||
sata-controller@65700000 {
|
||||
compatible = "socionext,uniphier-pxs3-ahci-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65700000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65700000 0x100>;
|
||||
|
||||
ahci0_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pxs3-ahci-reset";
|
||||
reg = <0x0 0x4>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 28>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 28>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
ahci0_phy: phy@10 {
|
||||
compatible = "socionext,uniphier-pxs3-ahci-phy";
|
||||
reg = <0x10 0x10>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 28>, <&sys_clk 30>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 28>, <&sys_rst 30>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ahci1: sata@65800000 {
|
||||
compatible = "socionext,uniphier-pxs3-ahci",
|
||||
"generic-ahci";
|
||||
status = "disabled";
|
||||
reg = <0x65800000 0x10000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sys_clk 29>;
|
||||
resets = <&sys_rst 29>, <&ahci1_rst 0>;
|
||||
ports-implemented = <1>;
|
||||
phys = <&ahci1_phy>;
|
||||
};
|
||||
|
||||
sata-controller@65900000 {
|
||||
compatible = "socionext,uniphier-pxs3-ahci-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65900000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65900000 0x100>;
|
||||
|
||||
ahci1_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pxs3-ahci-reset";
|
||||
reg = <0x0 0x4>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 29>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 29>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
ahci1_phy: phy@10 {
|
||||
compatible = "socionext,uniphier-pxs3-ahci-phy";
|
||||
reg = <0x10 0x10>;
|
||||
clock-names = "link", "phy";
|
||||
clocks = <&sys_clk 29>, <&sys_clk 30>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 29>, <&sys_rst 30>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 134 4>, <0 135 4>;
|
||||
interrupt-names = "dwc_usb3";
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
@ -611,14 +704,15 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65b00000 {
|
||||
usb-controller@65b00000 {
|
||||
compatible = "socionext,uniphier-pxs3-dwc3-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65b00000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb0_rst: reset@0 {
|
||||
usb0_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
@ -646,7 +740,7 @@
|
||||
resets = <&sys_rst 12>;
|
||||
};
|
||||
|
||||
usb0_hsphy0: hs-phy@200 {
|
||||
usb0_hsphy0: phy@200 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -660,7 +754,7 @@
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb0_hsphy1: hs-phy@210 {
|
||||
usb0_hsphy1: phy@210 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -674,7 +768,7 @@
|
||||
<&usb_hs_i0>;
|
||||
};
|
||||
|
||||
usb0_ssphy0: ss-phy@300 {
|
||||
usb0_ssphy0: phy@300 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -685,7 +779,7 @@
|
||||
vbus-supply = <&usb0_vbus0>;
|
||||
};
|
||||
|
||||
usb0_ssphy1: ss-phy@310 {
|
||||
usb0_ssphy1: phy@310 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x310 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -701,8 +795,8 @@
|
||||
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0xcd00>;
|
||||
interrupt-names = "host", "peripheral";
|
||||
interrupts = <0 137 4>, <0 138 4>;
|
||||
interrupt-names = "dwc_usb3";
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
||||
clock-names = "ref", "bus_early", "suspend";
|
||||
@ -713,14 +807,15 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb-glue@65d00000 {
|
||||
usb-controller@65d00000 {
|
||||
compatible = "socionext,uniphier-pxs3-dwc3-glue",
|
||||
"simple-mfd";
|
||||
reg = <0x65d00000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65d00000 0x400>;
|
||||
|
||||
usb1_rst: reset@0 {
|
||||
usb1_rst: reset-controller@0 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
@ -748,7 +843,7 @@
|
||||
resets = <&sys_rst 13>;
|
||||
};
|
||||
|
||||
usb1_hsphy0: hs-phy@200 {
|
||||
usb1_hsphy0: phy@200 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -763,7 +858,7 @@
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb1_hsphy1: hs-phy@210 {
|
||||
usb1_hsphy1: phy@210 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -778,7 +873,7 @@
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb1_ssphy0: ss-phy@300 {
|
||||
usb1_ssphy0: phy@300 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
@ -792,7 +887,7 @@
|
||||
};
|
||||
|
||||
pcie: pcie@66000000 {
|
||||
compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
|
||||
compatible = "socionext,uniphier-pcie";
|
||||
status = "disabled";
|
||||
reg-names = "dbi", "link", "config";
|
||||
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
|
||||
@ -812,7 +907,8 @@
|
||||
<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-names = "dma", "msi";
|
||||
interrupts = <0 224 4>, <0 225 4>;
|
||||
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
|
||||
<0 0 0 2 &pcie_intc 1>, /* INTB */
|
||||
@ -825,7 +921,7 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 226 4>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -845,7 +941,9 @@
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
|
||||
@ -36,11 +36,11 @@
|
||||
};
|
||||
|
||||
ðsc {
|
||||
interrupts = <0 8>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
&serialsc {
|
||||
interrupts = <0 8>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
@ -56,7 +56,7 @@
|
||||
};
|
||||
|
||||
&gpio {
|
||||
xirq0 {
|
||||
xirq0-hog {
|
||||
gpio-hog;
|
||||
gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
|
||||
input;
|
||||
@ -85,4 +85,8 @@
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
#include <dt-bindings/gpio/uniphier-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-sld8";
|
||||
@ -55,7 +56,8 @@
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-size = <(256 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
@ -69,7 +71,7 @@
|
||||
reg = <0x54006000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 39 4>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
@ -80,7 +82,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
@ -91,7 +93,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
@ -102,7 +104,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
@ -113,7 +115,7 @@
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 29 4>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
@ -144,7 +146,7 @@
|
||||
reg = <0x58400000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 1>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&peri_clk 4>;
|
||||
@ -158,7 +160,7 @@
|
||||
reg = <0x58480000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 1>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&peri_clk 5>;
|
||||
@ -172,7 +174,7 @@
|
||||
reg = <0x58500000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 1>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&peri_clk 6>;
|
||||
@ -186,7 +188,7 @@
|
||||
reg = <0x58580000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 1>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&peri_clk 7>;
|
||||
@ -209,33 +211,33 @@
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
mioctrl@59810000 {
|
||||
mioctrl: syscon@59810000 {
|
||||
compatible = "socionext,uniphier-sld8-mioctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x800>;
|
||||
|
||||
mio_clk: clock {
|
||||
mio_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-sld8-mio-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mio_rst: reset {
|
||||
mio_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-sld8-mio-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
syscon@59820000 {
|
||||
compatible = "socionext,uniphier-sld8-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
peri_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-sld8-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
peri_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-sld8-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -244,8 +246,13 @@
|
||||
dmac: dma-controller@5a000000 {
|
||||
compatible = "socionext,uniphier-mio-dmac";
|
||||
reg = <0x5a000000 0x1000>;
|
||||
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
|
||||
<0 71 4>, <0 72 4>, <0 73 4>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mio_clk 7>;
|
||||
resets = <&mio_rst 7>;
|
||||
#dma-cells = <1>;
|
||||
@ -255,7 +262,7 @@
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x200>;
|
||||
interrupts = <0 76 4>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default", "uhs";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_uhs>;
|
||||
@ -269,13 +276,14 @@
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
socionext,syscon-uhs-mode = <&mioctrl 0>;
|
||||
};
|
||||
|
||||
emmc: mmc@5a500000 {
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a500000 0x200>;
|
||||
interrupts = <0 78 4>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&mio_clk 1>;
|
||||
@ -293,7 +301,7 @@
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
|
||||
@ -307,7 +315,7 @@
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
|
||||
@ -321,7 +329,7 @@
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a820100 0x100>;
|
||||
interrupts = <0 82 4>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
|
||||
@ -331,7 +339,7 @@
|
||||
has-transaction-translator;
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
syscon@5f800000 {
|
||||
compatible = "socionext,uniphier-sld8-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
@ -341,9 +349,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
soc-glue@5f900000 {
|
||||
syscon@5f900000 {
|
||||
compatible = "socionext,uniphier-sld8-soc-glue-debug",
|
||||
"simple-mfd";
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f900000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x5f900000 0x2000>;
|
||||
@ -362,14 +371,16 @@
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x104>;
|
||||
interrupts = <GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x104>;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
@ -388,17 +399,17 @@
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
syscon@61840000 {
|
||||
compatible = "socionext,uniphier-sld8-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
sys_clk: clock-controller {
|
||||
compatible = "socionext,uniphier-sld8-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
sys_rst: reset-controller {
|
||||
compatible = "socionext,uniphier-sld8-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -409,7 +420,9 @@
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user