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serial: ns16550: Enable clocks during probe

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If the UART bus or baud clock has a gate, it must be enabled before the
UART can be used.

Series-to: Tom Rini <trini@konsulko.com>
Series-cc: Stefan Roese <sr@denx.de>
Series-cc: Simon Glass <sjg@chromium.org>
Series-cc: u-boot@lists.denx.de

Series-prefix: RESEND
Series-version: 3

Series-changes: 2
 - Only enable the first clock, as using the clk_get_bulk() API pushes
   a board (phycore-rk3288) over its SPL size limit.

Series-changes: 3
 - Switch back to the original patch, now that the phycore-rk3288 build
   is fixed by enabling LTO.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland 2022-10-30 14:56:10 -05:00
parent cbba1b7766
commit 0617377a25
1 changed files with 5 additions and 0 deletions
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5
drivers/serial/ns16550.c
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@ -514,6 +514,7 @@ int ns16550_serial_probe(struct udevice *dev)
struct ns16550_plat *plat = dev_get_plat(dev);
struct ns16550 *const com_port = dev_get_priv(dev);
struct reset_ctl_bulk reset_bulk;
struct clk_bulk clk_bulk;
fdt_addr_t addr;
fdt_addr_t size;
int ret;
@ -533,6 +534,10 @@ int ns16550_serial_probe(struct udevice *dev)
if (!ret)
reset_deassert_bulk(&reset_bulk);
ret = clk_get_bulk(dev, &clk_bulk);
if (!ret)
clk_enable_bulk(&clk_bulk);
com_port->plat = dev_get_plat(dev);
ns16550_init(com_port, -1);