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Xilinx changes for v2022.04-rc1

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gpio:
 - Add modepin driver
 
 net:
 - Save random mac addresses to eth variable
 
 zynqmp gem:
 - Add support for mdio bus DT description
 - Add support for reset and SGMII phy configuration
 - Reduce timeout for MDIO accesses
 
 zynqmp clk:
 - Fix clock handling for gem and usb
 
 phy:
 - Add zynqmp phy/serdes driver
 
 serial:
 - Add one missing compatible string
 
 microblaze:
 - Symbol alignement
 - SPL fixups
 - Code cleanups
 
 zynqmp:
 - Various dt changes, DP pre-reloc, gem resets, gem clocks
 - Switch SOM to shared psu configuration
 - Move dcache handling to firmware driver
 - Workaround gmii2rgmii DT description issue
 - Enable broadcasts again
 - Change firmware enablement logic
 - Small adjustement in firmware driver
 
 versal:
 - Support new mmc@ DT nodes
 - Fix run time variable handling
 - Add missing I2C_PMC ID for power domain
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Merge tag 'xilinx-for-v2022.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc1

gpio:
- Add modepin driver

net:
- Save random mac addresses to eth variable

zynqmp gem:
- Add support for mdio bus DT description
- Add support for reset and SGMII phy configuration
- Reduce timeout for MDIO accesses

zynqmp clk:
- Fix clock handling for gem and usb

phy:
- Add zynqmp phy/serdes driver

serial:
- Add one missing compatible string

microblaze:
- Symbol alignement
- SPL fixups
- Code cleanups

zynqmp:
- Various dt changes, DP pre-reloc, gem resets, gem clocks
- Switch SOM to shared psu configuration
- Move dcache handling to firmware driver
- Workaround gmii2rgmii DT description issue
- Enable broadcasts again
- Change firmware enablement logic
- Small adjustement in firmware driver

versal:
- Support new mmc@ DT nodes
- Fix run time variable handling
- Add missing I2C_PMC ID for power domain
This commit is contained in:
Tom Rini 2022-01-19 11:43:44 -05:00
commit 068415eade
33 changed files with 1225 additions and 233 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -618,6 +618,7 @@ F: drivers/clk/clk_zynqmp.c
F: driver/firmware/firmware-zynqmp.c
F: drivers/fpga/zynqpl.c
F: drivers/gpio/zynq_gpio.c
F: drivers/gpio/zynqmp_gpio_modepin.c
F: drivers/i2c/i2c-cdns.c
F: drivers/i2c/muxes/pca954x.c
F: drivers/i2c/zynq_i2c.c
@ -626,6 +627,7 @@ F: drivers/mmc/zynq_sdhci.c
F: drivers/mtd/nand/raw/zynq_nand.c
F: drivers/net/phy/xilinx_phy.c
F: drivers/net/zynq_gem.c
F: drivers/phy/phy-zynqmp.c
F: drivers/serial/serial_zynq.c
F: drivers/reset/reset-zynqmp.c
F: drivers/rtc/zynqmp_rtc.c

5
arch/arm/Kconfig
View File

@ -1207,7 +1207,7 @@ config ARCH_ZYNQMP
select DM_SERIAL
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
select FIRMWARE
imply FIRMWARE
select GICV2
select GPIO_EXTRA_HEADER
select OF_CONTROL
@ -1217,7 +1217,7 @@ config ARCH_ZYNQMP
select SPL_DM_SPI if SPI && SPL_DM
select SPL_DM_SPI_FLASH if SPL_DM_SPI
select SPL_DM_MAILBOX if SPL
select SPL_FIRMWARE if SPL
imply SPL_FIRMWARE if SPL
select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL
select ZYNQMP_IPI
@ -1228,6 +1228,7 @@ config ARCH_ZYNQMP
imply FAT_WRITE
imply MP
imply DM_USB_GADGET
imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
config ARCH_TEGRA
bool "NVIDIA Tegra"

4
arch/arm/dts/zynqmp-clk-ccf.dtsi
View File

@ -169,28 +169,24 @@
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem1 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem2 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem3 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gpio {

69
arch/arm/dts/zynqmp.dtsi
View File

@ -265,7 +265,7 @@
};
/* GDMA */
fpd_dma_chan1: dma@fd500000 {
fpd_dma_chan1: dma-controller@fd500000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd500000 0x0 0x1000>;
@ -276,9 +276,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14e8>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
};
fpd_dma_chan2: dma@fd510000 {
fpd_dma_chan2: dma-controller@fd510000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd510000 0x0 0x1000>;
@ -289,9 +290,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14e9>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
};
fpd_dma_chan3: dma@fd520000 {
fpd_dma_chan3: dma-controller@fd520000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd520000 0x0 0x1000>;
@ -302,9 +304,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ea>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
};
fpd_dma_chan4: dma@fd530000 {
fpd_dma_chan4: dma-controller@fd530000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd530000 0x0 0x1000>;
@ -315,9 +318,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14eb>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
};
fpd_dma_chan5: dma@fd540000 {
fpd_dma_chan5: dma-controller@fd540000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd540000 0x0 0x1000>;
@ -328,9 +332,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ec>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
};
fpd_dma_chan6: dma@fd550000 {
fpd_dma_chan6: dma-controller@fd550000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd550000 0x0 0x1000>;
@ -341,9 +346,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ed>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
};
fpd_dma_chan7: dma@fd560000 {
fpd_dma_chan7: dma-controller@fd560000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd560000 0x0 0x1000>;
@ -354,9 +360,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ee>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
};
fpd_dma_chan8: dma@fd570000 {
fpd_dma_chan8: dma-controller@fd570000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd570000 0x0 0x1000>;
@ -367,6 +374,7 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ef>;
power-domains = <&zynqmp_firmware PD_GDMA>;
#dma-cells = <1>;
};
gic: interrupt-controller@f9010000 {
@ -396,7 +404,7 @@
* These dma channels, Users should ensure that these dma
* Channels are allowed for non secure access.
*/
lpd_dma_chan1: dma@ffa80000 {
lpd_dma_chan1: dma-controller@ffa80000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa80000 0x0 0x1000>;
@ -407,9 +415,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x868>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
};
lpd_dma_chan2: dma@ffa90000 {
lpd_dma_chan2: dma-controller@ffa90000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa90000 0x0 0x1000>;
@ -420,9 +429,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x869>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
};
lpd_dma_chan3: dma@ffaa0000 {
lpd_dma_chan3: dma-controller@ffaa0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaa0000 0x0 0x1000>;
@ -433,9 +443,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86a>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
};
lpd_dma_chan4: dma@ffab0000 {
lpd_dma_chan4: dma-controller@ffab0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffab0000 0x0 0x1000>;
@ -446,9 +457,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86b>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
};
lpd_dma_chan5: dma@ffac0000 {
lpd_dma_chan5: dma-controller@ffac0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffac0000 0x0 0x1000>;
@ -459,9 +471,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86c>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
};
lpd_dma_chan6: dma@ffad0000 {
lpd_dma_chan6: dma-controller@ffad0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffad0000 0x0 0x1000>;
@ -472,9 +485,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86d>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
};
lpd_dma_chan7: dma@ffae0000 {
lpd_dma_chan7: dma-controller@ffae0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffae0000 0x0 0x1000>;
@ -485,9 +499,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86e>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
};
lpd_dma_chan8: dma@ffaf0000 {
lpd_dma_chan8: dma-controller@ffaf0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaf0000 0x0 0x1000>;
@ -498,6 +513,7 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86f>;
power-domains = <&zynqmp_firmware PD_ADMA>;
#dma-cells = <1>;
};
mc: memory-controller@fd070000 {
@ -527,12 +543,13 @@
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
};
gem1: ethernet@ff0c0000 {
@ -541,12 +558,13 @@
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
};
gem2: ethernet@ff0d0000 {
@ -555,12 +573,13 @@
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
};
gem3: ethernet@ff0e0000 {
@ -569,12 +588,13 @@
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
};
gpio: gpio@ff0a0000 {
@ -820,7 +840,7 @@
uart0: serial@ff000000 {
u-boot,dm-pre-reloc;
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
@ -831,7 +851,7 @@
uart1: serial@ff010000 {
u-boot,dm-pre-reloc;
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
@ -854,7 +874,7 @@
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
dwc3_0: dwc3@fe200000 {
dwc3_0: usb@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
@ -886,7 +906,7 @@
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
dwc3_1: dwc3@fe300000 {
dwc3_1: usb@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
@ -961,6 +981,7 @@
};
zynqmp_dpsub: display@fd4a0000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000>,

2
arch/microblaze/Kconfig
View File

@ -15,6 +15,8 @@ config TARGET_MICROBLAZE_GENERIC
select DM_SERIAL
select OF_CONTROL
select SUPPORT_SPL
select SPL_LIBCOMMON_SUPPORT if SPL
select SPL_LIBGENERIC_SUPPORT if SPL
select SYSRESET
select DM_SPI
select DM_SPI_FLASH

2
arch/microblaze/cpu/exception.c
View File

@ -55,7 +55,7 @@ void _hw_exception_handler (void)
hang();
}
#ifdef CONFIG_SYS_USR_EXCEP
#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
void _exception_handler (void)
{
puts("User vector_exception\n");

12
arch/microblaze/cpu/spl.c
View File

@ -12,12 +12,15 @@
#include <spl.h>
#include <asm/io.h>
#include <asm/u-boot.h>
#include <linux/stringify.h>
bool boot_linux;
u32 spl_boot_device(void)
void board_boot_order(u32 *spl_boot_list)
{
return BOOT_DEVICE_NOR;
spl_boot_list[0] = BOOT_DEVICE_NOR;
spl_boot_list[1] = BOOT_DEVICE_RAM;
spl_boot_list[2] = BOOT_DEVICE_SPI;
}
/* Board initialization after bss clearance */
@ -52,8 +55,9 @@ int spl_start_uboot(void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
__asm__ __volatile__ ("mts rmsr, r0;" \
"bra r0");
__asm__ __volatile__ (
"mts rmsr, r0;" \
"brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR));
return 0;
}

76
arch/microblaze/cpu/start.S
View File

@ -15,7 +15,7 @@
_start:
mts rmsr, r0 /* disable cache */
addi r8, r0, __end
addi r8, r0, _end
mts rslr, r8
#if defined(CONFIG_SPL_BUILD)
@ -105,15 +105,17 @@ clear_bss:
* r10: Stores little/big endian offset for vectors
* r2: Stores imm opcode
* r3: Stores brai opcode
* r4: Stores the vector base address
*/
__setup_exceptions:
addik r1, r1, -28
addik r1, r1, -32
swi r2, r1, 4
swi r3, r1, 8
swi r6, r1, 12
swi r7, r1, 16
swi r8, r1, 20
swi r10, r1, 24
swi r4, r1, 12
swi r6, r1, 16
swi r7, r1, 20
swi r8, r1, 24
swi r10, r1, 28
/* Find-out if u-boot is running on BIG/LITTLE endian platform
* There are some steps which is necessary to keep in mind:
@ -125,33 +127,32 @@ __setup_exceptions:
* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
*/
addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
lwi r7, r0, 0x28
swi r6, r0, 0x28 /* used first unused MB vector */
lbui r10, r0, 0x28 /* used first unused MB vector */
swi r7, r0, 0x28
sw r6, r1, r0
lbu r10, r1, r0
/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
#ifdef CONFIG_SYS_RESET_ADDRESS
/* reset address */
swi r2, r0, 0x0 /* reset address - imm opcode */
swi r3, r0, 0x4 /* reset address - brai opcode */
/* Store the vector base address in r4 */
addi r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
addik r6, r0, CONFIG_SYS_RESET_ADDRESS
/* reset address */
swi r2, r4, 0x0 /* reset address - imm opcode */
swi r3, r4, 0x4 /* reset address - brai opcode */
addik r6, r0, CONFIG_SYS_TEXT_BASE
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x2
sh r7, r0, r8
sh r7, r4, r8
rsubi r8, r10, 0x6
sh r6, r0, r8
#endif
sh r6, r4, r8
#ifdef CONFIG_SYS_USR_EXCEP
#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
/* user_vector_exception */
swi r2, r0, 0x8 /* user vector exception - imm opcode */
swi r3, r0, 0xC /* user vector exception - brai opcode */
swi r2, r4, 0x8 /* user vector exception - imm opcode */
swi r3, r4, 0xC /* user vector exception - brai opcode */
addik r6, r5, _exception_handler
sw r6, r1, r0
@ -177,42 +178,43 @@ __setup_exceptions:
*/
lhu r7, r1, r10
rsubi r8, r10, 0xa
sh r7, r0, r8
sh r7, r4, r8
rsubi r8, r10, 0xe
sh r6, r0, r8
sh r6, r4, r8
#endif
/* interrupt_handler */
swi r2, r0, 0x10 /* interrupt - imm opcode */
swi r3, r0, 0x14 /* interrupt - brai opcode */
swi r2, r4, 0x10 /* interrupt - imm opcode */
swi r3, r4, 0x14 /* interrupt - brai opcode */
addik r6, r5, _interrupt_handler
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x12
sh r7, r0, r8
sh r7, r4, r8
rsubi r8, r10, 0x16
sh r6, r0, r8
sh r6, r4, r8
/* hardware exception */
swi r2, r0, 0x20 /* hardware exception - imm opcode */
swi r3, r0, 0x24 /* hardware exception - brai opcode */
swi r2, r4, 0x20 /* hardware exception - imm opcode */
swi r3, r4, 0x24 /* hardware exception - brai opcode */
addik r6, r5, _hw_exception_handler
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x22
sh r7, r0, r8
sh r7, r4, r8
rsubi r8, r10, 0x26
sh r6, r0, r8
sh r6, r4, r8
lwi r10, r1, 24
lwi r8, r1, 20
lwi r7, r1, 16
lwi r6, r1, 12
lwi r10, r1, 28
lwi r8, r1, 24
lwi r7, r1, 20
lwi r6, r1, 16
lwi r4, r1, 12
lwi r3, r1, 8
lwi r2, r1, 4
addik r1, r1, 28
addik r1, r1, 32
rtsd r15, 8
or r0, r0, r0
@ -270,7 +272,7 @@ relocate_code:
add r23, r0, r7 /* Move reloc addr to r23 */
/* Relocate text and data - r12 temp value */
addi r21, r0, _start
addi r22, r0, __end - 4 /* Include BSS too */
addi r22, r0, _end - 4 /* Include BSS too */
rsub r6, r21, r22
or r5, r0, r0

4
arch/microblaze/cpu/u-boot-spl.lds
View File

@ -53,10 +53,10 @@ SECTIONS
. = ALIGN(4);
__bss_end = .;
}
__end = . ;
_end = . ;
}
#if defined(CONFIG_SPL_MAX_FOOTPRINT)
ASSERT(__end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \
ASSERT(_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \
"SPL image plus BSS too big");
#endif

2
arch/microblaze/cpu/u-boot.lds
View File

@ -56,5 +56,5 @@ SECTIONS
. = ALIGN(4);
__bss_end = .;
}
__end = . ;
_end = . ;
}

2
arch/microblaze/include/asm/processor.h
View File

@ -8,7 +8,7 @@
/* References to section boundaries */
extern char __end[];
extern char _end[];
extern char __text_start[];
/* Microblaze board initialization function */

1
board/xilinx/Kconfig
View File

@ -43,6 +43,7 @@ endif
config XILINX_OF_BOARD_DTB_ADDR
hex "Default DTB pickup address"
default 0x1000 if ARCH_VERSAL
default 0x8000 if MICROBLAZE
default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
depends on OF_BOARD || OF_SEPARATE
help

16
board/xilinx/microblaze-generic/Kconfig
View File

@ -38,4 +38,20 @@ config XILINX_MICROBLAZE0_HW_VER
string "Core version number"
default "7.10.d"
config XILINX_MICROBLAZE0_USR_EXCEP
bool "MicroBlaze user exception support"
default y
help
Enable this option in order to install the user exception handler
(_exception_handler routine from arch/microblaze/cpu/exception.c) in
the exception vector table. The user exception vector is located at
C_BASE_VECTORS + 0x8 address.
config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
hex "Location of MicroBlaze vectors"
default 0x0
help
Memory address location of the exception vector table. It is
configurable via the C_BASE_VECTORS hdl parameter.
endif

10
board/xilinx/versal/board.c
View File

@ -151,6 +151,8 @@ int board_late_init(void)
case EMMC_MODE:
puts("EMMC_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1050000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@f1050000", &dev)) {
puts("Boot from EMMC but without SD1 enabled!\n");
return -1;
@ -162,6 +164,8 @@ int board_late_init(void)
case SD_MODE:
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1040000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@f1040000", &dev)) {
puts("Boot from SD0 but without SD0 enabled!\n");
return -1;
@ -177,6 +181,8 @@ int board_late_init(void)
case SD_MODE1:
puts("SD_MODE1\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1050000", &dev) &&
uclass_get_device_by_name(UCLASS_MMC,
"sdhci@f1050000", &dev)) {
puts("Boot from SD1 but without SD1 enabled!\n");
return -1;
@ -263,13 +269,13 @@ enum env_location env_get_location(enum env_operation op, int prio)
return ENVL_FAT;
if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
return ENVL_EXT4;
return ENVL_UNKNOWN;
return ENVL_NOWHERE;
case OSPI_MODE:
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
return ENVL_SPI_FLASH;
return ENVL_UNKNOWN;
return ENVL_NOWHERE;
case JTAG_MODE:
default:
return ENVL_NOWHERE;

1
board/xilinx/zynqmp/cmds.c
View File

@ -211,7 +211,6 @@ static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc,
addr = hextoul(argv[2], NULL);
size = hextoul(argv[3], NULL);
flush_dcache_range((ulong)addr, (ulong)(addr + size));
zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr,
(size_t)size);

200
board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
View File

@ -9,33 +9,31 @@
static unsigned long psu_pll_init_data(void)
{
psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
mask_poll(0xFF5E0040, 0x00000002U);
psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4E2C62U);
psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00013C00U);
psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
mask_poll(0xFF5E0040, 0x00000001U);
psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000200U);
psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00015000U);
psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
mask_poll(0xFD1A0044, 0x00000001U);
psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x80000033U);
psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
@ -43,58 +41,43 @@ static unsigned long psu_pll_init_data(void)
psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
mask_poll(0xFD1A0044, 0x00000002U);
psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
mask_poll(0xFD1A0044, 0x00000004U);
psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
return 1;
}
static unsigned long psu_clock_init_data(void)
{
psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010800U);
psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010A00U);
psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010A00U);
psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010500U);
psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000402U);
psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000500U);
psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000202U);
psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000A02U);
psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000402U);
psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000202U);
psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010A00U);
psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010A00U);
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011402U);
psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U);
psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000300U);
psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
@ -133,8 +116,8 @@ static unsigned long psu_ddr_init_data(void)
psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102411U);
psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
@ -234,14 +217,14 @@ static unsigned long psu_ddr_init_data(void)
psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U);
psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07221008U);
psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07241008U);
psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U);
psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00311008U);
psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00331008U);
psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U);
psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
@ -407,90 +390,63 @@ static unsigned long psu_mio_init_data(void)
psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U);
psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U);
psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
psu_mask_write(0xFF180068, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180090, 0x000000FEU, 0x000000C0U);
psu_mask_write(0xFF180094, 0x000000FEU, 0x000000C0U);
psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xD4000000U);
psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U);
psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x84000000U);
psu_mask_write(0xFF180208, 0x000FFFFFU, 0x00000020U);
psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x00000000U);
psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x00080835U);
psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x03F7F7CAU);
psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x00FC000BU);
psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x0357FFFFU);
psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x0303FFF4U);
psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
return 1;
@ -506,24 +462,15 @@ static unsigned long psu_peripherals_pre_init_data(void)
static unsigned long psu_peripherals_init_data(void)
{
psu_mask_write(0xFD1A0100, 0x0001007EU, 0x00000000U);
psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
psu_mask_write(0xFF180320, 0x33843384U, 0x02841284U);
psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U);
psu_mask_write(0xFF010034, 0x000000FFU, 0x00000006U);
psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000007CU);
@ -536,13 +483,6 @@ static unsigned long psu_peripherals_init_data(void)
psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00040000U);
psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00040000U);
psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0004U);
mask_delay(1);
psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0000U);
mask_delay(5);
psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0004U);
return 1;
}

24
drivers/clk/clk_zynqmp.c
View File

@ -130,8 +130,8 @@ enum zynqmp_clk {
csu_spb, csu_pll, pcap,
iou_switch,
gem_tsu_ref, gem_tsu,
gem0_ref, gem1_ref, gem2_ref, gem3_ref,
gem0_tx, gem1_tx, gem2_tx, gem3_tx,
gem0_rx, gem1_rx, gem2_rx, gem3_rx,
qspi_ref,
sdio0_ref, sdio1_ref,
uart0_ref, uart1_ref,
@ -144,6 +144,8 @@ enum zynqmp_clk {
ams_ref,
pl0, pl1, pl2, pl3,
wdt,
gem0_ref = 104,
gem1_ref, gem2_ref, gem3_ref,
clk_max,
};
@ -161,14 +163,18 @@ static const char * const clk_names[clk_max] = {
"usb1_bus_ref", "usb3_dual_ref", "usb0",
"usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
"csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
"gem_tsu", "gem0_tx", "gem1_tx", "gem2_tx",
"gem3_tx", "gem0_rx", "gem1_rx", "gem2_rx",
"gem3_rx", "qspi_ref", "sdio0_ref", "sdio1_ref",
"uart0_ref", "uart1_ref", "spi0_ref",
"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
"can0_ref", "can1_ref", "can0", "can1",
"dll_ref", "adma_ref", "timestamp_ref",
"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt",
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref",
};
static const u32 pll_src[][4] = {
@ -258,12 +264,16 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return CRL_APB_USB3_DUAL_REF_CTRL;
case gem_tsu_ref:
return CRL_APB_GEM_TSU_REF_CTRL;
case gem0_tx:
case gem0_ref:
return CRL_APB_GEM0_REF_CTRL;
case gem1_tx:
case gem1_ref:
return CRL_APB_GEM1_REF_CTRL;
case gem2_tx:
case gem2_ref:
return CRL_APB_GEM2_REF_CTRL;
case gem3_tx:
case gem3_ref:
return CRL_APB_GEM3_REF_CTRL;
case usb0_bus_ref:
@ -665,6 +675,7 @@ static ulong zynqmp_clk_get_rate(struct clk *clk)
case gem_tsu_ref:
case pl0 ... pl3:
case gem0_ref ... gem3_ref:
case gem0_tx ... gem3_tx:
case qspi_ref ... can1_ref:
case usb0_bus_ref ... usb3_dual_ref:
two_divs = true;
@ -698,7 +709,9 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
switch (id) {
case gem0_ref ... gem3_ref:
case gem0_tx ... gem3_tx:
case qspi_ref ... can1_ref:
case usb0_bus_ref ... usb3_dual_ref:
return zynqmp_clk_set_peripheral_rate(priv, id,
rate, two_divs);
default:
@ -808,6 +821,7 @@ static int zynqmp_clk_enable(struct clk *clk)
clkact_shift = 25;
mask = 0x1;
break;
case gem0_tx ... gem3_tx:
case gem0_ref ... gem3_ref:
clkact_shift = 25;
mask = 0x3;

12
drivers/firmware/firmware-zynqmp.c
View File

@ -6,6 +6,7 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <log.h>
#include <zynqmp_firmware.h>
@ -19,6 +20,7 @@
#define PMUFW_PAYLOAD_ARG_CNT 8
#define XST_PM_NO_ACCESS 2002L
#define XST_PM_ALREADY_CONFIGURED 2009L
struct zynqmp_power {
struct mbox_chan tx_chan;
@ -97,7 +99,10 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
int err;
u32 ret_payload[PAYLOAD_ARG_CNT];
printf("Loading new PMUFW cfg obj (%ld bytes)\n", size);
if (IS_ENABLED(CONFIG_SPL_BUILD))
printf("Loading new PMUFW cfg obj (%ld bytes)\n", size);
flush_dcache_range((ulong)cfg_obj, (ulong)(cfg_obj + size));
err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0,
0, ret_payload);
@ -106,6 +111,11 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
return;
}
if (err == XST_PM_ALREADY_CONFIGURED) {
debug("PMUFW Node is already configured\n");
return;
}
if (err)
printf("Cannot load PMUFW configuration object (%d)\n", err);

9
drivers/gpio/Kconfig
View File

@ -528,4 +528,13 @@ config NOMADIK_GPIO
into a number of banks each with 32 GPIOs. The GPIOs for a device are
defined in the device tree with one node for each bank.
config ZYNQMP_GPIO_MODEPIN
bool "ZynqMP gpio modepin"
depends on DM_GPIO
help
This config enables the ZynqMP gpio modepin driver. ZynqMP modepin
driver will set and get the status of PS_MODE pins. These modepins
are accessed using xilinx firmware. In modepin register, [3:0] bits
set direction, [7:4] bits read IO, [11:8] bits set/clear IO.
endif

1
drivers/gpio/Makefile
View File

@ -69,3 +69,4 @@ obj-$(CONFIG_NX_GPIO) += nx_gpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o
obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o

153
drivers/gpio/zynqmp_gpio_modepin.c Normal file
View File

@ -0,0 +1,153 @@
// SPDX-License-Identifier: GPL-2.0
/*
* ZynqMP GPIO modepin driver
*
* Copyright (C) 2021 Xilinx, Inc.
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm.h>
#include <asm/arch/hardware.h>
#include <zynqmp_firmware.h>
#define OUTEN(pin) (BIT(0) << (pin))
#define INVAL(pin) (BIT(4) << (pin))
#define OUTVAL(pin) (BIT(8) << (pin))
#define ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK 0xF0F
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL (ZYNQMP_CRL_APB_BASEADDR + \
(0x250U))
static int get_gpio_modepin(u32 *ret_payload)
{
return xilinx_pm_request(PM_MMIO_READ, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
0, 0, 0, ret_payload);
}
static int set_gpio_modepin(int val)
{
return xilinx_pm_request(PM_MMIO_WRITE, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK,
val, 0, NULL);
}
static int modepin_gpio_direction_input(struct udevice *dev,
unsigned int offset)
{
return 0;
}
static int modepin_gpio_set_value(struct udevice *dev, unsigned int offset,
int value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 out_val = 0;
int ret;
ret = get_gpio_modepin(ret_payload);
if (value)
out_val = OUTVAL(offset) | ret_payload[1];
else
out_val = ~OUTVAL(offset) & ret_payload[1];
return set_gpio_modepin(out_val);
}
static int modepin_gpio_direction_output(struct udevice *dev,
unsigned int offset, int value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 out_en = 0;
int ret;
ret = get_gpio_modepin(ret_payload);
if (ret)
return ret;
if (value)
out_en = OUTEN(offset) | ret_payload[1];
else
out_en = ~OUTEN(offset) & ret_payload[1];
ret = set_gpio_modepin(out_en);
if (ret)
return ret;
return modepin_gpio_set_value(dev, offset, value);
}
static int modepin_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
struct ofnode_phandle_args *args)
{
desc->offset = args->args[0];
return 0;
}
static int modepin_gpio_get_value(struct udevice *dev, unsigned int offset)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
ret = get_gpio_modepin(ret_payload);
if (ret)
return ret;
return (INVAL(offset) & ret_payload[1]) ? 1 : 0;
}
static int modepin_gpio_get_function(struct udevice *dev, unsigned int offset)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
ret = get_gpio_modepin(ret_payload);
if (ret)
return ret;
return (OUTEN(offset) & ret_payload[1]) ? GPIOF_OUTPUT : GPIOF_INPUT;
}
static const struct dm_gpio_ops modepin_gpio_ops = {
.direction_input = modepin_gpio_direction_input,
.direction_output = modepin_gpio_direction_output,
.get_value = modepin_gpio_get_value,
.set_value = modepin_gpio_set_value,
.get_function = modepin_gpio_get_function,
.xlate = modepin_gpio_xlate,
};
static int modepin_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *label_ptr;
label_ptr = dev_read_prop(dev, "label", NULL);
if (label_ptr) {
uc_priv->bank_name = strdup(label_ptr);
if (!uc_priv->bank_name)
return -ENOMEM;
} else {
uc_priv->bank_name = dev->name;
}
uc_priv->gpio_count = 4;
return 0;
}
static const struct udevice_id modepin_gpio_ids[] = {
{ .compatible = "xlnx,zynqmp-gpio-modepin",},
{ }
};
U_BOOT_DRIVER(modepin_gpio) = {
.name = "modepin_gpio",
.id = UCLASS_GPIO,
.ops = &modepin_gpio_ops,
.of_match = modepin_gpio_ids,
.probe = modepin_gpio_probe,
};

60
drivers/net/zynq_gem.c
View File

@ -12,6 +12,7 @@
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <generic-phy.h>
#include <log.h>
#include <net.h>
#include <netdev.h>
@ -21,6 +22,7 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <phy.h>
#include <reset.h>
#include <miiphy.h>
#include <wait_bit.h>
#include <watchdog.h>
@ -60,7 +62,6 @@
#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_NO_BRDC BIT(5) /* No broadcast */
#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
@ -78,7 +79,6 @@
#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
ZYNQ_GEM_NWCFG_FDEN | \
ZYNQ_GEM_NWCFG_NO_BRDC | \
ZYNQ_GEM_NWCFG_FSREM | \
ZYNQ_GEM_NWCFG_MDCCLKDIV)
@ -110,6 +110,8 @@
#define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
#define MDIO_IDLE_TIMEOUT_MS 100
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
@ -215,6 +217,7 @@ struct zynq_gem_priv {
bool int_pcs;
bool dma_64bit;
u32 clk_en_info;
struct reset_ctl_bulk resets;
};
static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@ -225,7 +228,7 @@ static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
int err;
err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
true, 20000, false);
true, MDIO_IDLE_TIMEOUT_MS, false);
if (err)
return err;
@ -238,7 +241,7 @@ static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
writel(mgtcr, &regs->phymntnc);
err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
true, 20000, false);
true, MDIO_IDLE_TIMEOUT_MS, false);
if (err)
return err;
@ -333,7 +336,8 @@ static int zynq_phy_init(struct udevice *dev)
ADVERTISED_Asym_Pause;
priv->phydev->advertising = priv->phydev->supported;
priv->phydev->node = priv->phy_of_node;
if (!ofnode_valid(priv->phydev->node))
priv->phydev->node = priv->phy_of_node;
return phy_config(priv->phydev);
}
@ -686,11 +690,48 @@ static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
return phywrite(priv, addr, reg, value);
}
static int zynq_gem_reset_init(struct udevice *dev)
{
struct zynq_gem_priv *priv = dev_get_priv(dev);
int ret;
ret = reset_get_bulk(dev, &priv->resets);
if (ret == -ENOTSUPP || ret == -ENOENT)
return 0;
else if (ret)
return ret;
ret = reset_deassert_bulk(&priv->resets);
if (ret) {
reset_release_bulk(&priv->resets);
return ret;
}
return 0;
}
static int zynq_gem_probe(struct udevice *dev)
{
void *bd_space;
struct zynq_gem_priv *priv = dev_get_priv(dev);
int ret;
struct phy phy;
if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
ret = generic_phy_get_by_index(dev, 0, &phy);
if (!ret) {
ret = generic_phy_init(&phy);
if (ret)
return ret;
} else if (ret != -ENOENT) {
debug("could not get phy (err %d)\n", ret);
return ret;
}
}
ret = zynq_gem_reset_init(dev);
if (ret)
return ret;
/* Align rxbuffers to ARCH_DMA_MINALIGN */
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
@ -743,6 +784,12 @@ static int zynq_gem_probe(struct udevice *dev)
if (ret)
goto err3;
if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) {
ret = generic_phy_power_on(&phy);
if (ret)
return ret;
}
return ret;
err3:
@ -802,6 +849,9 @@ static int zynq_gem_of_to_plat(struct udevice *dev)
SPEED_1000);
parent = ofnode_get_parent(phandle_args.node);
if (ofnode_name_eq(parent, "mdio"))
parent = ofnode_get_parent(parent);
addr = ofnode_get_addr(parent);
if (addr != FDT_ADDR_T_NONE) {
debug("MDIO bus not found %s\n", dev->name);

7
drivers/phy/Kconfig
View File

@ -281,6 +281,13 @@ config PHY_IMX8MQ_USB
help
Support the USB3.0 PHY in NXP i.MX8MQ SoC
config PHY_XILINX_ZYNQMP
tristate "Xilinx ZynqMP PHY driver"
depends on PHY && ARCH_ZYNQMP
help
Enable this to support ZynqMP High Speed Gigabit Transceiver
that is part of ZynqMP SoC.
source "drivers/phy/rockchip/Kconfig"
source "drivers/phy/cadence/Kconfig"
source "drivers/phy/ti/Kconfig"

1
drivers/phy/Makefile
View File

@ -38,5 +38,6 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
obj-y += cadence/
obj-y += ti/

754
drivers/phy/phy-zynqmp.c Normal file
View File

@ -0,0 +1,754 @@
// SPDX-License-Identifier: GPL-2.0
/*
* phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
*
* Copyright (C) 2018-2021 Xilinx Inc.
*
* Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
* Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
* Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <generic-phy.h>
#include <log.h>
#include <power-domain.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <dm/device.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dt-bindings/phy/phy.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
/*
* Lane Registers
*/
/* TX De-emphasis parameters */
#define L0_TX_ANA_TM_18 0x0048
#define L0_TX_ANA_TM_118 0x01d8
#define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0)
/* DN Resistor calibration code parameters */
#define L0_TXPMA_ST_3 0x0b0c
#define L0_DN_CALIB_CODE 0x3f
/* PMA control parameters */
#define L0_TXPMD_TM_45 0x0cb4
#define L0_TXPMD_TM_48 0x0cc0
#define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0)
#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3)
#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5)
/* PCS control parameters */
#define L0_TM_DIG_6 0x106c
#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f
#define L0_TX_DIG_61 0x00f4
#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f
/* PLL Test Mode register parameters */
#define L0_TM_PLL_DIG_37 0x2094
#define L0_TM_COARSE_CODE_LIMIT 0x10
/* PLL SSC step size offsets */
#define L0_PLL_SS_STEPS_0_LSB 0x2368
#define L0_PLL_SS_STEPS_1_MSB 0x236c
#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370
#define L0_PLL_SS_STEP_SIZE_1 0x2374
#define L0_PLL_SS_STEP_SIZE_2 0x2378
#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c
#define L0_PLL_STATUS_READ_1 0x23e4
/* SSC step size parameters */
#define STEP_SIZE_0_MASK 0xff
#define STEP_SIZE_1_MASK 0xff
#define STEP_SIZE_2_MASK 0xff
#define STEP_SIZE_3_MASK 0x3
#define STEP_SIZE_SHIFT 8
#define FORCE_STEP_SIZE 0x10
#define FORCE_STEPS 0x20
#define STEPS_0_MASK 0xff
#define STEPS_1_MASK 0x07
/* Reference clock selection parameters */
#define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
#define L0_REF_CLK_SEL_MASK 0x8f
/* Calibration digital logic parameters */
#define L3_TM_CALIB_DIG19 0xec4c
#define L3_CALIB_DONE_STATUS 0xef14
#define L3_TM_CALIB_DIG18 0xec48
#define L3_TM_CALIB_DIG19_NSW 0x07
#define L3_TM_CALIB_DIG18_NSW 0xe0
#define L3_TM_OVERRIDE_NSW_CODE 0x20
#define L3_CALIB_DONE 0x02
#define L3_NSW_SHIFT 5
#define L3_NSW_PIPE_SHIFT 4
#define L3_NSW_CALIB_SHIFT 3
#define PHY_REG_OFFSET 0x4000
/*
* Global Registers
*/
/* Refclk selection parameters */
#define PLL_REF_SEL(n) (0x10000 + (n) * 4)
#define PLL_FREQ_MASK 0x1f
#define PLL_STATUS_LOCKED 0x10
/* Inter Connect Matrix parameters */
#define ICM_CFG0 0x10010
#define ICM_CFG1 0x10014
#define ICM_CFG0_L0_MASK 0x07
#define ICM_CFG0_L1_MASK 0x70
#define ICM_CFG1_L2_MASK 0x07
#define ICM_CFG2_L3_MASK 0x70
#define ICM_CFG_SHIFT 4
/* Inter Connect Matrix allowed protocols */
#define ICM_PROTOCOL_PD 0x0
#define ICM_PROTOCOL_PCIE 0x1
#define ICM_PROTOCOL_SATA 0x2
#define ICM_PROTOCOL_USB 0x3
#define ICM_PROTOCOL_DP 0x4
#define ICM_PROTOCOL_SGMII 0x5
/* Test Mode common reset control parameters */
#define TM_CMN_RST 0x10018
#define TM_CMN_RST_EN 0x1
#define TM_CMN_RST_SET 0x2
#define TM_CMN_RST_MASK 0x3
/* Bus width parameters */
#define TX_PROT_BUS_WIDTH 0x10040
#define RX_PROT_BUS_WIDTH 0x10044
#define PROT_BUS_WIDTH_10 0x0
#define PROT_BUS_WIDTH_20 0x1
#define PROT_BUS_WIDTH_40 0x2
#define PROT_BUS_WIDTH_MASK 0x3
#define PROT_BUS_WIDTH_SHIFT 2
/* Number of GT lanes */
#define NUM_LANES 4
/* SIOU SATA control register */
#define SATA_CONTROL_OFFSET 0x0100
/* Total number of controllers */
#define CONTROLLERS_PER_LANE 5
/* Protocol Type parameters */
enum {
XPSGTR_TYPE_USB0 = 0, /* USB controller 0 */
XPSGTR_TYPE_USB1 = 1, /* USB controller 1 */
XPSGTR_TYPE_SATA_0 = 2, /* SATA controller lane 0 */
XPSGTR_TYPE_SATA_1 = 3, /* SATA controller lane 1 */
XPSGTR_TYPE_PCIE_0 = 4, /* PCIe controller lane 0 */
XPSGTR_TYPE_PCIE_1 = 5, /* PCIe controller lane 1 */
XPSGTR_TYPE_PCIE_2 = 6, /* PCIe controller lane 2 */
XPSGTR_TYPE_PCIE_3 = 7, /* PCIe controller lane 3 */
XPSGTR_TYPE_DP_0 = 8, /* Display Port controller lane 0 */
XPSGTR_TYPE_DP_1 = 9, /* Display Port controller lane 1 */
XPSGTR_TYPE_SGMII0 = 10, /* Ethernet SGMII controller 0 */
XPSGTR_TYPE_SGMII1 = 11, /* Ethernet SGMII controller 1 */
XPSGTR_TYPE_SGMII2 = 12, /* Ethernet SGMII controller 2 */
XPSGTR_TYPE_SGMII3 = 13, /* Ethernet SGMII controller 3 */
};
/* Timeout values */
#define TIMEOUT_US 1000
#define IOU_SLCR_GEM_CLK_CTRL 0x308
#define GEM_CTRL_GEM_SGMII_MODE BIT(2)
#define GEM_CTRL_GEM_REF_SRC_SEL BIT(1)
#define IOU_SLCR_GEM_CTRL 0x360
#define GEM_CTRL_GEM_SGMII_SD BIT(0)
/**
* struct xpsgtr_ssc - structure to hold SSC settings for a lane
* @refclk_rate: PLL reference clock frequency
* @pll_ref_clk: value to be written to register for corresponding ref clk rate
* @steps: number of steps of SSC (Spread Spectrum Clock)
* @step_size: step size of each step
*/
struct xpsgtr_ssc {
u32 refclk_rate;
u8 pll_ref_clk;
u32 steps;
u32 step_size;
};
/**
* struct xpsgtr_phy - representation of a lane
* @dev: pointer to the xpsgtr_dev instance
* @refclk: reference clock index
* @type: controller which uses this lane
* @lane: lane number
* @protocol: protocol in which the lane operates
*/
struct xpsgtr_phy {
struct xpsgtr_dev *dev;
unsigned int refclk;
u8 type;
u8 lane;
u8 protocol;
};
/**
* struct xpsgtr_dev - representation of a ZynMP GT device
* @dev: pointer to device
* @serdes: serdes base address
* @siou: siou base address
* @phys: PHY lanes
* @refclk_sscs: spread spectrum settings for the reference clocks
* @clk: reference clocks
*/
struct xpsgtr_dev {
struct udevice *dev;
u8 *serdes;
u8 *siou;
struct xpsgtr_phy phys[NUM_LANES];
const struct xpsgtr_ssc *refclk_sscs[NUM_LANES];
struct clk clk[NUM_LANES];
};
/* Configuration Data */
/* lookup table to hold all settings needed for a ref clock frequency */
static const struct xpsgtr_ssc ssc_lookup[] = {
{ 19200000, 0x05, 608, 264020 },
{ 20000000, 0x06, 634, 243454 },
{ 24000000, 0x07, 760, 168973 },
{ 26000000, 0x08, 824, 143860 },
{ 27000000, 0x09, 856, 86551 },
{ 38400000, 0x0a, 1218, 65896 },
{ 40000000, 0x0b, 634, 243454 },
{ 52000000, 0x0c, 824, 143860 },
{ 100000000, 0x0d, 1058, 87533 },
{ 108000000, 0x0e, 856, 86551 },
{ 125000000, 0x0f, 992, 119497 },
{ 135000000, 0x10, 1070, 55393 },
{ 150000000, 0x11, 792, 187091 }
};
/* I/O Accessors */
static u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
{
return readl(gtr_dev->serdes + reg);
}
static void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
{
writel(value, gtr_dev->serdes + reg);
}
static void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
u32 clr, u32 set)
{
u32 value = xpsgtr_read(gtr_dev, reg);
value &= ~clr;
value |= set;
xpsgtr_write(gtr_dev, reg, value);
}
static u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg)
{
void __iomem *addr = gtr_phy->dev->serdes
+ gtr_phy->lane * PHY_REG_OFFSET + reg;
return readl(addr);
}
static void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy,
u32 reg, u32 value)
{
void __iomem *addr = gtr_phy->dev->serdes
+ gtr_phy->lane * PHY_REG_OFFSET + reg;
writel(value, addr);
}
static void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
u32 reg, u32 clr, u32 set)
{
void __iomem *addr = gtr_phy->dev->serdes
+ gtr_phy->lane * PHY_REG_OFFSET + reg;
writel((readl(addr) & ~clr) | set, addr);
}
/* Configure PLL and spread-sprectrum clock. */
static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
{
const struct xpsgtr_ssc *ssc;
u32 step_size;
ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];
step_size = ssc->step_size;
xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
PLL_FREQ_MASK, ssc->pll_ref_clk);
/* Enable lane clock sharing, if required */
if (gtr_phy->refclk != gtr_phy->lane) {
/* Lane3 Ref Clock Selection Register */
xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
}
/* SSC step size [7:0] */
xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK);
/* SSC step size [15:8] */
step_size >>= STEP_SIZE_SHIFT;
xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1,
STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK);
/* SSC step size [23:16] */
step_size >>= STEP_SIZE_SHIFT;
xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2,
STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK);
/* SSC steps [7:0] */
xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB,
STEPS_0_MASK, ssc->steps & STEPS_0_MASK);
/* SSC steps [10:8] */
xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB,
STEPS_1_MASK,
(ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);
/* SSC step size [24:25] */
step_size >>= STEP_SIZE_SHIFT;
xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB,
STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) |
FORCE_STEP_SIZE | FORCE_STEPS);
}
/* Configure the lane protocol. */
static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
{
struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
u8 protocol = gtr_phy->protocol;
switch (gtr_phy->lane) {
case 0:
xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol);
break;
case 1:
xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK,
protocol << ICM_CFG_SHIFT);
break;
case 2:
xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol);
break;
case 3:
xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK,
protocol << ICM_CFG_SHIFT);
break;
default:
/* We already checked 0 <= lane <= 3 */
break;
}
}
/* Bypass (de)scrambler and 8b/10b decoder and encoder. */
static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
{
xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER);
xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
}
/* SGMII-specific initialization. */
static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
{
struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
u32 shift = gtr_phy->lane * PROT_BUS_WIDTH_SHIFT;
/* Set SGMII protocol TX and RX bus width to 10 bits. */
xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, PROT_BUS_WIDTH_MASK << shift,
PROT_BUS_WIDTH_10 << shift);
xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, PROT_BUS_WIDTH_MASK << shift,
PROT_BUS_WIDTH_10 << shift);
xpsgtr_bypass_scrambler_8b10b(gtr_phy);
/*
* Below code is just temporary solution till we have a way how to
* do it via firmware interface in sync with Linux. Till that happen
* this is the most sensible thing to do here.
*/
/* GEM I/O Clock Control */
clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CLK_CTRL,
0xf << shift,
(GEM_CTRL_GEM_SGMII_MODE | GEM_CTRL_GEM_REF_SRC_SEL) <<
shift);
/* Setup signal detect */
clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CTRL,
PROT_BUS_WIDTH_MASK << shift,
GEM_CTRL_GEM_SGMII_SD << shift);
}
static int xpsgtr_init(struct phy *x)
{
struct xpsgtr_dev *gtr_dev = dev_get_priv(x->dev);
struct xpsgtr_phy *gtr_phy;
u32 phy_lane = x->id;
gtr_phy = &gtr_dev->phys[phy_lane];
/* Enable coarse code saturation limiting logic. */
xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT);
/*
* Configure the PLL, the lane protocol, and perform protocol-specific
* initialization.
*/
xpsgtr_configure_pll(gtr_phy);
xpsgtr_lane_set_protocol(gtr_phy);
switch (gtr_phy->protocol) {
case ICM_PROTOCOL_SGMII:
xpsgtr_phy_init_sgmii(gtr_phy);
break;
case ICM_PROTOCOL_DP:
case ICM_PROTOCOL_SATA:
return -EINVAL;
}
dev_dbg(gtr_dev->dev, "lane %u (type %u, protocol %u): init done\n",
gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
return 0;
}
/* Wait for the PLL to lock (with a timeout). */
static int xpsgtr_wait_pll_lock(struct phy *phy)
{
struct xpsgtr_dev *gtr_dev = dev_get_priv(phy->dev);
struct xpsgtr_phy *gtr_phy;
u32 phy_lane = phy->id;
int ret = 0;
unsigned int timeout = TIMEOUT_US;
gtr_phy = &gtr_dev->phys[phy_lane];
dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
while (1) {
u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) {
ret = 0;
break;
}
if (--timeout == 0) {
ret = -ETIMEDOUT;
break;
}
udelay(1);
}
if (ret == -ETIMEDOUT)
dev_err(gtr_dev->dev,
"lane %u (type %u, protocol %u): PLL lock timeout\n",
gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
return ret;
}
static int xpsgtr_power_on(struct phy *phy)
{
struct xpsgtr_dev *gtr_dev = dev_get_priv(phy->dev);
struct xpsgtr_phy *gtr_phy;
u32 phy_lane = phy->id;
int ret = 0;
gtr_phy = &gtr_dev->phys[phy_lane];
/*
* Wait for the PLL to lock. For DP, only wait on DP0 to avoid
* cumulating waits for both lanes. The user is expected to initialize
* lane 0 last.
*/
if (gtr_phy->protocol != ICM_PROTOCOL_DP ||
gtr_phy->type == XPSGTR_TYPE_DP_0)
ret = xpsgtr_wait_pll_lock(phy);
return ret;
}
/*
* OF Xlate Support
*/
/* Set the lane type and protocol based on the PHY type and instance number. */
static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
unsigned int phy_instance)
{
unsigned int num_phy_types;
const int *phy_types;
switch (phy_type) {
case PHY_TYPE_SATA: {
static const int types[] = {
XPSGTR_TYPE_SATA_0,
XPSGTR_TYPE_SATA_1,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
gtr_phy->protocol = ICM_PROTOCOL_SATA;
break;
}
case PHY_TYPE_USB3: {
static const int types[] = {
XPSGTR_TYPE_USB0,
XPSGTR_TYPE_USB1,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
gtr_phy->protocol = ICM_PROTOCOL_USB;
break;
}
case PHY_TYPE_DP: {
static const int types[] = {
XPSGTR_TYPE_DP_0,
XPSGTR_TYPE_DP_1,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
gtr_phy->protocol = ICM_PROTOCOL_DP;
break;
}
case PHY_TYPE_PCIE: {
static const int types[] = {
XPSGTR_TYPE_PCIE_0,
XPSGTR_TYPE_PCIE_1,
XPSGTR_TYPE_PCIE_2,
XPSGTR_TYPE_PCIE_3,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
gtr_phy->protocol = ICM_PROTOCOL_PCIE;
break;
}
case PHY_TYPE_SGMII: {
static const int types[] = {
XPSGTR_TYPE_SGMII0,
XPSGTR_TYPE_SGMII1,
XPSGTR_TYPE_SGMII2,
XPSGTR_TYPE_SGMII3,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
gtr_phy->protocol = ICM_PROTOCOL_SGMII;
break;
}
default:
return -EINVAL;
}
if (phy_instance >= num_phy_types)
return -EINVAL;
gtr_phy->type = phy_types[phy_instance];
return 0;
}
/*
* Valid combinations of controllers and lanes (Interconnect Matrix).
*/
static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
{ XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 },
{ XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0,
XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 },
{ XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 },
{ XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1,
XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 }
};
/* Translate OF phandle and args to PHY instance. */
static int xpsgtr_of_xlate(struct phy *x,
struct ofnode_phandle_args *args)
{
struct xpsgtr_dev *gtr_dev = dev_get_priv(x->dev);
struct xpsgtr_phy *gtr_phy;
struct udevice *dev = x->dev;
unsigned int phy_instance;
unsigned int phy_lane;
unsigned int phy_type;
unsigned int refclk;
unsigned int i;
int ret;
if (args->args_count != 4) {
dev_err(dev, "Invalid number of cells in 'phy' property\n");
return -EINVAL;
}
/*
* Get the PHY parameters from the OF arguments and derive the lane
* type.
*/
phy_lane = args->args[0];
if (phy_lane >= NUM_LANES) {
dev_err(dev, "Invalid lane number %u\n", phy_lane);
return -EINVAL;
}
gtr_phy = &gtr_dev->phys[phy_lane];
phy_type = args->args[1];
phy_instance = args->args[2];
ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance);
if (ret) {
dev_err(dev, "Invalid PHY type and/or instance\n");
return ret;
}
refclk = args->args[3];
if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||
!gtr_dev->refclk_sscs[refclk]) {
dev_err(dev, "Invalid reference clock number %u\n", refclk);
return -EINVAL;
}
gtr_phy->refclk = refclk;
/* This is difference compare to Linux */
gtr_phy->dev = gtr_dev;
gtr_phy->lane = phy_lane;
/*
* Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
* is allowed to operate on the lane.
*/
for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
if (icm_matrix[phy_lane][i] == gtr_phy->type) {
x->id = phy_lane;
return 0;
}
}
return -EINVAL;
}
/*
* Probe & Platform Driver
*/
static int xpsgtr_get_ref_clocks(struct udevice *dev)
{
unsigned int refclk;
struct xpsgtr_dev *gtr_dev = dev_get_priv(dev);
int ret;
for (refclk = 0; refclk < NUM_LANES; ++refclk) {
int i;
u32 rate;
char name[8];
struct clk *clk = &gtr_dev->clk[refclk];
snprintf(name, sizeof(name), "ref%u", refclk);
dev_dbg(dev, "Checking name: %s\n", name);
ret = clk_get_by_name(dev, name, clk);
if (ret == -ENODATA) {
dev_dbg(dev, "%s clock not specified (err %d)\n",
name, ret);
continue;
} else if (ret) {
dev_dbg(dev, "couldn't get clock %s (err %d)\n",
name, ret);
return ret;
}
rate = clk_get_rate(clk);
dev_dbg(dev, "clk rate %d\n", rate);
ret = clk_enable(clk);
if (ret) {
dev_err(dev, "failed to enable refclk %d clock\n",
refclk);
return ret;
}
for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
if (rate == ssc_lookup[i].refclk_rate) {
gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];
dev_dbg(dev, "Found rate %d\n", i);
break;
}
}
if (i == ARRAY_SIZE(ssc_lookup)) {
dev_err(dev,
"Invalid rate %u for reference clock %u\n",
rate, refclk);
return -EINVAL;
}
}
return 0;
}
static int xpsgtr_probe(struct udevice *dev)
{
struct xpsgtr_dev *gtr_dev = dev_get_priv(dev);
gtr_dev->serdes = dev_remap_addr_name(dev, "serdes");
if (!gtr_dev->serdes)
return -EINVAL;
gtr_dev->siou = dev_remap_addr_name(dev, "siou");
if (!gtr_dev->siou)
return -EINVAL;
gtr_dev->dev = dev;
return xpsgtr_get_ref_clocks(dev);
}
static const struct udevice_id xpsgtr_phy_ids[] = {
{ .compatible = "xlnx,zynqmp-psgtr-v1.1", },
{ }
};
static const struct phy_ops xpsgtr_phy_ops = {
.init = xpsgtr_init,
.of_xlate = xpsgtr_of_xlate,
.power_on = xpsgtr_power_on,
};
U_BOOT_DRIVER(psgtr_phy) = {
.name = "psgtr_phy",
.id = UCLASS_PHY,
.of_match = xpsgtr_phy_ids,
.ops = &xpsgtr_phy_ops,
.probe = xpsgtr_probe,
.priv_auto = sizeof(struct xpsgtr_dev),
};

1
drivers/serial/serial_zynq.c
View File

@ -272,6 +272,7 @@ static const struct udevice_id zynq_serial_ids[] = {
{ .compatible = "xlnx,xuartps" },
{ .compatible = "cdns,uart-r1p8" },
{ .compatible = "cdns,uart-r1p12" },
{ .compatible = "xlnx,zynqmp-uart" },
{ }
};

6
drivers/sysreset/sysreset_microblaze.c
View File

@ -8,13 +8,15 @@
#include <errno.h>
#include <sysreset.h>
#include <linux/err.h>
#include <linux/stringify.h>
static int microblaze_sysreset_request(struct udevice *dev,
enum sysreset_t type)
{
puts("Microblaze soft reset sysreset\n");
__asm__ __volatile__ (" mts rmsr, r0;" \
"bra r0");
__asm__ __volatile__ (
"mts rmsr, r0;" \
"brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR));
return -EINPROGRESS;
}

5
include/configs/microblaze-generic.h
View File

@ -21,9 +21,6 @@
# define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* setting reset address */
/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
/* Stack location before relocation */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_F_LEN)
@ -57,8 +54,6 @@
#define CONFIG_HOSTNAME "microblaze-generic"
/* architecture dependent code */
#define CONFIG_SYS_USR_EXCEP /* user exception */
#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else

3
include/dt-bindings/power/xlnx-versal-power.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 - 2020 Xilinx, Inc.
* Copyright (C) 2019 - 2021 Xilinx, Inc.
*/
#ifndef _DT_BINDINGS_VERSAL_POWER_H
@ -26,6 +26,7 @@
#define PM_DEV_OSPI (0x1822402aU)
#define PM_DEV_QSPI (0x1822402bU)
#define PM_DEV_GPIO_PMC (0x1822402cU)
#define PM_DEV_I2C_PMC (0x1822402dU)
#define PM_DEV_SDIO_0 (0x1822402eU)
#define PM_DEV_SDIO_1 (0x1822402fU)
#define PM_DEV_RTC (0x18224034U)

9
net/Kconfig
View File

@ -27,10 +27,11 @@ config BOOTP_SEND_HOSTNAME
config NET_RANDOM_ETHADDR
bool "Random ethaddr if unset"
help
Selecting this will allow the Ethernet interface to function
even when the ethaddr variable for that interface is unset.
A new MAC address will be generated on every boot and it will
not be added to the environment.
Selecting this will allow the Ethernet interface to function even
when the ethaddr variable for that interface is unset. In this case,
a random MAC address in the locally administered address space is
generated. It will be saved to the appropriate environment variable,
too.
config NETCONSOLE
bool "NetConsole support"

2
net/eth-uclass.c
View File

@ -583,6 +583,8 @@ static int eth_post_probe(struct udevice *dev)
net_random_ethaddr(pdata->enetaddr);
printf("\nWarning: %s (eth%d) using random MAC address - %pM\n",
dev->name, dev_seq(dev), pdata->enetaddr);
eth_env_set_enetaddr_by_index("eth", dev_seq(dev),
pdata->enetaddr);
#else
printf("\nError: %s address not set.\n",
dev->name);

2
net/eth_legacy.c
View File

@ -164,6 +164,8 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
net_random_ethaddr(dev->enetaddr);
printf("\nWarning: %s (eth%d) using random MAC address - %pM\n",
dev->name, eth_number, dev->enetaddr);
eth_env_set_enetaddr_by_index("eth", eth_number,
dev->enetaddr);
#else
printf("\nError: %s address not set.\n",
dev->name);

1
scripts/config_whitelist.txt
View File

@ -2015,7 +2015,6 @@ CONFIG_SYS_USE_MMC
CONFIG_SYS_USE_NAND
CONFIG_SYS_USE_NANDFLASH
CONFIG_SYS_USE_NORFLASH
CONFIG_SYS_USR_EXCEP
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT