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Merge tag 'u-boot-rockchip-20240812' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

Browse Source 
Please pull the updates for rockchip platform:
- Add board support:
        RK3566: Radxa ROCK 3 Model C
                Radxa ZERO 3W/3E
                Xunlong Orange Pi 3B
        RK3568J: Radxa ROCK 3B
        RK3308B: Radxa ROCK S0
        RK3588: Radxa ROCK 5 ITX
                FriendlyElec CM3588 NAS board
- dw-mmc: allow 4-bit mode;
- dts and config updates;

CI:
https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/21997
This commit is contained in:
Tom Rini 2024-08-12 07:58:24 -06:00
commit 06dceeba3d
92 changed files with 9280 additions and 7668 deletions
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4
arch/arm/dts/px30-firefly.dts
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@ -13,6 +13,10 @@
model = "Firefly Core-PX30-JD4";
compatible = "rockchip,px30-firefly", "rockchip,px30";
aliases {
ethernet0 = &gmac;
};
chosen {
stdout-path = "serial2:115200n8";
};

4
arch/arm/dts/px30-u-boot.dtsi
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@ -99,16 +99,20 @@
&gpio0 {
bootph-all;
gpio-ranges = <&pinctrl 0 0 32>;
};
&gpio1 {
bootph-all;
gpio-ranges = <&pinctrl 0 32 32>;
};
&gpio2 {
bootph-all;
gpio-ranges = <&pinctrl 0 64 32>;
};
&gpio3 {
bootph-all;
gpio-ranges = <&pinctrl 0 96 32>;
};

2415
arch/arm/dts/px30.dtsi
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File diff suppressed because it is too large Load Diff

19
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
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@ -4,17 +4,6 @@
*/
#include "rk3308-u-boot.dtsi"
&emmc {
cap-sd-highspeed;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>;
};
&emmc_bus4 {
bootph-pre-ram;
bootph-some-ram;
};
&u2phy_otg {
/delete-property/ phy-supply;
};
@ -24,14 +13,6 @@
clock-frequency = <24000000>;
};
&uart0_cts {
bootph-all;
};
&uart0_rts {
bootph-all;
};
&uart0_xfer {
bootph-all;
};

21
arch/arm/dts/rk3308-rock-s0-u-boot.dtsi Normal file
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@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3308-u-boot.dtsi"
&emmc_pwren {
bootph-pre-ram;
bootph-some-ram;
};
&uart0 {
bootph-all;
clock-frequency = <24000000>;
};
&uart0_xfer {
bootph-all;
};
&vdd_core {
regulator-init-microvolt = <1015000>;
};

16
arch/arm/dts/rk3308-u-boot.dtsi
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@ -21,22 +21,6 @@
bootph-all;
};
otp: nvmem@ff210000 {
compatible = "rockchip,rk3308-otp";
reg = <0x0 0xff210000 0x0 0x4000>;
clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
<&cru PCLK_OTP_PHY>;
clock-names = "otp", "apb_pclk", "phy";
resets = <&cru SRST_OTP_PHY>;
reset-names = "phy";
#address-cells = <1>;
#size-cells = <1>;
cpu_id: id@7 {
reg = <0x07 0x10>;
};
};
rng: rng@ff2f0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff2f0000 0x0 0x4000>;

4
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
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@ -48,18 +48,22 @@
&gpio0 {
bootph-all;
gpio-ranges = <&pinctrl 0 0 32>;
};
&gpio1 {
bootph-all;
gpio-ranges = <&pinctrl 0 32 32>;
};
&gpio2 {
bootph-all;
gpio-ranges = <&pinctrl 0 64 32>;
};
&gpio3 {
bootph-all;
gpio-ranges = <&pinctrl 0 96 32>;
};
&grf {

15
arch/arm/dts/rk3326.dtsi
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@ -1,15 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
*/
#include "px30.dtsi"
&display_subsystem {
ports = <&vopb_out>;
};
/delete-node/ &dsi_in_vopl;
/delete-node/ &lvds_vopl_in;
/delete-node/ &vopl;
/delete-node/ &vopl_mmu;

14
arch/arm/dts/rk3566-orangepi-3b-u-boot.dtsi Normal file
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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk356x-u-boot.dtsi"
&gpio4 {
bootph-pre-ram;
};
&sfc {
flash@0 {
bootph-pre-ram;
bootph-some-ram;
};
};

3
arch/arm/dts/rk3566-orangepi-3b-v1.1-u-boot.dtsi Normal file
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@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3566-orangepi-3b-u-boot.dtsi"

3
arch/arm/dts/rk3566-orangepi-3b-v1.1.dts Normal file
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@ -0,0 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <arm64/rockchip/rk3566-orangepi-3b-v1.1.dts>

3
arch/arm/dts/rk3566-orangepi-3b-v2.1-u-boot.dtsi Normal file
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@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3566-orangepi-3b-u-boot.dtsi"

3
arch/arm/dts/rk3566-orangepi-3b-v2.1.dts Normal file
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@ -0,0 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <arm64/rockchip/rk3566-orangepi-3b-v2.1.dts>

5
arch/arm/dts/rk3566-orangepi-3b.dts Normal file
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@ -0,0 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <arm64/rockchip/rk3566-orangepi-3b.dtsi>

28
arch/arm/dts/rk3566-pinetab2-v0.1.dts
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@ -1,28 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-pinetab2.dtsi"
/ {
model = "Pine64 PineTab2 v0.1";
compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566";
};
&lcd {
reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>;
};
&pinctrl {
lcd0 {
lcd0_rst_l: lcd0-rst-l {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdmmc1 {
vmmc-supply = <&vcc3v3_sys>;
};

48
arch/arm/dts/rk3566-pinetab2-v2.0.dts
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@ -1,48 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-pinetab2.dtsi"
/ {
model = "Pine64 PineTab2 v2.0";
compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566";
};
&gpio_keys {
pinctrl-0 = <&kb_id_det>, <&hall_int_l>;
event-hall-sensor {
debounce-interval = <20>;
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
label = "Hall Sensor";
linux,code = <SW_LID>;
linux,input-type = <EV_SW>;
wakeup-event-action = <EV_ACT_DEASSERTED>;
wakeup-source;
};
};
&lcd {
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>;
};
&pinctrl {
lcd0 {
lcd0_rst_l: lcd0-rst-l {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hall {
hall_int_l: hall-int-l {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdmmc1 {
vmmc-supply = <&vcc_sys>;
};

943
arch/arm/dts/rk3566-pinetab2.dtsi
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@ -1,943 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include <dt-bindings/usb/pd.h>
#include "rk3566.dtsi"
/ {
chassis-type = "tablet";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc0;
};
chosen {
stdout-path = "serial2:1500000n8";
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <25>;
button-vol-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <297500>;
};
button-vol-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <1750>;
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 25000 0>;
brightness-levels = <20 220>;
num-interpolated-steps = <200>;
default-brightness-level = <100>;
power-supply = <&vcc_sys>;
};
battery: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <6000000>;
charge-term-current-microamp = <300000>;
constant-charge-current-max-microamp = <2000000>;
constant-charge-voltage-max-microvolt = <4300000>;
voltage-max-design-microvolt = <4350000>;
voltage-min-design-microvolt = <3400000>;
ocv-capacity-celsius = <20>;
ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>,
<4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>,
<3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>,
<3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>,
<3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>,
<3400000 0>;
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&kb_id_det>;
tablet-mode-switch {
debounce-interval = <20>;
gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
label = "Tablet Mode";
linux,input-type = <EV_SW>;
linux,code = <SW_TABLET_MODE>;
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "d";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
led-0 {
compatible = "regulator-led";
vled-supply = <&vcc5v0_flashled>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_FLASH;
};
rk817-sound {
compatible = "simple-audio-card";
pinctrl-names = "default";
pinctrl-0 = <&hp_det_l>;
simple-audio-card,format = "i2s";
simple-audio-card,name = "rk817_ext";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphones",
"Speaker", "Internal Speakers";
simple-audio-card,routing =
"MICR", "Mic Jack",
"Headphones", "HPOL",
"Headphones", "HPOR",
"Internal Speakers", "Speaker Amplifier OUTL",
"Internal Speakers", "Speaker Amplifier OUTR",
"Speaker Amplifier INL", "HPOL",
"Speaker Amplifier INR", "HPOR";
simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
simple-audio-card,aux-devs = <&speaker_amp>;
simple-audio-card,pin-switches = "Internal Speakers";
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk817>;
};
};
speaker_amp: speaker-amplifier {
compatible = "simple-audio-amplifier";
pinctrl-names = "default";
pinctrl-0 = <&spk_ctl>;
enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
sound-name-prefix = "Speaker Amplifier";
VCC-supply = <&vcc_bat>;
};
vcc_3v3: vcc-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
vcc3v3_minipcie: vcc3v3-minipcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwren_h>;
regulator-name = "vcc3v3_minipcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_sys>;
};
vcc3v3_sd: vcc3v3-sd-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren_l>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
vcc5v0_flashled: vcc5v0-flashled-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&flash_led_en_h>;
regulator-name = "vcc5v0_flashled";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v_midu>;
};
vcc5v0_usb_host0: vcc5v0-usb-host0-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_host_pwren1_h>;
regulator-name = "vcc5v0_usb_host0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v_midu>;
};
vcc5v0_usb_host2: vcc5v0-usb-host2-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_host_pwren2_h>;
regulator-name = "vcc5v0_usb_host2";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v_midu>;
};
vcc_bat: vcc-bat-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_bat";
regulator-always-on;
regulator-boot-on;
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_bat>;
};
vdd1v2_dvp: vdd1v2-dvp-regulator {
compatible = "regulator-fixed";
regulator-name = "vdd1v2_dvp";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vcc_3v3>;
};
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&cru {
assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
<&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>;
assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
};
&csi_dphy {
status = "okay";
};
&dsi0 {
status = "okay";
clock-master;
#address-cells = <1>;
#size-cells = <0>;
lcd: panel@0 {
compatible = "boe,th101mb31ig002-28a";
reg = <0>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
rotation = <90>;
power-supply = <&vcc_3v3>;
port@0 {
panel_in_dsi: endpoint@0 {
remote-endpoint = <&dsi0_out_con>;
};
};
};
};
&dsi0_in {
dsi0_in_vp1: endpoint {
remote-endpoint = <&vp1_out_dsi0>;
};
};
&dsi0_out {
dsi0_out_con: endpoint {
remote-endpoint = <&panel_in_dsi>;
};
};
&dsi_dphy0 {
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu_npu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda_0v9_p>;
avdd-1v8-supply = <&vcc_1v8>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
#clock-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
rockchip,system-power-controller;
#sound-dai-cells = <0>;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_sys>;
vcc9-supply = <&vcc5v_midu>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu_npu: DCDC_REG2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu_npu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_sys: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x2>;
regulator-name = "vcc3v3_sys";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdda_0v9_p: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9_p";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pmu";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc2v8_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc5v_midu: BOOST {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "boost";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vbus: OTG_SWITCH {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "otg_switch";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
charger {
monitored-battery = <&battery>;
rockchip,resistor-sense-micro-ohms = <10000>;
rockchip,sleep-enter-current-microamp = <300000>;
rockchip,sleep-filter-current-microamp = <100000>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
touchscreen@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB0 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>;
AVDD28-supply = <&vcc3v3_pmu>;
VDDIO-supply = <&vcca1v8_pmu>;
irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c2m1_xfer>;
status = "okay";
vcm@c {
compatible = "dongwoon,dw9714";
reg = <0x0c>;
vcc-supply = <&vcc1v8_dvp>;
};
camera@36 {
compatible = "ovti,ov5648";
reg = <0x36>;
pinctrl-names = "default";
pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>;
clocks = <&cru CLK_CIF_OUT>;
assigned-clocks = <&cru CLK_CIF_OUT>;
assigned-clock-rates = <24000000>;
avdd-supply = <&vcc2v8_dvp>;
dvdd-supply = <&vdd1v2_dvp>;
dovdd-supply = <&vcc1v8_dvp>;
powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
port {
endpoint {
data-lanes = <1 2>;
remote-endpoint = <0>;
link-frequencies = /bits/ 64 <210000000 168000000>;
};
};
};
};
&i2c5 {
clock-frequency = <400000>;
status = "okay";
accelerometer@18 {
compatible = "silan,sc7a20";
reg = <0x18>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&gsensor_int_l>;
st,drdy-int-pin = <1>;
vdd-supply = <&vcc_1v8>;
vddio-supply = <&vcc_1v8>;
mount-matrix = "1", "0", "0",
"0", "0", "1",
"0", "1", "0";
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx
&i2s1m0_sdi0
&i2s1m0_sdo0>;
rockchip,trcm-sync-tx-only;
status = "okay";
};
&pcie2x1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_h>;
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_minipcie>;
status = "okay";
};
&pinctrl {
camerab {
camerab_pdn_l: camerab-pdn-l {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
camerab_rst_l: camerab-rst-l {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
cameraf {
cameraf_pdn_l: cameraf-pdn-l {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
cameraf_rst_l: cameraf-rst-l {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
flash {
flash_led_en_h: flash-led-en-h {
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
fspi {
fspi_dual_io_pins: fspi-dual-io-pins {
rockchip,pins =
/* fspi_clk */
<1 RK_PD0 1 &pcfg_pull_none>,
/* fspi_cs0n */
<1 RK_PD3 1 &pcfg_pull_none>,
/* fspi_d0 */
<1 RK_PD1 1 &pcfg_pull_none>,
/* fspi_d1 */
<1 RK_PD2 1 &pcfg_pull_none>;
};
};
gsensor {
gsensor_int_l: gsensor-int-l {
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
kb {
kb_id_det: kb-id-det {
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcd_pwren_h: lcd-pwren-h {
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_pwren_h: pcie-pwren-h {
rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_reset_h: pcie-reset-h {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_pwren_l: sdmmc-pwren-l {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sound {
hp_det_l: hp-det-l {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
spk_ctl: spk-ctl {
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
tp {
tp_int_l_pmuio2: tp-int-l-pmuio2 {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
tp_rst_l_pmuio2: tp-rst-l-pmuio2 {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
usbcc_int_l: usbcc-int-l {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb_host_pwren1_h: usb-host-pwren1-h {
rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb_host_pwren2_h: usb-host-pwren2-h {
rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
host_wake_wl: host-wake-wl {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_wake_host_h: wifi-wake-host-h {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcca1v8_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_1v8>;
vccio6-supply = <&vcc1v8_dvp>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&pwm4 {
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
max-frequency = <200000000>;
mmc-hs200-1_8v;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8
&emmc_clk
&emmc_cmd
&emmc_datastrobe
&emmc_rstnout>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4
&sdmmc0_clk
&sdmmc0_cmd
&sdmmc0_det>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc1 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4
&sdmmc1_cmd
&sdmmc1_clk>;
sd-uhs-sdr104;
vqmmc-supply = <&vcca1v8_pmu>;
status = "okay";
};
&sfc {
pinctrl-names = "default";
pinctrl-0 = <&fspi_dual_io_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <1>;
};
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host0>;
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host2>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};
&vp1 {
vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
reg = <ROCKCHIP_VOP2_EP_MIPI0>;
remote-endpoint = <&dsi0_in_vp1>;
};
};

15
arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk356x-u-boot.dtsi"
&saradc {
bootph-pre-ram;
};
&usb_host0_xhci {
dr_mode = "otg";
};
&vcca_1v8 {
bootph-pre-ram;
};

15
arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk356x-u-boot.dtsi"
&saradc {
bootph-pre-ram;
};
&usb_host0_xhci {
dr_mode = "otg";
};
&vcca_1v8 {
bootph-pre-ram;
};

18
arch/arm/dts/rk3566-rock-3c-u-boot.dtsi Normal file
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk356x-u-boot.dtsi"
&sfc {
flash@0 {
bootph-pre-ram;
bootph-some-ram;
};
};
/ {
leds {
led-0 {
default-state = "on";
};
};
};

0
arch/arm/dts/rk3568-evb-u-boot.dtsi → arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
View File

13
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
View File

@ -26,17 +26,12 @@
};
&sfc {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
bootph-pre-ram;
bootph-some-ram;
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&usb_host0_ohci {
status = "disabled";
};

15
arch/arm/dts/rk3568-rock-3b-u-boot.dtsi Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk356x-u-boot.dtsi"
&sdhci {
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&sfc {
flash@0 {
bootph-pre-ram;
bootph-some-ram;
};
};

8
arch/arm/dts/rk3588-friendlyelec-cm3588-nas-u-boot.dtsi Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588-u-boot.dtsi"
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
};

22
arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Collabora Ltd.
*/
#include "rk3588-u-boot.dtsi"
&fspim2_pins {
bootph-pre-ram;
bootph-some-ram;
};
&sfc {
flash@0 {
bootph-pre-ram;
bootph-some-ram;
};
};
&vcc3v3_mkey {
regulator-always-on;
};

17
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
View File

@ -39,18 +39,6 @@
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_otg {
status = "okay";
};
&usbdp_phy1 {
status = "okay";
};
&usbdp_phy0 {
status = "okay";
};
@ -60,8 +48,3 @@
maximum-speed = "high-speed";
status = "okay";
};
&usb_host1_xhci {
dr_mode = "host";
status = "okay";
};

344
arch/arm/dts/rockchip-pinconf.dtsi
View File

@ -1,344 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
&pinctrl {
/omit-if-no-ref/
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
/omit-if-no-ref/
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
/omit-if-no-ref/
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
bias-disable;
drive-strength = <0>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
bias-disable;
drive-strength = <1>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
bias-disable;
drive-strength = <2>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
bias-disable;
drive-strength = <3>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
bias-disable;
drive-strength = <4>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
bias-disable;
drive-strength = <5>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
bias-disable;
drive-strength = <6>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
bias-disable;
drive-strength = <7>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
bias-disable;
drive-strength = <8>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
bias-disable;
drive-strength = <9>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
bias-disable;
drive-strength = <10>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
bias-disable;
drive-strength = <11>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
bias-disable;
drive-strength = <12>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
bias-disable;
drive-strength = <13>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
bias-disable;
drive-strength = <14>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
bias-disable;
drive-strength = <15>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
bias-pull-up;
drive-strength = <0>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
bias-pull-up;
drive-strength = <1>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
bias-pull-up;
drive-strength = <2>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
bias-pull-up;
drive-strength = <3>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
bias-pull-up;
drive-strength = <4>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
bias-pull-up;
drive-strength = <5>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
bias-pull-up;
drive-strength = <6>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
bias-pull-up;
drive-strength = <7>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
bias-pull-up;
drive-strength = <8>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
bias-pull-up;
drive-strength = <9>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
bias-pull-up;
drive-strength = <10>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
bias-pull-up;
drive-strength = <11>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
bias-pull-up;
drive-strength = <12>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
bias-pull-up;
drive-strength = <13>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
bias-pull-up;
drive-strength = <14>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
bias-pull-up;
drive-strength = <15>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
bias-pull-down;
drive-strength = <0>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
bias-pull-down;
drive-strength = <1>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
bias-pull-down;
drive-strength = <2>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
bias-pull-down;
drive-strength = <3>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
bias-pull-down;
drive-strength = <4>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
bias-pull-down;
drive-strength = <5>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
bias-pull-down;
drive-strength = <6>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
bias-pull-down;
drive-strength = <7>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
bias-pull-down;
drive-strength = <8>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
bias-pull-down;
drive-strength = <9>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
bias-pull-down;
drive-strength = <10>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
bias-pull-down;
drive-strength = <11>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
bias-pull-down;
drive-strength = <12>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
bias-pull-down;
drive-strength = <13>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
bias-pull-down;
drive-strength = <14>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
bias-pull-down;
drive-strength = <15>;
};
/omit-if-no-ref/
pcfg_pull_up_smt: pcfg-pull-up-smt {
bias-pull-up;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_down_smt: pcfg-pull-down-smt {
bias-pull-down;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_smt: pcfg-pull-none-smt {
bias-disable;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
bias-disable;
drive-strength = <0>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_output_high: pcfg-output-high {
output-high;
};
/omit-if-no-ref/
pcfg_output_low: pcfg-output-low {
output-low;
};
};

3
arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
View File

@ -16,4 +16,7 @@ U_BOOT_DRIVER(syscon_rk3308) = {
.name = "rk3308_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3308_syscon_ids,
#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
};

12
arch/arm/mach-rockchip/rk3568/Kconfig
View File

@ -32,6 +32,16 @@ config TARGET_QUARTZ64_RK3566
help
Pine64 Quartz64 single board computer with a RK3566 SoC.
config TARGET_RADXA_ZERO_3_RK3566
bool "Radxa ZERO 3W/3E"
help
Radxa ZERO 3W/3E single board computers with a RK3566 SoC.
config TARGET_ORANGEPI_3B_RK3566
bool "Xunlong Orange Pi 3B"
help
Xunlong Orange Pi 3B single board computer with a RK3566 SoC.
endchoice
config ROCKCHIP_BOOT_MODE_REG
@ -54,5 +64,7 @@ source "board/anbernic/rgxx3_rk3566/Kconfig"
source "board/hardkernel/odroid_m1/Kconfig"
source "board/pine64/quartz64_rk3566/Kconfig"
source "board/powkiddy/x55/Kconfig"
source "board/radxa/zero3-rk3566/Kconfig"
source "board/xunlong/orangepi-3b-rk3566/Kconfig"
endif

53
arch/arm/mach-rockchip/rk3588/Kconfig
View File

@ -6,6 +6,29 @@ config TARGET_EVB_RK3588
help
RK3588 EVB is a evaluation board for Rockchp RK3588.
config TARGET_CM3588_NAS_RK3588
bool "FriendlyElec CM3588 NAS"
select BOARD_LATE_INIT
help
The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based
on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board.
Hardware features:
- Rockchip RK3588 SoC
- 4GB/8GB/16GB LPDDR4x RAM
- 0GB/64GB HS400 eMMC
- MicroSD card slot
- 1x RTL8125B 2.5G Ethernet
- 4x M.2 M-Key with PCIe 3.0 x1 (via bifurcation) for NVMe SSDs
- 2x USB 3.0 (USB 3.1 Gen1) Type-A, 1x USB 2.0 Type-A
- 1x USB 3.0 Type-C with DP AltMode support
- 2x HDMI 2.1 out, 1x HDMI in
- MIPI-CSI Connector, MIPI-DSI Connector
- 40-pin GPIO header
- 4 buttons: power, reset, recovery, MASK, user button
- 3.5mm Headphone out, 2.0mm PH-2A Mic in
- 5V Fan connector, PWM beeper, IR receiver, RTC battery connector
config TARGET_JAGUAR_RK3588
bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)"
select BOARD_LATE_INIT
@ -185,6 +208,34 @@ config TARGET_ROCK5B_RK3588
USB PD over USB Type-C
Size: 100mm x 72mm (Pico-ITX form factor)
config TARGET_ROCK_5_ITX_RK3588
bool "Radxa ROCK-5-ITX RK3588 board"
select BOARD_LATE_INIT
help
Radxa ROCK-5-ITX is a Rockchip RK3588 based SBC (Single Board
Computer) by Radxa in the ITX formfactor.
There are variants depending on the DRAM size : from 4G up to 32G.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16/24/32GB memory LPDDR5
Mali G610MC4 GPU
2x MIPI CSI 2 multiple lanes connector
eMMC
uSD slot (up to 128GB)
M.2 M-key and M.2 E-key connector
4x SATA
2x USB 2.0 + 4x USB 3.0 Type-A, 2x USB 2.0 Panel, 1x USB 3.0 Type-C
2x HDMI 2.1 output, 1x HDMI input
DP via Type-C
2x DSI via PCB connector
2x 2.5 Gbps Ethernet port
Front-panel connectors for audio and case-power, -leds
Powered by either 12V, ATX power-supply or PoE
config TARGET_SIGE7_RK3588
bool "ArmSoM Sige7 RK3588 board"
select BOARD_LATE_INIT
@ -311,6 +362,7 @@ config TEXT_BASE
source "board/armsom/sige7-rk3588/Kconfig"
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/cm3588-nas-rk3588/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig"
source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig"
@ -319,6 +371,7 @@ source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"
source "board/radxa/rock5b-rk3588/Kconfig"
source "board/radxa/rock-5-itx-rk3588/Kconfig"
source "board/rockchip/evb_rk3588/Kconfig"
source "board/rockchip/toybrick_rk3588/Kconfig"
source "board/theobroma-systems/jaguar_rk3588/Kconfig"

12
board/friendlyelec/cm3588-nas-rk3588/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_CM3588_NAS_RK3588
config SYS_BOARD
default "cm3588-nas-rk3588"
config SYS_VENDOR
default "friendlyelec"
config SYS_CONFIG_NAME
default "nanopc-t6-rk3588"
endif

6
board/friendlyelec/cm3588-nas-rk3588/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
CM3588-NAS-RK3588
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/friendlyelec/cm3588-nas-rk3588
F: configs/cm3588-nas-rk3588_defconfig
F: arch/arm/dts/rk3588-friendlyelec-cm3588-nas*

12
board/radxa/rock-5-itx-rk3588/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_ROCK_5_ITX_RK3588
config SYS_BOARD
default "rock-5-itx-rk3588"
config SYS_VENDOR
default "radxa"
config SYS_CONFIG_NAME
default "rock-5-itx-rk3588"
endif

8
board/radxa/rock-5-itx-rk3588/MAINTAINERS Normal file
View File

@ -0,0 +1,8 @@
ROCK-5-ITX-RK3588
M: Heiko Stuebner <heiko@sntech.de>
R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/radxa/rock-5-itx-rk3588
F: include/configs/rock-5-itx-rk3588.h
F: configs/rock-5-itx-rk3588_defconfig
F: arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi

12
board/radxa/zero3-rk3566/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_RADXA_ZERO_3_RK3566
config SYS_BOARD
default "zero3-rk3566"
config SYS_VENDOR
default "radxa"
config SYS_CONFIG_NAME
default "evb_rk3568"
endif

6
board/radxa/zero3-rk3566/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
RADXA-ZERO-3-RK3566
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/radxa/zero3-rk3566
F: configs/radxa-zero-3-rk3566_defconfig
F: arch/arm/dts/rk3566-radxa-zero-3*

3
board/radxa/zero3-rk3566/Makefile Normal file
View File

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += zero3-rk3566.o

59
board/radxa/zero3-rk3566/zero3-rk3566.c Normal file
View File

@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0+
#include <linux/errno.h>
#include <linux/kernel.h>
#include <adc.h>
#include <env.h>
#define HW_ID_CHANNEL 1
struct board_model {
unsigned int low;
unsigned int high;
const char *fdtfile;
};
static const struct board_model board_models[] = {
{ 230, 270, "rockchip/rk3566-radxa-zero-3w.dtb" },
{ 400, 450, "rockchip/rk3566-radxa-zero-3e.dtb" },
};
static const struct board_model *get_board_model(void)
{
unsigned int val;
int i, ret;
ret = adc_channel_single_shot("saradc@fe720000", HW_ID_CHANNEL, &val);
if (ret)
return NULL;
for (i = 0; i < ARRAY_SIZE(board_models); i++) {
unsigned int min = board_models[i].low;
unsigned int max = board_models[i].high;
if (min <= val && val <= max)
return &board_models[i];
}
return NULL;
}
int rk_board_late_init(void)
{
const struct board_model *model = get_board_model();
if (model)
env_set("fdtfile", model->fdtfile);
return 0;
}
int board_fit_config_name_match(const char *name)
{
const struct board_model *model = get_board_model();
if (model && !strcmp(name, model->fdtfile))
return 0;
return -EINVAL;
}

6
board/rockchip/evb_rk3308/MAINTAINERS
View File

@ -12,3 +12,9 @@ R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: configs/rock-pi-s-rk3308_defconfig
F: arch/arm/dts/rk3308-rock-pi-s*
ROCK-S0
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: configs/rock-s0-rk3308_defconfig
F: arch/arm/dts/rk3308-rock-s0*

13
board/rockchip/evb_rk3568/MAINTAINERS
View File

@ -69,3 +69,16 @@ S: Maintained
F: configs/rock-3a-rk3568_defconfig
F: arch/arm/dts/rk3568-rock-3a.dts
F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
ROCK-3B
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: configs/rock-3b-rk3568_defconfig
F: arch/arm/dts/rk3568-rock-3b*
ROCK-3C
M: Jonas Karlman <jonas@kwiboo.se>
M: Maxim Moskalets <maximmosk4@gmail.com>
S: Maintained
F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
F: configs/rock-3c-rk3566_defconfig

12
board/xunlong/orangepi-3b-rk3566/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_ORANGEPI_3B_RK3566
config SYS_BOARD
default "orangepi-3b-rk3566"
config SYS_VENDOR
default "xunlong"
config SYS_CONFIG_NAME
default "evb_rk3568"
endif

6
board/xunlong/orangepi-3b-rk3566/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
ORANGEPI-3B-RK3566
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/xunlong/orangepi-3b-rk3566
F: configs/orangepi-3b-rk3566_defconfig
F: arch/arm/dts/rk3566-orangepi-3b*

3
board/xunlong/orangepi-3b-rk3566/Makefile Normal file
View File

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += orangepi-3b-rk3566.o

77
board/xunlong/orangepi-3b-rk3566/orangepi-3b-rk3566.c Normal file
View File

@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0+
#include <env.h>
#include <asm/gpio.h>
struct board_model {
int value;
const char *fdtfile;
const char *config;
};
static const struct board_model board_models[] = {
{ 0, "rockchip/rk3566-orangepi-3b-v1.1.dtb", "rk3566-orangepi-3b-v1.1.dtb" },
{ 1, "rockchip/rk3566-orangepi-3b-v2.1.dtb", "rk3566-orangepi-3b-v2.1.dtb" },
};
static int get_board_value(void)
{
struct gpio_desc desc;
int ret;
/*
* GPIO4_C4 (E20):
* v1.1.1: x (internal pull-down)
* v2.1: PHY_RESET (external pull-up)
*/
ret = dm_gpio_lookup_name("E20", &desc);
if (ret)
return ret;
ret = dm_gpio_request(&desc, "phy_reset");
if (ret && ret != -EBUSY)
return ret;
dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
ret = dm_gpio_get_value(&desc);
dm_gpio_free(desc.dev, &desc);
return ret;
}
static const struct board_model *get_board_model(void)
{
int i, val;
val = get_board_value();
if (val < 0)
return NULL;
for (i = 0; i < ARRAY_SIZE(board_models); i++) {
if (val == board_models[i].value)
return &board_models[i];
}
return NULL;
}
int rk_board_late_init(void)
{
const struct board_model *model = get_board_model();
if (model)
env_set("fdtfile", model->fdtfile);
return 0;
}
int board_fit_config_name_match(const char *name)
{
const struct board_model *model = get_board_model();
if (model && (!strcmp(name, model->fdtfile) ||
!strcmp(name, model->config)))
return 0;
return -EINVAL;
}

90
configs/cm3588-nas-rk3588_defconfig Normal file
View File

@ -0,0 +1,90 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-friendlyelec-cm3588-nas"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_CM3588_NAS_RK3588=y
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-friendlyelec-cm3588-nas.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
CONFIG_SPL_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHYLIB=y
CONFIG_RTL8169=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

1
configs/nanopi-r5c-rk3568_defconfig
View File

@ -35,7 +35,6 @@ CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y

1
configs/nanopi-r5s-rk3568_defconfig
View File

@ -35,7 +35,6 @@ CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y

98
configs/orangepi-3b-rk3566_defconfig Normal file
View File

@ -0,0 +1,98 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-orangepi-3b"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_ORANGEPI_3B_RK3566=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-orangepi-3b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_LIST="rk3566-orangepi-3b rk3566-orangepi-3b-v1.1 rk3566-orangepi-3b-v2.1"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=4
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_PHY_MOTORCOMM=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y

5
configs/pinetab2-rk3566_defconfig
View File

@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-pinetab2-v2.0"
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-pinetab2-v2.0"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
@ -47,8 +47,7 @@ CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_LIST="rk3566-pinetab2-v0.1 rk3566-pinetab2-v2.0"
CONFIG_OF_LIST="rockchip/rk3566-pinetab2-v0.1 rockchip/rk3566-pinetab2-v2.0"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y

10
configs/puma-rk3399_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_CONSOLE_MUX=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x38000
@ -40,7 +41,6 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
@ -102,12 +102,4 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
CONFIG_ERRNO_STR=y

85
configs/radxa-zero-3-rk3566_defconfig Normal file
View File

@ -0,0 +1,85 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-radxa-zero-3w"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_RADXA_ZERO_3_RK3566=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-zero-3w.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_LIST="rockchip/rk3566-radxa-zero-3w rockchip/rk3566-radxa-zero-3e"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_ADC=y
CONFIG_SPL_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

100
configs/rock-3b-rk3568_defconfig Normal file
View File

@ -0,0 +1,100 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-rock-3b"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=4
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

97
configs/rock-3c-rk3566_defconfig Normal file
View File

@ -0,0 +1,97 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-rock-3c"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-rock-3c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=4
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y

111
configs/rock-5-itx-rk3588_defconfig Normal file
View File

@ -0,0 +1,111 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-rock-5-itx"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_ROCK5B_RK3588=y
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5-itx.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_AHCI_PCI=y
CONFIG_DWC_AHCI=y
CONFIG_SPL_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=5
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_PHYLIB=y
CONFIG_RTL8169=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_LAN75XX=y
CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

4
configs/rock-pi-s-rk3308_defconfig
View File

@ -38,10 +38,14 @@ CONFIG_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

72
configs/rock-s0-rk3308_defconfig Normal file
View File

@ -0,0 +1,72 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-s0"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_DEBUG_UART_BASE=0xFF0A0000
CONFIG_DEBUG_UART_CLOCK=24000000
# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-s0.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_RNG=y
CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y

1
configs/rock5b-rk3588_defconfig
View File

@ -39,6 +39,7 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set

3
configs/toybrick-rk3588_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0"
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-toybrick-x0"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_TOYBRICK_RK3588=y
@ -31,7 +31,6 @@ CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM_SEQ_ALIAS=y

9
doc/board/rockchip/rockchip.rst
View File

@ -54,6 +54,7 @@ List of mainline supported Rockchip boards:
- Amarula Vyasa-RK3288 (vyasa-rk3288)
* rk3308
- Radxa ROCK Pi S (rock-pi-s-rk3308)
- Radxa ROCK S0 (rock-s0-rk3308)
- Rockchip Evb-RK3308 (evb-rk3308)
- Roc-cc-RK3308 (roc-cc-rk3308)
* rk3326
@ -105,6 +106,9 @@ List of mainline supported Rockchip boards:
- Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
- Powkiddy X55 (powkiddy-x55-rk3566)
- Radxa CM3 IO Board (radxa-cm3-io-rk3566)
- Radxa ROCK 3C (rock-3c-rk3566)
- Radxa ZERO 3W/3E (radxa-zero-3-rk3566)
- Xunlong Orange Pi 3B (orangepi-3b-rk3566)
* rk3568
- Rockchip Evb-RK3568 (evb-rk3568)
@ -115,19 +119,22 @@ List of mainline supported Rockchip boards:
- Generic RK3566/RK3568 (generic-rk3568)
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
- Radxa E25 Carrier Board (radxa-e25-rk3568)
- Radxa ROCK 3 Model A (rock-3a-rk3568)
- Radxa ROCK 3A (rock-3a-rk3568)
- Radxa ROCK 3B (rock-3b-rk3568)
* rk3588
- ArmSoM Sige7 (sige7-rk3588)
- Rockchip EVB (evb-rk3588)
- Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
- FriendlyElec CM3588 NAS (cm3588-nas-rk3588)
- FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
- FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
- FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)
- Generic RK3588S/RK3588 (generic-rk3588)
- Indiedroid Nova (nova-rk3588s)
- Pine64 QuartzPro64 (quartzpro64-rk3588)
- Radxa ROCK 5 ITX (rock-5-itx-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)

2
drivers/Makefile
View File

@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_$(SPL_TPL_)ADC) += adc/
obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/
obj-$(CONFIG_$(SPL_TPL_)BLK) += block/
obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
@ -81,7 +82,6 @@ endif
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-y += adc/
obj-y += ata/
obj-$(CONFIG_DM_DEMO) += demo/
obj-y += block/

5
drivers/adc/Kconfig
View File

@ -1,5 +1,6 @@
config ADC
bool "Enable ADC drivers using Driver Model"
depends on DM
help
This enables ADC API for drivers, which allows driving ADC features
by single and multi-channel methods for:
@ -11,6 +12,10 @@ config ADC
- support supply's phandle with auto-enable
- supply polarity setting in fdt
config SPL_ADC
bool "Enable ADC drivers using Driver Model in SPL"
depends on SPL_DM
config ADC_EXYNOS
bool "Enable Exynos 54xx ADC driver"
depends on ADC

2
drivers/adc/Makefile
View File

@ -4,7 +4,7 @@
# Przemyslaw Marczak <p.marczak@samsung.com>
#
obj-$(CONFIG_ADC) += adc-uclass.o
obj-$(CONFIG_$(SPL_TPL_)ADC) += adc-uclass.o
obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o
obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o

37
drivers/misc/rockchip-io-domain.c
View File

@ -31,6 +31,10 @@
#define PX30_IO_VSEL_VCCIO6_SRC BIT(0)
#define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1
#define RK3308_SOC_CON0 0x300
#define RK3308_SOC_CON0_VCCIO3 BIT(8)
#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3
#define RK3328_SOC_CON4 0x410
#define RK3328_SOC_CON4_VCCIO2 BIT(7)
#define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
@ -119,6 +123,22 @@ static int px30_iodomain_write(struct regmap *grf, uint offset, int idx, int uV)
return ret;
}
static int rk3308_iodomain_write(struct regmap *grf, uint offset, int idx, int uV)
{
int ret = rockchip_iodomain_write(grf, offset, idx, uV);
if (!ret && idx == RK3308_SOC_VCCIO3_SUPPLY_NUM) {
/*
* set vccio3 iodomain to also use this framework
* instead of a special gpio.
*/
u32 val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
ret = regmap_write(grf, RK3308_SOC_CON0, val);
}
return ret;
}
static int rk3328_iodomain_write(struct regmap *grf, uint offset, int idx, int uV)
{
int ret = rockchip_iodomain_write(grf, offset, idx, uV);
@ -189,6 +209,19 @@ static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = {
.write = rockchip_iodomain_write,
};
static const struct rockchip_iodomain_soc_data soc_data_rk3308 = {
.grf_offset = 0x300,
.supply_names = {
"vccio0-supply",
"vccio1-supply",
"vccio2-supply",
"vccio3-supply",
"vccio4-supply",
"vccio5-supply",
},
.write = rk3308_iodomain_write,
};
static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
.grf_offset = 0x410,
.supply_names = {
@ -256,6 +289,10 @@ static const struct udevice_id rockchip_iodomain_ids[] = {
.compatible = "rockchip,px30-pmu-io-voltage-domain",
.data = (ulong)&soc_data_px30_pmu,
},
{
.compatible = "rockchip,rk3308-io-voltage-domain",
.data = (ulong)&soc_data_rk3308,
},
{
.compatible = "rockchip,rk3328-io-voltage-domain",
.data = (ulong)&soc_data_rk3328,

4
drivers/mmc/rockchip_dw_mmc.c
View File

@ -159,6 +159,10 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
host->mmc->dev = dev;
upriv->mmc = host->mmc;
/* Hosts capable of 8-bit can also do 4 bits */
if (host->buswidth == 8)
plat->cfg.host_caps |= MMC_MODE_4BIT;
return dwmci_probe(dev);
}

46
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
View File

@ -67,12 +67,15 @@ struct rockchip_combphy_grfcfg {
};
struct rockchip_combphy_cfg {
unsigned int num_phys;
unsigned int phy_ids[3];
const struct rockchip_combphy_grfcfg *grfcfg;
int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
};
struct rockchip_combphy_priv {
u32 mode;
int id;
void __iomem *mmio;
struct udevice *dev;
struct regmap *pipe_grf;
@ -270,8 +273,13 @@ static int rockchip_combphy_probe(struct udevice *udev)
{
struct rockchip_combphy_priv *priv = dev_get_priv(udev);
const struct rockchip_combphy_cfg *phy_cfg;
fdt_addr_t addr = dev_read_addr(udev);
if (addr == FDT_ADDR_T_NONE) {
dev_err(udev, "No valid device address found\n");
return -EINVAL;
}
priv->mmio = (void __iomem *)dev_read_addr(udev);
priv->mmio = (void __iomem *)addr;
if (IS_ERR(priv->mmio))
return PTR_ERR(priv->mmio);
@ -281,6 +289,20 @@ static int rockchip_combphy_probe(struct udevice *udev)
return -EINVAL;
}
/* Find the phy-id based on the device's I/O-address */
priv->id = -ENODEV;
for (int id = 0; id < phy_cfg->num_phys; id++) {
if (addr == phy_cfg->phy_ids[id]) {
priv->id = id;
break;
}
}
if (priv->id == -ENODEV) {
dev_err(udev, "Failed to find PHY ID\n");
return -ENODEV;
}
priv->dev = udev;
priv->mode = PHY_TYPE_SATA;
priv->cfg = phy_cfg;
@ -421,6 +443,12 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
};
static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
.num_phys = 3,
.phy_ids = {
0xfe820000,
0xfe830000,
0xfe840000,
},
.grfcfg = &rk3568_combphy_grfcfgs,
.combphy_cfg = rk3568_combphy_cfg,
};
@ -436,8 +464,14 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
switch (priv->id) {
case 1:
param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
break;
case 2:
param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
break;
}
break;
case PHY_TYPE_USB3:
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
@ -515,6 +549,12 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
};
static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
.num_phys = 3,
.phy_ids = {
0xfee00000,
0xfee10000,
0xfee20000,
},
.grfcfg = &rk3588_combphy_grfcfgs,
.combphy_cfg = rk3588_combphy_cfg,
};

81
dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts
View File

@ -17,6 +17,7 @@
ethernet0 = &gmac;
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdio;
};
chosen {
@ -144,11 +145,25 @@
&gmac {
clock_in_out = "output";
phy-handle = <&rtl8201f>;
phy-supply = <&vcc_io>;
snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
rtl8201f: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&mac_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
};
};
};
&gpio0 {
@ -217,10 +232,40 @@
status = "okay";
};
&io_domains {
vccio0-supply = <&vcc_io>;
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc_io>;
vccio3-supply = <&vcc_io>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_io>;
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
bluetooth {
bt_reg_on: bt-reg-on {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host: bt-wake-host {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
host_wake_bt: host-wake-bt {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gmac {
mac_rst: mac-rst {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
green_led: green-led {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
@ -264,15 +309,31 @@
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <1000000>;
max-frequency = <100000000>;
mmc-pwrseq = <&sdio_pwrseq>;
no-mmc;
no-sd;
non-removable;
sd-uhs-sdr104;
sd-uhs-sdr50;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
rtl8723ds: wifi@1 {
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake>;
};
};
&sdmmc {
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
vmmc-supply = <&vcc_io>;
status = "okay";
};
@ -291,16 +352,22 @@
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "okay";
};
&uart4 {
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "realtek,rtl8723bs-bt";
device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
compatible = "realtek,rtl8723ds-bt";
device-wake-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>;
};
};

293
dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts Normal file
View File

@ -0,0 +1,293 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "rk3308.dtsi"
/ {
model = "Radxa ROCK S0";
compatible = "radxa,rock-s0", "rockchip,rk3308";
aliases {
ethernet0 = &gmac;
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdio;
};
chosen {
stdout-path = "serial0:1500000n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pwr_led>;
led-green {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
vdd_log: regulator-1v04-vdd-log {
compatible = "regulator-fixed";
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1040000>;
regulator-max-microvolt = <1040000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_ddr: regulator-1v5-vcc-ddr {
compatible = "regulator-fixed";
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_1v8: regulator-1v8-vcc {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_io>;
};
vcc_io: regulator-3v3-vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: regulator-5v0-vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vdd_core: regulator-vdd-core {
compatible = "pwm-regulator";
pwms = <&pwm0 0 5000 1>;
pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_core";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>;
regulator-settling-time-up-us = <250>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_reg_on>;
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
};
};
&cpu0 {
cpu-supply = <&vdd_core>;
};
&emmc {
cap-mmc-highspeed;
no-sd;
no-sdio;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_pwren>;
vmmc-supply = <&vcc_io>;
status = "okay";
};
&gmac {
clock_in_out = "output";
phy-handle = <&rtl8201f>;
phy-supply = <&vcc_io>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
rtl8201f: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&mac_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
};
};
};
&io_domains {
vccio0-supply = <&vcc_io>;
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc_io>;
vccio3-supply = <&vcc_io>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_io>;
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
bluetooth {
bt_reg_on: bt-reg-on {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host: bt-wake-host {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
host_wake_bt: host-wake-bt {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gmac {
mac_rst: mac-rst {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
pwr_led: pwr-led {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_reg_on: wifi-reg-on {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_wake_host: wifi-wake-host {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin_pull_down>;
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdio {
#address-cells = <1>;
#size-cells = <0>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <50000000>;
mmc-pwrseq = <&sdio_pwrseq>;
no-mmc;
no-sd;
non-removable;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_wake_host>;
};
};
&sdmmc {
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
vmmc-supply = <&vcc_io>;
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "okay";
};
&uart4 {
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43430a1-bt";
clocks = <&cru SCLK_RTC32K>;
clock-names = "lpo";
interrupt-parent = <&gpio4>;
interrupts = <RK_PB4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wakeup";
device-wakeup-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>;
vbat-supply = <&vcc_io>;
vddio-supply = <&vcc_1v8>;
};
};
&usb_host_ehci {
status = "okay";
};
&usb_host_ohci {
status = "okay";
};
&usb20_otg {
dr_mode = "peripheral";
status = "okay";
};
&wdt {
status = "okay";
};

29
dts/upstream/src/arm64/rockchip/rk3308.dtsi
View File

@ -173,6 +173,11 @@
compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
reg = <0x0 0xff000000 0x0 0x08000>;
io_domains: io-domains {
compatible = "rockchip,rk3308-io-voltage-domain";
status = "disabled";
};
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x500>;
@ -556,6 +561,30 @@
status = "disabled";
};
otp: efuse@ff210000 {
compatible = "rockchip,rk3308-otp";
reg = <0x0 0xff210000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
<&cru PCLK_OTP_PHY>;
clock-names = "otp", "apb_pclk", "phy";
resets = <&cru SRST_OTP_PHY>;
reset-names = "phy";
cpu_id: id@7 {
reg = <0x07 0x10>;
};
cpu_leakage: cpu-leakage@17 {
reg = <0x17 0x1>;
};
logic_leakage: logic-leakage@18 {
reg = <0x18 0x1>;
};
};
dmac0: dma-controller@ff2c0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff2c0000 0x0 0x4000>;

29
dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b-v1.1.dts Normal file
View File

@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-orangepi-3b.dtsi"
/ {
model = "Xunlong Orange Pi 3B v1.1";
compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566";
};
&pmu_io_domains {
vccio5-supply = <&vcc_3v3>;
};
&gmac1 {
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-assert-us = <20000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
};
};

70
dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b-v2.1.dts Normal file
View File

@ -0,0 +1,70 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-orangepi-3b.dtsi"
/ {
model = "Xunlong Orange Pi 3B v2.1";
compatible = "xunlong,orangepi-3b-v2.1", "xunlong,orangepi-3b", "rockchip,rk3566";
vccio_phy1: regulator-1v8-vccio-phy {
compatible = "regulator-fixed";
regulator-name = "vccio_phy1";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
};
&pmu_io_domains {
vccio5-supply = <&vccio_phy1>;
};
&gmac1 {
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-assert-us = <20000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
};
};
&sdmmc1 {
#address-cells = <1>;
#size-cells = <0>;
brcmf: wifi@1 {
compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD6 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_wake_host_h>;
};
};
&uart1 {
bluetooth {
compatible = "brcm,bcm4345c5";
clocks = <&rk809 1>;
clock-names = "lpo";
interrupt-parent = <&gpio2>;
interrupts = <RK_PC0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wakeup";
device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on_h &bt_wake_host_h &host_wake_bt_h>;
vbat-supply = <&vcc_3v3>;
vddio-supply = <&vcc_1v8>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
model = "Xunlong Orange Pi 3B";
compatible = "xunlong,orangepi-3b", "rockchip,rk3566";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
};
chosen {
stdout-path = "serial2:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&work_led>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
vcc3v3_pcie30: regulator-3v3-vcc-pcie30 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie20_pwren>;
regulator-name = "vcc3v3_pcie30";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
vcc3v3_sys: regulator-3v3-vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: regulator-5v0-vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_usb_host: regulator-5v0-vcc-usb-host {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_host_pwren_h>;
regulator-name = "vcc5v0_usb_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_otg_pwren_h>;
regulator-name = "vcc5v0_usb_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_reg_on_h>;
post-power-on-delay-ms = <200>;
power-off-delay-us = <5000000>;
reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "Analog RK809";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809>;
};
};
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
clock_in_out = "input";
phy-mode = "rgmii-id";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m0_miim
&gmac1m0_tx_bus2
&gmac1m0_rx_bus2
&gmac1m0_rgmii_clk
&gmac1m0_rgmii_bus
&gmac1m0_clkinout>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
clocks = <&cru I2S1_MCLKOUT_TX>;
clock-names = "mclk";
clock-output-names = "rk809-clkout1", "rk809-clkout2";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
#sound-dai-cells = <0>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <830000>;
regulator-max-microvolt = <1200000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx
&i2s1m0_sdi0
&i2s1m0_sdo0>;
rockchip,trcm-sync-tx-only;
status = "okay";
};
&pcie2x1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie20_pins>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
status = "okay";
};
&pinctrl {
bluetooth {
bt_reg_on_h: bt-reg-on-h {
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host_h: bt-wake-host-h {
rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
};
host_wake_bt_h: host-wake-bt-h {
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
work_led: work-led {
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie20_pins: pcie20-pins {
rockchip,pins =
<1 RK_PB0 4 &pcfg_pull_none>,
<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PB1 4 &pcfg_pull_none>;
};
pcie20_pwren: pcie20-pwren {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
usb_host_pwren_h: usb-host-pwren-h {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb_otg_pwren_h: usb-otg-pwren-h {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_reg_on_h: wifi-reg-on-h {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_wake_host_h: wifi-wake-host-h {
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio6-supply = <&vcc_3v3>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdhci {
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc1 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
no-mmc;
no-sd;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sfc {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy0_otg {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
chosen {
stdout-path = "serial2:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "d";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_led2>;
led-green {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
vcc_1v8: regulator-1v8-vcc {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8_p>;
};
vcca_1v8: regulator-1v8-vcca {
compatible = "regulator-fixed";
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8_p>;
};
vcca1v8_image: regulator-1v8-vcca-image {
compatible = "regulator-fixed";
regulator-name = "vcca1v8_image";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8_p>;
};
vcc_3v3: regulator-3v3-vcc {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
vcc_sys: regulator-5v0-vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&combphy1 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpio0 {
gpio-line-names =
/* GPIO0_A0 - A7 */
"", "", "", "", "", "", "", "",
/* GPIO0_B0 - B7 */
"", "", "", "", "", "", "", "",
/* GPIO0_C0 - C7 */
"", "", "", "", "", "", "", "",
/* GPIO0_D0 - D7 */
"pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "",
"", "", "", "", "";
};
&gpio1 {
gpio-line-names =
/* GPIO1_A0 - A7 */
"pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "",
"", "pin-37 [GPIO1_A4]", "",
"", "",
/* GPIO1_B0 - B7 */
"", "", "", "", "", "", "", "",
/* GPIO1_C0 - C7 */
"", "", "", "", "", "", "", "",
/* GPIO1_D0 - D7 */
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
/* GPIO2_A0 - A7 */
"", "", "", "", "", "", "", "",
/* GPIO2_B0 - B7 */
"", "", "", "", "", "", "", "",
/* GPIO2_C0 - C7 */
"", "", "", "", "", "", "", "",
/* GPIO2_D0 - D7 */
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
/* GPIO3_A0 - A7 */
"", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]",
"pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]",
"pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]",
/* GPIO3_B0 - B7 */
"pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]",
"pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "",
"", "",
/* GPIO3_C0 - C7 */
"", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]",
"pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "",
"", "",
/* GPIO3_D0 - D7 */
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names =
/* GPIO4_A0 - A7 */
"", "", "", "", "", "", "", "",
/* GPIO4_B0 - B7 */
"", "", "pin-27 [GPIO4_B2]",
"pin-28 [GPIO4_B3]", "", "", "", "",
/* GPIO4_C0 - C7 */
"", "", "pin-23 [GPIO4_C2]",
"pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]",
"pin-24 [GPIO4_C6]", "",
/* GPIO4_D0 - D7 */
"", "", "", "", "", "", "", "";
};
&gpu {
mali-supply = <&vdd_gpu_npu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda_0v9>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
#clock-cells = <1>;
clock-output-names = "rk817-clkout1", "rk817-clkout2";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_sys>;
vcc9-supply = <&vcc5v_midu>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_gpu_npu: DCDC_REG2 {
regulator-name = "vdd_gpu_npu";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_sys: DCDC_REG4 {
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca1v8_pmu: LDO_REG1 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_1v8_p: LDO_REG7 {
regulator-name = "vcc_1v8_p";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-name = "vcc1v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc2v8_dvp: LDO_REG9 {
regulator-name = "vcc2v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc5v_midu: BOOST {
regulator-name = "vcc5v_midu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vbus: OTG_SWITCH {
regulator-name = "vbus";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu: regulator@40 {
compatible = "rockchip,rk8600";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2s0_8ch {
status = "okay";
};
&pinctrl {
leds {
user_led2: user-led2 {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcca1v8_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_3v3>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sys>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "peripheral";
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

52
dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3e.dts Normal file
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@ -0,0 +1,52 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-radxa-zero-3.dtsi"
/ {
model = "Radxa ZERO 3E";
compatible = "radxa,zero-3e", "rockchip,rk3566";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdmmc0;
};
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
clock_in_out = "input";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus
&gmac1m1_clkinout>;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1_rstn>;
reset-assert-us = <20000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
gmac1 {
gmac1_rstn: gmac1-rstn {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

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@ -0,0 +1,92 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-radxa-zero-3.dtsi"
/ {
model = "Radxa ZERO 3W";
compatible = "radxa,zero-3w", "rockchip,rk3566";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk817 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_reg_on_h>;
post-power-on-delay-ms = <100>;
power-off-delay-us = <5000000>;
reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
bluetooth {
bt_reg_on_h: bt-reg-on-h {
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host_h: bt-wake-host-h {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
host_wake_bt_h: host-wake-bt-h {
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_reg_on_h: wifi-reg-on-h {
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_wake_host_h: wifi-wake-host-h {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdhci {
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc1 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
no-mmc;
no-sd;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
uart-has-rtscts;
status = "okay";
};

2
dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts
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@ -633,7 +633,7 @@
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <120000000>;
spi-max-frequency = <104000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
model = "Radxa ROCK 3B";
compatible = "radxa,rock-3b", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc2;
};
chosen {
stdout-path = "serial2:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_ir>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
/* pi6c pcie clock generator */
vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwren_h>;
regulator-name = "vcc3v3_pi6c_03";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <10000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sys: regulator-3v3-vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sys2: regulator-3v3-vcc-sys2 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys2";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: regulator-5v0-vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_usb_host: regulator-5v0-vcc-usb-host {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_host_pwren_h>;
regulator-name = "vcc5v0_usb_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_otg_pwren_h>;
regulator-name = "vcc5v0_usb_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_reg_on_h>;
post-power-on-delay-ms = <100>;
power-off-delay-us = <5000000>;
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "Analog RK809";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809>;
};
};
};
&combphy0 {
status = "okay";
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
clock_in_out = "input";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii-id";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&gmac0_clkinout>;
status = "okay";
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
clock_in_out = "input";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus
&gmac1m1_clkinout>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
clocks = <&cru I2S1_MCLKOUT_TX>;
clock-names = "mclk";
clock-output-names = "rk809-clkout1", "rk809-clkout2";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
#sound-dai-cells = <0>;
system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2c5 {
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
clock-output-names = "rtcic_32kout";
pinctrl-names = "default";
pinctrl-0 = <&rtcic_int_l>;
wakeup-source;
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx
&i2s1m0_sdi0
&i2s1m0_sdo0>;
rockchip,trcm-sync-tx-only;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-assert-us = <20000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-assert-us = <20000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
};
};
&pcie2x1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie20m1_pins>;
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys2>;
status = "okay";
};
&pcie30phy {
status = "okay";
};
&pcie3x2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie30x2m1_pins>;
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pinctrl {
bluetooth {
bt_reg_on_h: bt-reg-on-h {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host_h: bt-wake-host-h {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
host_wake_bt_h: host-wake-bt-h {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
ir-receiver {
pwm3_ir: pwm3-ir {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led: led {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_pwren_h: pcie-pwren-h {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie20 {
pcie20m1_pins: pcie20m1-pins {
rockchip,pins =
<2 RK_PD0 4 &pcfg_pull_none>,
<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,
<2 RK_PD1 4 &pcfg_pull_none>;
};
};
pcie30x2 {
pcie30x2m1_pins: pcie30x2m1-pins {
rockchip,pins =
<2 RK_PD4 4 &pcfg_pull_none>,
<2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>,
<2 RK_PD5 4 &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rtc {
rtcic_int_l: rtcic-int-l {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
usb_host_pwren_h: usb-host-pwren-h {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb_otg_pwren_h: usb-otg-pwren-h {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_reg_on_h: wifi-reg-on-h {
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_wake_host_h: wifi-wake-host-h {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdhci {
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc2 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sys2>;
vqmmc-supply = <&vcc_1v8>;
status = "disabled";
};
&sfc {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
uart-has-rtscts;
status = "disabled";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
extcon = <&usb2phy0>;
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy0_otg {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include "rk3588-base.dtsi"
#include "rk3588-extra-pinctrl.dtsi"
/ {
usb_host1_xhci: usb@fc400000 {
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfc400000 0x0 0x400000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
<&cru ACLK_USB3OTG1>;
clock-names = "ref_clk", "suspend_clk", "bus_clk";
dr_mode = "otg";
phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3588_PD_USB>;
resets = <&cru SRST_A_USB3OTG1>;
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
status = "disabled";
};
pcie30_phy_grf: syscon@fd5b8000 {
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
reg = <0x0 0xfd5b8000 0x0 0x10000>;
};
pipe_phy1_grf: syscon@fd5c0000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
reg = <0x0 0xfd5c0000 0x0 0x100>;
};
usbdpphy1_grf: syscon@fd5cc000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5cc000 0x0 0x4000>;
};
usb2phy1_grf: syscon@fd5d4000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d4000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy1: usb2phy@4000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x4000 0x10>;
#clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy1";
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
reset-names = "phy", "apb";
status = "disabled";
u2phy1_otg: otg-port {
#phy-cells = <0>;
status = "disabled";
};
};
};
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 22>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO0>;
resets = <&cru SRST_M_I2S8_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s6_8ch: i2s@fddf4000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddf4000 0x0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 4>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S6_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s7_8ch: i2s@fddf8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddf8000 0x0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 21>;
dma-names = "rx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S7_8CH_RX>;
reset-names = "rx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s10_8ch: i2s@fde00000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfde00000 0x0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 24>;
dma-names = "rx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S10_8CH_RX>;
reset-names = "rx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
pcie3x4: pcie@fe150000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0x0f>;
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
<0 0 0 2 &pcie3x4_intc 1>,
<0 0 0 3 &pcie3x4_intc 2>,
<0 0 0 4 &pcie3x4_intc 3>;
linux,pci-domain = <0>;
max-link-speed = <3>;
msi-map = <0x0000 &its1 0x0000 0x1000>;
num-lanes = <4>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
reg = <0xa 0x40000000 0x0 0x00400000>,
<0x0 0xfe150000 0x0 0x00010000>,
<0x0 0xf0000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
reset-names = "pwr", "pipe";
status = "disabled";
pcie3x4_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
};
};
pcie3x2: pcie@fe160000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
<0 0 0 2 &pcie3x2_intc 1>,
<0 0 0 3 &pcie3x2_intc 2>,
<0 0 0 4 &pcie3x2_intc 3>;
linux,pci-domain = <1>;
max-link-speed = <3>;
msi-map = <0x1000 &its1 0x1000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
<0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
reg = <0xa 0x40400000 0x0 0x00400000>,
<0x0 0xfe160000 0x0 0x00010000>,
<0x0 0xf1000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
reset-names = "pwr", "pipe";
status = "disabled";
pcie3x2_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
};
};
pcie2x1l0: pcie@fe170000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
<0 0 0 2 &pcie2x1l0_intc 1>,
<0 0 0 3 &pcie2x1l0_intc 2>,
<0 0 0 4 &pcie2x1l0_intc 3>;
linux,pci-domain = <2>;
max-link-speed = <2>;
msi-map = <0x2000 &its0 0x2000 0x1000>;
num-lanes = <1>;
phys = <&combphy1_ps PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
reg = <0xa 0x40800000 0x0 0x00400000>,
<0x0 0xfe170000 0x0 0x00010000>,
<0x0 0xf2000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
reset-names = "pwr", "pipe";
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie2x1l0_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
};
};
gmac0: ethernet@fe1b0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1b0000 0x0 0x10000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
<&cru CLK_GMAC0_PTP_REF>;
clock-names = "stmmaceth", "clk_mac_ref",
"pclk_mac", "aclk_mac",
"ptp_ref";
power-domains = <&power RK3588_PD_GMAC>;
resets = <&cru SRST_A_GMAC0>;
reset-names = "stmmaceth";
rockchip,grf = <&sys_grf>;
rockchip,php-grf = <&php_grf>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
snps,mixed-burst;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,tso;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,wr_osr_lmt = <4>;
snps,rd_osr_lmt = <8>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <2>;
queue0 {};
queue1 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <2>;
queue0 {};
queue1 {};
};
};
sata1: sata@fe220000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
reg = <0 0xfe220000 0 0x1000>;
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
ports-implemented = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
phys = <&combphy1_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
snps,rx-ts-max = <32>;
snps,tx-ts-max = <32>;
};
};
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;
#phy-cells = <1>;
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
<&cru CLK_USBDP_PHY1_IMMORTAL>,
<&cru PCLK_USBDPPHY1>,
<&u2phy1>;
clock-names = "refclk", "immortal", "pclk", "utmi";
resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
<&cru SRST_USBDP_COMBO_PHY1_CMN>,
<&cru SRST_USBDP_COMBO_PHY1_LANE>,
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
<&cru SRST_P_USBDPPHY1>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
rockchip,u2phy-grf = <&usb2phy1_grf>;
rockchip,usb-grf = <&usb_grf>;
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
rockchip,vo-grf = <&vo0_grf>;
status = "disabled";
};
combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;
clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
<&cru PCLK_PHP_ROOT>;
clock-names = "ref", "apb", "pipe";
assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
assigned-clock-rates = <100000000>;
#phy-cells = <1>;
resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
reset-names = "phy", "apb";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
status = "disabled";
};
pcie30phy: phy@fee80000 {
compatible = "rockchip,rk3588-pcie3-phy";
reg = <0x0 0xfee80000 0x0 0x20000>;
#phy-cells = <0>;
clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
clock-names = "pclk";
resets = <&cru SRST_PCIE30_PHY>;
reset-names = "phy";
rockchip,pipe-grf = <&php_grf>;
rockchip,phy-grf = <&pcie30_phy_grf>;
status = "disabled";
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 Thomas McKahan
* Copyright (c) 2024 Sebastian Kropatsch
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/usb/pd.h>
#include "rk3588-friendlyelec-cm3588.dtsi"
/ {
model = "FriendlyElec CM3588 NAS";
compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
adc_key_recovery: adc-key-recovery {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <17000>;
};
};
analog-sound {
compatible = "simple-audio-card";
pinctrl-names = "default";
pinctrl-0 = <&headphone_detect>;
simple-audio-card,format = "i2s";
simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "realtek,rt5616-codec";
simple-audio-card,routing =
"Headphones", "HPOL",
"Headphones", "HPOR",
"MIC1", "Microphone Jack",
"Microphone Jack", "micbias1";
simple-audio-card,widgets =
"Headphone", "Headphones",
"Microphone", "Microphone Jack";
simple-audio-card,cpu {
sound-dai = <&i2s0_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rt5616>;
};
};
buzzer: pwm-beeper {
compatible = "pwm-beeper";
amp-supply = <&vcc_5v0_sys>;
beeper-hz = <500>;
pwms = <&pwm8 0 500000 0>;
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
cooling-levels = <0 50 80 120 160 220>;
fan-supply = <&vcc_5v0_sys>;
pwms = <&pwm1 0 50000 0>;
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key1_pin>;
button-user {
debounce-interval = <50>;
gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
label = "User Button";
linux,code = <BTN_1>;
wakeup-source;
};
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc_12v_dcin: regulator-vcc-12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc_12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc_3v3_m2_a: regulator-vcc-3v3-m2-a {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_m2_a";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_12v_dcin>;
};
vcc_3v3_m2_b: regulator-vcc-3v3-m2-b {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_m2_b";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_12v_dcin>;
};
vcc_3v3_m2_c: regulator-vcc-3v3-m2-c {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_m2_c";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_12v_dcin>;
};
vcc_3v3_m2_d: regulator-vcc-3v3-m2-d {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_m2_d";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_12v_dcin>;
};
/* vcc_5v0_sys powers the peripherals */
vcc_5v0_sys: regulator-vcc-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_12v_dcin>;
};
/* SY6280AAC power switch (U14 in schematics) */
vcc_5v0_host_20: regulator-vcc-5v0-host-20 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc_5v0_host20_en>;
regulator-name = "vcc_5v0_host_20";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v0_sys>;
};
/* SY6280AAC power switch (U8 in schematics) */
vcc_5v0_host_30_p1: regulator-vcc-5v0-host-30-p1 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc_5v0_host30p1_en>;
regulator-name = "vcc_5v0_host_30_p1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v0_sys>;
};
/* SY6280AAC power switch (U9 in schematics) */
vcc_5v0_host_30_p2: regulator-vcc-5v0-host-30-p2 {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc_5v0_host30p2_en>;
regulator-name = "vcc_5v0_host_30_p2";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v0_sys>;
};
/* SY6280AAC power switch (U10 in schematics) */
vbus_5v0_typec: regulator-vbus-5v0-typec {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&typec_5v_pwr_en>;
regulator-name = "vbus_5v0_typec";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v0_sys>;
};
};
/* vcc_4v0_sys powers the RK806 and RK860's */
&vcc_4v0_sys {
vin-supply = <&vcc_12v_dcin>;
};
/* Combo PHY 1 is configured to act as as PCIe 2.0 PHY */
/* Used by PCIe controller 2 (pcie2x1l0) */
&combphy1_ps {
status = "okay";
};
/* Combo PHY 2 is configured to act as USB3 PHY */
/* Used by USB 3.0 OTG 2 controller (USB 3.0 Type-A port 2) */
/* CM3588 USB Controller Config Table: USB30 HOST2 */
&combphy2_psu {
status = "okay";
};
/* GPIO names are in the format "Human-readable-name [SIGNAL_LABEL]" */
/* Signal labels match the official CM3588 NAS SDK schematic revision 2309 */
&gpio0 {
gpio-line-names =
/* GPIO0 A0-A7 */
"", "", "", "",
"MicroSD detect [SDMMC_DET_L]", "", "", "",
/* GPIO0 B0-B7 */
"", "", "", "",
"", "", "", "",
/* GPIO0 C0-C7 */
"", "", "", "",
"Pin 10 [UART0_RX_M0]", "Pin 08 [UART0_TX_M0/PWM4_M0]", "Pin 32 [PWM5_M1]", "",
/* GPIO0 D0-D7 */
"", "", "", "USB3 Type-C [CC_INT_L]",
"IR receiver [PWM3_IR_M0]", "User Button", "", "";
};
&gpio1 {
gpio-line-names =
/* GPIO1 A0-A7 */
"Pin 27 [UART6_RX_M1]", "Pin 28 [UART6_TX_M1]", "", "",
"USB2 Type-A [USB2_PWREN]", "", "", "Pin 15",
/* GPIO1 B0-B7 */
"Pin 26", "Pin 21 [SPI0_MISO_M2]", "Pin 19 [SPI0_MOSI_M2/UART4_RX_M2]", "Pin 23 [SPI0_CLK_M2/UART4_TX_M2]",
"Pin 24 [SPI0_CS0_M2/UART7_RX_M2]", "Pin 22 [SPI0_CS1_M0/UART7_TX_M2]", "", "CSI-Pin 14 [MIPI_CAM2_CLKOUT]",
/* GPIO1 C0-C7 */
"", "", "", "",
"Headphone detect [HP_DET_L]", "", "", "",
/* GPIO1 D0-D7 */
"", "", "USB3 Type-C [TYPEC5V_PWREN_H]", "5V Fan [PWM1_M1]",
"", "HDMI-in detect [HDMIIRX_DET_L]", "Pin 05 [I2C8_SCL_M2]", "Pin 03 [I2C8_SDA_M2]";
};
&gpio2 {
gpio-line-names =
/* GPIO2 A0-A7 */
"", "", "", "",
"", "", "SPI NOR Flash [FSPI_D0_M1]", "SPI NOR Flash [FSPI_D1_M1]",
/* GPIO2 B0-B7 */
"SPI NOR Flash [FSPI_D2_M1]", "SPI NOR Flash [FSPI_D3_M1]", "", "SPI NOR Flash [FSPI_CLK_M1]",
"SPI NOR Flash [FSPI_CSN0_M1]", "", "", "",
/* GPIO2 C0-C7 */
"", "CSI-Pin 11 [MIPI_CAM2_RESET_L]", "CSI-Pin 12 [MIPI_CAM2_PDN_L]", "",
"", "", "", "",
/* GPIO2 D0-D7 */
"", "", "", "",
"", "", "", "";
};
&gpio3 {
gpio-line-names =
/* GPIO3 A0-A7 */
"Pin 35 [SPI4_MISO_M1/PWM10_M0]", "Pin 38 [SPI4_MOSI_M1]", "Pin 40 [SPI4_CLK_M1/UART8_TX_M1]", "Pin 36 [SPI4_CS0_M1/UART8_RX_M1]",
"Pin 37 [SPI4_CS1_M1]", "USB3-A #2 [USB3_2_PWREN]", "DSI-Pin 12 [LCD_RST]", "Buzzer [PWM8_M0]",
/* GPIO3 B0-B7 */
"Pin 33 [PWM9_M0]", "DSI-Pin 10 [PWM2_M1/LCD_BL]", "Pin 07", "Pin 16",
"Pin 18", "Pin 29 [UART3_TX_M1/PWM12_M0]", "Pin 31 [UART3_RX_M1/PWM13_M0]", "Pin 12",
/* GPIO3 C0-C7 */
"DSI-Pin 08 [TP_INT_L]", "DSI-Pin 14 [TP_RST_L]", "Pin 11 [PWM14_M0]", "Pin 13 [PWM15_IR_M0]",
"", "", "", "DSI-Pin 06 [I2C5_SCL_M0_TP]",
/* GPIO3 D0-D7 */
"DSI-Pin 05 [I2C5_SDA_M0_TP]", "", "", "",
"", "", "", "";
};
&gpio4 {
gpio-line-names =
/* GPIO4 A0-A7 */
"", "", "M.2 M-Key Slot4 [M2_D_PERST_L]", "",
"", "", "", "",
/* GPIO4 B0-B7 */
"USB3-A #1 [USB3_TYPEC1_PWREN]", "", "", "M.2 M-Key Slot3 [M2_C_PERST_L]",
"M.2 M-Key Slot2 [M2_B_PERST_L]", "M.2 M-Key Slot1 [M2_A_CLKREQ_L]", "M.2 M-Key Slot1 [M2_A_PERST_L]", "",
/* GPIO4 C0-C7 */
"", "", "", "",
"", "", "", "",
/* GPIO4 D0-D7 */
"", "", "", "",
"", "", "", "";
};
/* Connected to MIPI-DSI0 */
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5m0_xfer>;
status = "disabled";
};
&i2c6 {
fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus_5v0_typec>;
usb_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
power-role = "source";
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
try-power-role = "source";
vbus-supply = <&vbus_5v0_typec>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&usbdp_phy0_orientation_switch>;
};
};
port@1 {
reg = <1>;
usbc0_role_sw: endpoint {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
port@2 {
reg = <2>;
dp_altmode_mux: endpoint {
remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
};
};
};
};
};
};
/* Connected to MIPI-CSI1 */
/* &i2c7 */
/* GPIO Connector, connected to 40-pin GPIO header */
&i2c8 {
pinctrl-names = "default";
pinctrl-0 = <&i2c8m2_xfer>;
status = "okay";
};
&pcie2x1l0 {
/* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */
max-link-speed = <3>;
num-lanes = <1>;
phys = <&pcie30phy>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_0_rst>;
reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_m2_b>;
status = "okay";
};
&pcie2x1l1 {
/* 4. M.2 socket, CON16: pcie30phy port1 lane1, @fe180000 */
max-link-speed = <3>;
num-lanes = <1>;
phys = <&pcie30phy>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_1_rst>;
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_m2_d>;
status = "okay";
};
&pcie30phy {
/*
* Data lane mapping <1 3 2 4> = x1x1 x1x1 (bifurcation of both ports)
* port 0 lane 0 - always mapped to controller 0 (4L)
* port 0 lane 1 - map to controller 2 (1L0)
* port 1 lane 0 - map to controller 1 (2L)
* port 1 lane 1 - map to controller 3 (1L1)
*/
data-lanes = <1 3 2 4>;
status = "okay";
};
&pcie3x4 {
/* 1. M.2 socket, CON13: pcie30phy port0 lane0, @fe150000 */
max-link-speed = <3>;
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3x4_rst>;
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_m2_a>;
status = "okay";
};
&pcie3x2 {
/* 3. M.2 socket, CON15: pcie30phy port1 lane0, @fe160000 */
max-link-speed = <3>;
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3x2_rst>;
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_m2_c>;
status = "okay";
};
&pinctrl {
audio {
headphone_detect: headphone-detect {
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio-key {
key1_pin: key1-pin {
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pcie {
pcie2_0_rst: pcie2-0-rst {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie2_1_rst: pcie2-1-rst {
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie3x2_rst: pcie3x2-rst {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie3x4_rst: pcie3x4-rst {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc_5v0_host20_en: vcc-5v0-host20-en {
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc_5v0_host30p1_en: vcc-5v0-host30p1-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc_5v0_host30p2_en: vcc-5v0-host30p2-en {
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
typec_5v_pwr_en: typec-5v-pwr-en {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
/* Connected to 5V Fan */
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm1m1_pins>;
status = "okay";
};
/* Connected to MIPI-DSI0 */
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pwm2m1_pins>;
};
/* Connected to IR Receiver */
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pwm3m0_pins>;
status = "okay";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with UART0 */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pwm4m1_pins>;
status = "disabled";
};
/* GPIO Connector, connected to 40-pin GPIO header */
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pwm5m1_pins>;
status = "okay";
};
/* Connected to Buzzer */
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pwm8m0_pins>;
status = "okay";
};
/* GPIO Connector, connected to 40-pin GPIO header */
&pwm9 {
pinctrl-names = "default";
pinctrl-0 = <&pwm9m0_pins>;
status = "okay";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with SPI4 */
&pwm10 {
pinctrl-names = "default";
pinctrl-0 = <&pwm10m0_pins>;
status = "disabled";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with UART3 */
&pwm12 {
pinctrl-names = "default";
pinctrl-0 = <&pwm12m0_pins>;
status = "disabled";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with UART3 */
&pwm13 {
pinctrl-names = "default";
pinctrl-0 = <&pwm13m0_pins>;
status = "disabled";
};
/* GPIO Connector, connected to 40-pin GPIO header */
&pwm14 {
pinctrl-names = "default";
pinctrl-0 = <&pwm14m0_pins>;
status = "okay";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Optimized for infrared applications */
&pwm15 {
pinctrl-names = "default";
pinctrl-0 = <&pwm15m0_pins>;
status = "disabled";
};
/* microSD card */
&sdmmc {
status = "okay";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with UART4, UART7 and PWM10 */
&spi0 {
num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>;
status = "disabled";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with UART8 */
&spi4 {
num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&spi4m1_cs0 &spi4m1_pins>;
status = "disabled";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with PWM4 */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
status = "disabled";
};
/* Debug UART */
&uart2 {
status = "okay";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with PWM12 and PWM13 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
status = "disabled";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with SPI0 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4m2_xfer>;
status = "disabled";
};
/* GPIO Connector, connected to 40-pin GPIO header */
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&uart6m1_xfer>;
status = "okay";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with SPI0 */
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&uart7m2_xfer>;
status = "disabled";
};
/* GPIO Connector, connected to 40-pin GPIO header */
/* Shared with SPI4 */
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8m1_xfer>;
status = "disabled";
};
/* USB2 PHY for USB Type-C port */
/* CM3588 USB Controller Config Table: USB20 OTG0 */
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
phy-supply = <&vbus_5v0_typec>;
status = "okay";
};
/* USB2 PHY for USB 3.0 Type-A port 1 */
/* CM3588 USB Controller Config Table: USB20 OTG1 */
&u2phy1 {
status = "okay";
};
&u2phy1_otg {
phy-supply = <&vcc_5v0_host_30_p1>;
status = "okay";
};
/* USB2 PHY for USB 2.0 Type-A */
/* CM3588 USB Controller Config Table: USB20 HOST0 */
&u2phy2 {
status = "okay";
};
&u2phy2_host {
phy-supply = <&vcc_5v0_host_20>;
status = "okay";
};
/* USB2 PHY for USB 3.0 Type-A port 2 */
/* CM3588 USB Controller Config Table: USB20 HOST1 */
&u2phy3 {
status = "okay";
};
&u2phy3_host {
phy-supply = <&vcc_5v0_host_30_p2>;
status = "okay";
};
/* USB 2.0 Type-A */
/* PHY: <&u2phy2_host> */
&usb_host0_ehci {
status = "okay";
};
/* USB 2.0 Type-A */
/* PHY: <&u2phy2_host> */
&usb_host0_ohci {
status = "okay";
};
/* USB Type-C */
/* PHYs: <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3> */
&usb_host0_xhci {
usb-role-switch;
status = "okay";
port {
dwc3_0_role_switch: endpoint {
remote-endpoint = <&usbc0_role_sw>;
};
};
};
/* Lower USB 3.0 Type-A (port 2) */
/* PHY: <&u2phy3_host> */
&usb_host1_ehci {
status = "okay";
};
/* Lower USB 3.0 Type-A (port 2) */
/* PHY: <&u2phy3_host> */
&usb_host1_ohci {
status = "okay";
};
/* Upper USB 3.0 Type-A (port 1) */
/* PHYs: <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3> */
&usb_host1_xhci {
dr_mode = "host";
status = "okay";
};
/* Lower USB 3.0 Type-A (port 2) */
/* PHYs: <&combphy2_psu PHY_TYPE_USB3> */
&usb_host2_xhci {
status = "okay";
};
/* USB3 PHY for USB Type-C port */
/* CM3588 USB Controller Config Table: USB30 OTG0 */
&usbdp_phy0 {
mode-switch;
orientation-switch;
sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
usbdp_phy0_dp_altmode_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&dp_altmode_mux>;
};
};
};
/* USB3 PHY for USB 3.0 Type-A port 1 */
/* CM3588 USB Controller Config Table: USB30 OTG1 */
&usbdp_phy1 {
status = "okay";
};

459
arch/arm/dts/rk3588-toybrick-x0.dts → dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi
View File

@ -1,194 +1,101 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 Thomas McKahan
* Copyright (c) 2024 Sebastian Kropatsch
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3588.dtsi"
/ {
model = "Rockchip Toybrick TB-RK3588X Board";
compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588";
model = "FriendlyElec CM3588";
compatible = "friendlyarm,cm3588", "rockchip,rk3588";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
leds {
compatible = "gpio-leds";
button-vol-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <17000>;
led_sys: led-0 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&led_sys_pin>;
};
button-vol-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <417000>;
};
button-menu {
label = "Menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <890000>;
};
button-escape {
label = "Escape";
linux,code = <KEY_ESC>;
press-threshold-microvolt = <1235000>;
led_usr: led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&led_usr_pin>;
};
};
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vcc12v_dcin>;
pwms = <&pwm2 0 25000 0>;
};
pcie20_avdd0v85: pcie20-avdd0v85-regulator {
/* vcc_4v0_sys powers the RK806 and RK860's */
vcc_4v0_sys: regulator-vcc-4v0-sys {
compatible = "regulator-fixed";
regulator-name = "pcie20_avdd0v85";
regulator-name = "vcc_4v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
vin-supply = <&vdd_0v85_s0>;
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <4000000>;
};
pcie20_avdd1v8: pcie20-avdd1v8-regulator {
vcc_3v3_pcie20: regulator-vcc-3v3-pcie20 {
compatible = "regulator-fixed";
regulator-name = "pcie20_avdd1v8";
regulator-name = "vcc_3v3_pcie20";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
pcie30_avdd0v75: pcie30-avdd0v75-regulator {
vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd0v75";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
vin-supply = <&avdd_0v75_s0>;
};
pcie30_avdd1v8: pcie30-avdd1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
pinctrl-0 = <&sd_s0_pwr>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "vcc_3v3_sd_s0";
vin-supply = <&vcc_3v3_s3>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usbdcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usbdcin>;
};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-name = "vcc-1v1-nldo-s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
vin-supply = <&vcc_4v0_sys>;
};
};
/* Combo PHY 0 is configured to act as as PCIe 2.0 PHY */
/* Used by PCIe controller 4 (pcie2x1l2) */
&combphy0_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
@ -205,18 +112,25 @@
cpu-supply = <&vdd_cpu_lit_s0>;
};
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
phy-mode = "rgmii-rxid";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
pinctrl-names = "default";
rx_delay = <0x00>;
tx_delay = <0x43>;
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&gpu {
mali-supply = <&vdd_gpu_s0>;
sram-supply = <&vdd_gpu_mem_s0>;
status = "okay";
};
@ -235,7 +149,7 @@
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
vin-supply = <&vcc_4v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@ -252,7 +166,7 @@
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
vin-supply = <&vcc_4v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@ -263,72 +177,146 @@
&i2c2 {
status = "okay";
vdd_npu_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc_4v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c6 {
clock-frequency = <200000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6m0_xfer>;
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "hym8563";
interrupt-parent = <&gpio0>;
interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
wakeup-source;
};
};
&mdio0 {
rgmii_phy: ethernet-phy@1 {
/* RTL8211F */
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
&i2c7 {
clock-frequency = <200000>;
status = "okay";
rt5616: audio-codec@1b {
compatible = "realtek,rt5616";
reg = <0x1b>;
#sound-dai-cells = <0>;
};
};
&i2s0_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s0_lrck
&i2s0_mclk
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
status = "okay";
};
&i2s5_8ch {
status = "okay";
};
&i2s6_8ch {
status = "okay";
};
&i2s7_8ch {
status = "okay";
};
&pcie2x1l2 {
/* r8125 ethernet, @fe190000 */
pinctrl-names = "default";
pinctrl-0 = <&pcie2_2_rst>;
reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
status = "okay";
};
&pinctrl {
rtl8211f {
rtl8211f_rst: rtl8211f-rst {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
gpio-leds {
led_sys_pin: led-sys-pin {
rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_usr_pin: led-usr-pin {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
hym8563_int: rtc-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
pcie {
pcie2_2_rst: pcie2-2-rst {
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm2 {
status = "okay";
sdmmc {
sd_s0_pwr: sd-s0-pwr {
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&saradc {
vref-supply = <&vcc_1v8_s0>;
vref-supply = <&avcc_1v8_s0>;
status = "okay";
};
/* eMMC */
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
no-sdio;
no-sd;
no-sdio;
non-removable;
vmmc-supply = <&vcc_3v3_s3>;
vqmmc-supply = <&vcc_1v8_s3>;
status = "okay";
};
/* microSD card */
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
no-mmc;
no-sdio;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_sd_s0>;
vqmmc-supply = <&vccio_sd_s0>;
};
&spi2 {
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
@ -337,34 +325,38 @@
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
status = "okay";
pmic@0 {
rk806_single: pmic@0 {
compatible = "rockchip,rk806";
reg = <0x0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
spi-max-frequency = <1000000>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc5v0_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc1-supply = <&vcc_4v0_sys>;
vcc2-supply = <&vcc_4v0_sys>;
vcc3-supply = <&vcc_4v0_sys>;
vcc4-supply = <&vcc_4v0_sys>;
vcc5-supply = <&vcc_4v0_sys>;
vcc6-supply = <&vcc_4v0_sys>;
vcc7-supply = <&vcc_4v0_sys>;
vcc8-supply = <&vcc_4v0_sys>;
vcc9-supply = <&vcc_4v0_sys>;
vcc10-supply = <&vcc_4v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc_4v0_sys>;
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
vcca-supply = <&vcc_4v0_sys>;
gpio-controller;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";
@ -383,12 +375,12 @@
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-name = "vdd_gpu_s0";
regulator-boot-on;
regulator-enable-ramp-delay = <400>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
@ -396,12 +388,12 @@
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
regulator-name = "vdd_cpu_lit_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -409,12 +401,12 @@
};
vdd_log_s0: dcdc-reg3 {
regulator-name = "vdd_log_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -423,13 +415,12 @@
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
regulator-name = "vdd_vdenc_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-init-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -437,12 +428,12 @@
};
vdd_ddr_s0: dcdc-reg5 {
regulator-name = "vdd_ddr_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -451,9 +442,9 @@
};
vdd2_ddr_s3: dcdc-reg6 {
regulator-name = "vdd2_ddr_s3";
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -461,11 +452,12 @@
};
vcc_2v0_pldo_s3: dcdc-reg7 {
regulator-name = "vdd_2v0_pldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -474,11 +466,11 @@
};
vcc_3v3_s3: dcdc-reg8 {
regulator-name = "vcc_3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -487,9 +479,9 @@
};
vddq_ddr_s0: dcdc-reg9 {
regulator-name = "vddq_ddr_s0";
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -497,11 +489,11 @@
};
vcc_1v8_s3: dcdc-reg10 {
regulator-name = "vcc_1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -510,11 +502,11 @@
};
avcc_1v8_s0: pldo-reg1 {
regulator-name = "avcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -522,11 +514,11 @@
};
vcc_1v8_s0: pldo-reg2 {
regulator-name = "vcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -535,11 +527,11 @@
};
avdd_1v2_s0: pldo-reg3 {
regulator-name = "avdd_1v2_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -547,11 +539,12 @@
};
vcc_3v3_s0: pldo-reg4 {
regulator-name = "vcc_3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -559,11 +552,12 @@
};
vccio_sd_s0: pldo-reg5 {
regulator-name = "vccio_sd_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -571,11 +565,11 @@
};
pldo6_s3: pldo-reg6 {
regulator-name = "pldo6_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -584,11 +578,11 @@
};
vdd_0v75_s3: nldo-reg1 {
regulator-name = "vdd_0v75_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -597,11 +591,11 @@
};
vdd_ddr_pll_s0: nldo-reg2 {
regulator-name = "vdd_ddr_pll_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -610,11 +604,11 @@
};
avdd_0v75_s0: nldo-reg3 {
regulator-name = "avdd_0v75_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <837500>;
regulator-max-microvolt = <837500>;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -622,11 +616,11 @@
};
vdd_0v85_s0: nldo-reg4 {
regulator-name = "vdd_0v85_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -634,11 +628,11 @@
};
vdd_0v75_s0: nldo-reg5 {
regulator-name = "vdd_0v75_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -648,41 +642,12 @@
};
};
&u2phy2 {
status = "okay";
};
&u2phy2_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy3 {
status = "okay";
};
&u2phy3_host {
phy-supply = <&vcc5v0_host>;
&tsadc {
status = "okay";
};
/* Debug UART */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};

1177
dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts Normal file
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File diff suppressed because it is too large Load Diff

412
dts/upstream/src/arm64/rockchip/rk3588.dtsi
View File

@ -1,413 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3588s.dtsi"
#include "rk3588-pinctrl.dtsi"
/ {
usb_host1_xhci: usb@fc400000 {
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfc400000 0x0 0x400000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
<&cru ACLK_USB3OTG1>;
clock-names = "ref_clk", "suspend_clk", "bus_clk";
dr_mode = "otg";
phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3588_PD_USB>;
resets = <&cru SRST_A_USB3OTG1>;
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
status = "disabled";
};
pcie30_phy_grf: syscon@fd5b8000 {
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
reg = <0x0 0xfd5b8000 0x0 0x10000>;
};
pipe_phy1_grf: syscon@fd5c0000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
reg = <0x0 0xfd5c0000 0x0 0x100>;
};
usbdpphy1_grf: syscon@fd5cc000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5cc000 0x0 0x4000>;
};
usb2phy1_grf: syscon@fd5d4000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d4000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy1: usb2phy@4000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x4000 0x10>;
#clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy1";
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
reset-names = "phy", "apb";
status = "disabled";
u2phy1_otg: otg-port {
#phy-cells = <0>;
status = "disabled";
};
};
};
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 22>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO0>;
resets = <&cru SRST_M_I2S8_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s6_8ch: i2s@fddf4000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddf4000 0x0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 4>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S6_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s7_8ch: i2s@fddf8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddf8000 0x0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 21>;
dma-names = "rx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S7_8CH_RX>;
reset-names = "rx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s10_8ch: i2s@fde00000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfde00000 0x0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 24>;
dma-names = "rx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S10_8CH_RX>;
reset-names = "rx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
pcie3x4: pcie@fe150000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0x0f>;
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
<0 0 0 2 &pcie3x4_intc 1>,
<0 0 0 3 &pcie3x4_intc 2>,
<0 0 0 4 &pcie3x4_intc 3>;
linux,pci-domain = <0>;
max-link-speed = <3>;
msi-map = <0x0000 &its1 0x0000 0x1000>;
num-lanes = <4>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
reg = <0xa 0x40000000 0x0 0x00400000>,
<0x0 0xfe150000 0x0 0x00010000>,
<0x0 0xf0000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
reset-names = "pwr", "pipe";
status = "disabled";
pcie3x4_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
};
};
pcie3x2: pcie@fe160000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
<0 0 0 2 &pcie3x2_intc 1>,
<0 0 0 3 &pcie3x2_intc 2>,
<0 0 0 4 &pcie3x2_intc 3>;
linux,pci-domain = <1>;
max-link-speed = <3>;
msi-map = <0x1000 &its1 0x1000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
<0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
reg = <0xa 0x40400000 0x0 0x00400000>,
<0x0 0xfe160000 0x0 0x00010000>,
<0x0 0xf1000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
reset-names = "pwr", "pipe";
status = "disabled";
pcie3x2_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
};
};
pcie2x1l0: pcie@fe170000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
<0 0 0 2 &pcie2x1l0_intc 1>,
<0 0 0 3 &pcie2x1l0_intc 2>,
<0 0 0 4 &pcie2x1l0_intc 3>;
linux,pci-domain = <2>;
max-link-speed = <2>;
msi-map = <0x2000 &its0 0x2000 0x1000>;
num-lanes = <1>;
phys = <&combphy1_ps PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
reg = <0xa 0x40800000 0x0 0x00400000>,
<0x0 0xfe170000 0x0 0x00010000>,
<0x0 0xf2000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
reset-names = "pwr", "pipe";
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie2x1l0_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
};
};
gmac0: ethernet@fe1b0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1b0000 0x0 0x10000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
<&cru CLK_GMAC0_PTP_REF>;
clock-names = "stmmaceth", "clk_mac_ref",
"pclk_mac", "aclk_mac",
"ptp_ref";
power-domains = <&power RK3588_PD_GMAC>;
resets = <&cru SRST_A_GMAC0>;
reset-names = "stmmaceth";
rockchip,grf = <&sys_grf>;
rockchip,php-grf = <&php_grf>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
snps,mixed-burst;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,tso;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,wr_osr_lmt = <4>;
snps,rd_osr_lmt = <8>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <2>;
queue0 {};
queue1 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <2>;
queue0 {};
queue1 {};
};
};
sata1: sata@fe220000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
reg = <0 0xfe220000 0 0x1000>;
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
ports-implemented = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
phys = <&combphy1_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
snps,rx-ts-max = <32>;
snps,tx-ts-max = <32>;
};
};
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;
#phy-cells = <1>;
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
<&cru CLK_USBDP_PHY1_IMMORTAL>,
<&cru PCLK_USBDPPHY1>,
<&u2phy1>;
clock-names = "refclk", "immortal", "pclk", "utmi";
resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
<&cru SRST_USBDP_COMBO_PHY1_CMN>,
<&cru SRST_USBDP_COMBO_PHY1_LANE>,
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
<&cru SRST_P_USBDPPHY1>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
rockchip,u2phy-grf = <&usb2phy1_grf>;
rockchip,usb-grf = <&usb_grf>;
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
rockchip,vo-grf = <&vo0_grf>;
status = "disabled";
};
combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;
clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
<&cru PCLK_PHP_ROOT>;
clock-names = "ref", "apb", "pipe";
assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
assigned-clock-rates = <100000000>;
#phy-cells = <1>;
resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
reset-names = "phy", "apb";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
status = "disabled";
};
pcie30phy: phy@fee80000 {
compatible = "rockchip,rk3588-pcie3-phy";
reg = <0x0 0xfee80000 0x0 0x20000>;
#phy-cells = <0>;
clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
clock-names = "pclk";
resets = <&cru SRST_PCIE30_PHY>;
reset-names = "phy";
rockchip,pipe-grf = <&php_grf>;
rockchip,phy-grf = <&pcie30_phy_grf>;
status = "disabled";
};
};
#include "rk3588-extra.dtsi"

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dts/upstream/src/arm64/rockchip/rk3588j.dtsi
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@ -4,4 +4,4 @@
*
*/
#include "rk3588.dtsi"
#include "rk3588-extra.dtsi"

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dts/upstream/src/arm64/rockchip/rk3588s.dtsi
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include/configs/rock-5-itx-rk3588.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
*/
#ifndef __ROCK_5_ITX_RK3588_H
#define __ROCK_5_ITX_RK3588_H
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3588_common.h>
#endif /* __ROCK_5_ITX_RK3588_H */

389
include/dt-bindings/clock/px30-cru.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
* Author: Elaine <zhangqing@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_NPLL 4
#define APLL_BOOST_H 5
#define APLL_BOOST_L 6
#define ARMCLK 7
/* sclk gates (special clocks) */
#define USB480M 14
#define SCLK_PDM 15
#define SCLK_I2S0_TX 16
#define SCLK_I2S0_TX_OUT 17
#define SCLK_I2S0_RX 18
#define SCLK_I2S0_RX_OUT 19
#define SCLK_I2S1 20
#define SCLK_I2S1_OUT 21
#define SCLK_I2S2 22
#define SCLK_I2S2_OUT 23
#define SCLK_UART1 24
#define SCLK_UART2 25
#define SCLK_UART3 26
#define SCLK_UART4 27
#define SCLK_UART5 28
#define SCLK_I2C0 29
#define SCLK_I2C1 30
#define SCLK_I2C2 31
#define SCLK_I2C3 32
#define SCLK_I2C4 33
#define SCLK_PWM0 34
#define SCLK_PWM1 35
#define SCLK_SPI0 36
#define SCLK_SPI1 37
#define SCLK_TIMER0 38
#define SCLK_TIMER1 39
#define SCLK_TIMER2 40
#define SCLK_TIMER3 41
#define SCLK_TIMER4 42
#define SCLK_TIMER5 43
#define SCLK_TSADC 44
#define SCLK_SARADC 45
#define SCLK_OTP 46
#define SCLK_OTP_USR 47
#define SCLK_CRYPTO 48
#define SCLK_CRYPTO_APK 49
#define SCLK_DDRC 50
#define SCLK_ISP 51
#define SCLK_CIF_OUT 52
#define SCLK_RGA_CORE 53
#define SCLK_VOPB_PWM 54
#define SCLK_NANDC 55
#define SCLK_SDIO 56
#define SCLK_EMMC 57
#define SCLK_SFC 58
#define SCLK_SDMMC 59
#define SCLK_OTG_ADP 60
#define SCLK_GMAC_SRC 61
#define SCLK_GMAC 62
#define SCLK_GMAC_RX_TX 63
#define SCLK_MAC_REF 64
#define SCLK_MAC_REFOUT 65
#define SCLK_MAC_OUT 66
#define SCLK_SDMMC_DRV 67
#define SCLK_SDMMC_SAMPLE 68
#define SCLK_SDIO_DRV 69
#define SCLK_SDIO_SAMPLE 70
#define SCLK_EMMC_DRV 71
#define SCLK_EMMC_SAMPLE 72
#define SCLK_GPU 73
#define SCLK_PVTM 74
#define SCLK_CORE_VPU 75
#define SCLK_GMAC_RMII 76
#define SCLK_UART2_SRC 77
#define SCLK_NANDC_DIV 78
#define SCLK_NANDC_DIV50 79
#define SCLK_SDIO_DIV 80
#define SCLK_SDIO_DIV50 81
#define SCLK_EMMC_DIV 82
#define SCLK_EMMC_DIV50 83
/* dclk gates */
#define DCLK_VOPB 150
#define DCLK_VOPL 151
/* aclk gates */
#define ACLK_GPU 170
#define ACLK_BUS_PRE 171
#define ACLK_CRYPTO 172
#define ACLK_VI_PRE 173
#define ACLK_VO_PRE 174
#define ACLK_VPU 175
#define ACLK_PERI_PRE 176
#define ACLK_GMAC 178
#define ACLK_CIF 179
#define ACLK_ISP 180
#define ACLK_VOPB 181
#define ACLK_VOPL 182
#define ACLK_RGA 183
#define ACLK_GIC 184
#define ACLK_DCF 186
#define ACLK_DMAC 187
/* hclk gates */
#define HCLK_BUS_PRE 240
#define HCLK_CRYPTO 241
#define HCLK_VI_PRE 242
#define HCLK_VO_PRE 243
#define HCLK_VPU 244
#define HCLK_PERI_PRE 245
#define HCLK_MMC_NAND 246
#define HCLK_SDMMC 247
#define HCLK_USB 248
#define HCLK_CIF 249
#define HCLK_ISP 250
#define HCLK_VOPB 251
#define HCLK_VOPL 252
#define HCLK_RGA 253
#define HCLK_NANDC 254
#define HCLK_SDIO 255
#define HCLK_EMMC 256
#define HCLK_SFC 257
#define HCLK_OTG 258
#define HCLK_HOST 259
#define HCLK_HOST_ARB 260
#define HCLK_PDM 261
#define HCLK_I2S0 262
#define HCLK_I2S1 263
#define HCLK_I2S2 264
/* pclk gates */
#define PCLK_BUS_PRE 320
#define PCLK_DDR 321
#define PCLK_VO_PRE 322
#define PCLK_GMAC 323
#define PCLK_MIPI_DSI 324
#define PCLK_MIPIDSIPHY 325
#define PCLK_MIPICSIPHY 326
#define PCLK_USB_GRF 327
#define PCLK_DCF 328
#define PCLK_UART1 329
#define PCLK_UART2 330
#define PCLK_UART3 331
#define PCLK_UART4 332
#define PCLK_UART5 333
#define PCLK_I2C0 334
#define PCLK_I2C1 335
#define PCLK_I2C2 336
#define PCLK_I2C3 337
#define PCLK_I2C4 338
#define PCLK_PWM0 339
#define PCLK_PWM1 340
#define PCLK_SPI0 341
#define PCLK_SPI1 342
#define PCLK_SARADC 343
#define PCLK_TSADC 344
#define PCLK_TIMER 345
#define PCLK_OTP_NS 346
#define PCLK_WDT_NS 347
#define PCLK_GPIO1 348
#define PCLK_GPIO2 349
#define PCLK_GPIO3 350
#define PCLK_ISP 351
#define PCLK_CIF 352
#define PCLK_OTP_PHY 353
#define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
/* pmu-clocks indices */
#define PLL_GPLL 1
#define SCLK_RTC32K_PMU 4
#define SCLK_WIFI_PMU 5
#define SCLK_UART0_PMU 6
#define SCLK_PVTM_PMU 7
#define PCLK_PMU_PRE 8
#define SCLK_REF24M_PMU 9
#define SCLK_USBPHY_REF 10
#define SCLK_MIPIDSIPHY_REF 11
#define XIN24M_DIV 12
#define PCLK_GPIO0_PMU 20
#define PCLK_UART0_PMU 21
#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)
/* soft-reset indices */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1
#define SRST_CORE2_PO 2
#define SRST_CORE3_PO 3
#define SRST_CORE0 4
#define SRST_CORE1 5
#define SRST_CORE2 6
#define SRST_CORE3 7
#define SRST_CORE0_DBG 8
#define SRST_CORE1_DBG 9
#define SRST_CORE2_DBG 10
#define SRST_CORE3_DBG 11
#define SRST_TOPDBG 12
#define SRST_CORE_NOC 13
#define SRST_STRC_A 14
#define SRST_L2C 15
#define SRST_DAP 16
#define SRST_CORE_PVTM 17
#define SRST_GPU 18
#define SRST_GPU_NIU 19
#define SRST_UPCTL2 20
#define SRST_UPCTL2_A 21
#define SRST_UPCTL2_P 22
#define SRST_MSCH 23
#define SRST_MSCH_P 24
#define SRST_DDRMON_P 25
#define SRST_DDRSTDBY_P 26
#define SRST_DDRSTDBY 27
#define SRST_DDRGRF_p 28
#define SRST_AXI_SPLIT_A 29
#define SRST_AXI_CMD_A 30
#define SRST_AXI_CMD_P 31
#define SRST_DDRPHY 32
#define SRST_DDRPHYDIV 33
#define SRST_DDRPHY_P 34
#define SRST_VPU_A 36
#define SRST_VPU_NIU_A 37
#define SRST_VPU_H 38
#define SRST_VPU_NIU_H 39
#define SRST_VI_NIU_A 40
#define SRST_VI_NIU_H 41
#define SRST_ISP_H 42
#define SRST_ISP 43
#define SRST_CIF_A 44
#define SRST_CIF_H 45
#define SRST_CIF_PCLKIN 46
#define SRST_MIPICSIPHY_P 47
#define SRST_VO_NIU_A 48
#define SRST_VO_NIU_H 49
#define SRST_VO_NIU_P 50
#define SRST_VOPB_A 51
#define SRST_VOPB_H 52
#define SRST_VOPB 53
#define SRST_PWM_VOPB 54
#define SRST_VOPL_A 55
#define SRST_VOPL_H 56
#define SRST_VOPL 57
#define SRST_RGA_A 58
#define SRST_RGA_H 59
#define SRST_RGA 60
#define SRST_MIPIDSI_HOST_P 61
#define SRST_MIPIDSIPHY_P 62
#define SRST_VPU_CORE 63
#define SRST_PERI_NIU_A 64
#define SRST_USB_NIU_H 65
#define SRST_USB2OTG_H 66
#define SRST_USB2OTG 67
#define SRST_USB2OTG_ADP 68
#define SRST_USB2HOST_H 69
#define SRST_USB2HOST_ARB_H 70
#define SRST_USB2HOST_AUX_H 71
#define SRST_USB2HOST_EHCI 72
#define SRST_USB2HOST 73
#define SRST_USBPHYPOR 74
#define SRST_USBPHY_OTG_PORT 75
#define SRST_USBPHY_HOST_PORT 76
#define SRST_USBPHY_GRF 77
#define SRST_CPU_BOOST_P 78
#define SRST_CPU_BOOST 79
#define SRST_MMC_NAND_NIU_H 80
#define SRST_SDIO_H 81
#define SRST_EMMC_H 82
#define SRST_SFC_H 83
#define SRST_SFC 84
#define SRST_SDCARD_NIU_H 85
#define SRST_SDMMC_H 86
#define SRST_NANDC_H 89
#define SRST_NANDC 90
#define SRST_GMAC_NIU_A 92
#define SRST_GMAC_NIU_P 93
#define SRST_GMAC_A 94
#define SRST_PMU_NIU_P 96
#define SRST_PMU_SGRF_P 97
#define SRST_PMU_GRF_P 98
#define SRST_PMU 99
#define SRST_PMU_MEM_P 100
#define SRST_PMU_GPIO0_P 101
#define SRST_PMU_UART0_P 102
#define SRST_PMU_CRU_P 103
#define SRST_PMU_PVTM 104
#define SRST_PMU_UART 105
#define SRST_PMU_NIU_H 106
#define SRST_PMU_DDR_FAIL_SAVE 107
#define SRST_PMU_CORE_PERF_A 108
#define SRST_PMU_CORE_GRF_P 109
#define SRST_PMU_GPU_PERF_A 110
#define SRST_PMU_GPU_GRF_P 111
#define SRST_CRYPTO_NIU_A 112
#define SRST_CRYPTO_NIU_H 113
#define SRST_CRYPTO_A 114
#define SRST_CRYPTO_H 115
#define SRST_CRYPTO 116
#define SRST_CRYPTO_APK 117
#define SRST_BUS_NIU_H 120
#define SRST_USB_NIU_P 121
#define SRST_BUS_TOP_NIU_P 122
#define SRST_INTMEM_A 123
#define SRST_GIC_A 124
#define SRST_ROM_H 126
#define SRST_DCF_A 127
#define SRST_DCF_P 128
#define SRST_PDM_H 129
#define SRST_PDM 130
#define SRST_I2S0_H 131
#define SRST_I2S0_TX 132
#define SRST_I2S1_H 133
#define SRST_I2S1 134
#define SRST_I2S2_H 135
#define SRST_I2S2 136
#define SRST_UART1_P 137
#define SRST_UART1 138
#define SRST_UART2_P 139
#define SRST_UART2 140
#define SRST_UART3_P 141
#define SRST_UART3 142
#define SRST_UART4_P 143
#define SRST_UART4 144
#define SRST_UART5_P 145
#define SRST_UART5 146
#define SRST_I2C0_P 147
#define SRST_I2C0 148
#define SRST_I2C1_P 149
#define SRST_I2C1 150
#define SRST_I2C2_P 151
#define SRST_I2C2 152
#define SRST_I2C3_P 153
#define SRST_I2C3 154
#define SRST_PWM0_P 157
#define SRST_PWM0 158
#define SRST_PWM1_P 159
#define SRST_PWM1 160
#define SRST_SPI0_P 161
#define SRST_SPI0 162
#define SRST_SPI1_P 163
#define SRST_SPI1 164
#define SRST_SARADC_P 165
#define SRST_SARADC 166
#define SRST_TSADC_P 167
#define SRST_TSADC 168
#define SRST_TIMER_P 169
#define SRST_TIMER0 170
#define SRST_TIMER1 171
#define SRST_TIMER2 172
#define SRST_TIMER3 173
#define SRST_TIMER4 174
#define SRST_TIMER5 175
#define SRST_OTP_NS_P 176
#define SRST_OTP_NS_SBPI 177
#define SRST_OTP_NS_USR 178
#define SRST_OTP_PHY_P 179
#define SRST_OTP_PHY 180
#define SRST_WDT_NS_P 181
#define SRST_GPIO1_P 182
#define SRST_GPIO2_P 183
#define SRST_GPIO3_P 184
#define SRST_SGRF_P 185
#define SRST_GRF_P 186
#define SRST_I2S0_RX 191
#endif

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include/dt-bindings/clock/rockchip,rk808.h
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/*
* This header provides constants clk index RK808 pmic clkout
*/
#ifndef _CLK_ROCKCHIP_RK808
#define _CLK_ROCKCHIP_RK808
/* CLOCKOUT index */
#define RK808_CLKOUT0 0
#define RK808_CLKOUT1 1
#endif

27
include/dt-bindings/power/px30-power.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__
#define __DT_BINDINGS_POWER_PX30_POWER_H__
/* VD_CORE */
#define PX30_PD_A35_0 0
#define PX30_PD_A35_1 1
#define PX30_PD_A35_2 2
#define PX30_PD_A35_3 3
#define PX30_PD_SCU 4
/* VD_LOGIC */
#define PX30_PD_USB 5
#define PX30_PD_DDR 6
#define PX30_PD_SDCARD 7
#define PX30_PD_CRYPTO 8
#define PX30_PD_GMAC 9
#define PX30_PD_MMC_NAND 10
#define PX30_PD_VPU 11
#define PX30_PD_VO 12
#define PX30_PD_VI 13
#define PX30_PD_GPU 14
/* VD_PMU */
#define PX30_PD_PMU 15
#endif

16
include/dt-bindings/soc/rockchip,boot-mode.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ROCKCHIP_BOOT_MODE_H
#define __ROCKCHIP_BOOT_MODE_H
/*high 24 bits is tag, low 8 bits is type*/
#define REBOOT_FLAG 0x5242C300
/* normal boot */
#define BOOT_NORMAL (REBOOT_FLAG + 0)
/* enter bootloader rockusb mode */
#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1)
/* enter recovery */
#define BOOT_RECOVERY (REBOOT_FLAG + 3)
/* enter fastboot mode */
#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
#endif

18
include/dt-bindings/soc/rockchip,vop2.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
#define __DT_BINDINGS_ROCKCHIP_VOP2_H
#define ROCKCHIP_VOP2_EP_RGB0 1
#define ROCKCHIP_VOP2_EP_HDMI0 2
#define ROCKCHIP_VOP2_EP_EDP0 3
#define ROCKCHIP_VOP2_EP_MIPI0 4
#define ROCKCHIP_VOP2_EP_LVDS0 5
#define ROCKCHIP_VOP2_EP_MIPI1 6
#define ROCKCHIP_VOP2_EP_LVDS1 7
#define ROCKCHIP_VOP2_EP_HDMI1 8
#define ROCKCHIP_VOP2_EP_EDP1 9
#define ROCKCHIP_VOP2_EP_DP0 10
#define ROCKCHIP_VOP2_EP_DP1 11
#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */