From 09e4ce4e25adbc3886e10b5a582bfc9f3945bab1 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 7 Aug 2021 13:48:44 -0500 Subject: [PATCH] sunxi: Add a U-Boot port for the Allwinner D1 Nezha Signed-off-by: Samuel Holland --- Kconfig | 2 + arch/arm/mach-sunxi/Kconfig | 2 - arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + .../dts/sun20i-d1-common-regulators.dtsi | 65 + arch/riscv/dts/sun20i-d1-nezha.dts | 341 ++++ arch/riscv/dts/sun20i-d1.dtsi | 1437 +++++++++++++++++ arch/riscv/dts/sunxi-u-boot.dtsi | 3 + board/sunxi/Kconfig | 88 + board/sunxi/Makefile | 3 +- board/sunxi/board-riscv.c | 23 + common/spl/Kconfig | 4 +- configs/nezha_defconfig | 31 + drivers/clk/Makefile | 2 +- drivers/clk/sunxi/Kconfig | 3 +- drivers/net/phy/Kconfig | 4 +- drivers/phy/allwinner/Kconfig | 2 +- drivers/reset/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/usb/gadget/Kconfig | 6 +- drivers/usb/musb-new/Kconfig | 2 +- drivers/watchdog/Kconfig | 4 +- include/configs/sun20i.h | 68 + include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 + include/dt-bindings/clock/sun6i-rtc.h | 10 + .../dt-bindings/mailbox/sun20i-d1-msgbox.h | 15 + include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 + scripts/Makefile.spl | 4 + 28 files changed, 2145 insertions(+), 18 deletions(-) create mode 100644 arch/riscv/dts/sun20i-d1-common-regulators.dtsi create mode 100644 arch/riscv/dts/sun20i-d1-nezha.dts create mode 100644 arch/riscv/dts/sun20i-d1.dtsi create mode 100644 arch/riscv/dts/sunxi-u-boot.dtsi create mode 100644 board/sunxi/board-riscv.c create mode 100644 configs/nezha_defconfig create mode 100644 include/configs/sun20i.h create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h create mode 100644 include/dt-bindings/clock/sun6i-rtc.h create mode 100644 include/dt-bindings/mailbox/sun20i-d1-msgbox.h create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h diff --git a/Kconfig b/Kconfig index 6194dcb472b..e2c49a6d317 100644 --- a/Kconfig +++ b/Kconfig @@ -12,6 +12,8 @@ source "scripts/Kconfig.include" # Allow defaults in arch-specific code to override any given here source "arch/Kconfig" +source "board/sunxi/Kconfig" + menu "General setup" config BROKEN diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index e3afed49970..43be3baf346 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -986,8 +986,6 @@ config BLUETOOTH_DT_DEVICE_FIXUP The used address is "bdaddr" if set, and "ethaddr" with the LSB flipped elsewise. -source "board/sunxi/Kconfig" - endif config CHIP_DIP_SCAN diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 38c57982196..bff5f7c904d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -31,6 +31,10 @@ config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 +config TARGET_SUNXI + bool "Support Allwinner sunxi SoCs with RISC-V cores" + select SYS_CACHE_SHIFT_6 + endchoice config SYS_ICACHE_OFF diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 5c15a0f303a..524ce14169c 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb +dtb-$(CONFIG_TARGET_SUNXI) += sun20i-d1-nezha.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/riscv/dts/sun20i-d1-common-regulators.dtsi b/arch/riscv/dts/sun20i-d1-common-regulators.dtsi new file mode 100644 index 00000000000..a353d9888cc --- /dev/null +++ b/arch/riscv/dts/sun20i-d1-common-regulators.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +/ { + reg_vcc: vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc>; + }; +}; + +&codec { + avcc-supply = <®_aldo>; + hpvcc-supply = <®_hpldo>; + vdd33-supply = <®_vcc_3v3>; +}; + +&gpio { + vcc-pb-supply = <®_vcc_3v3>; + vcc-pc-supply = <®_vcc_3v3>; + vcc-pd-supply = <®_vcc_3v3>; + vcc-pe-supply = <®_vcc_3v3>; + vcc-pf-supply = <®_vcc_3v3>; + vcc-pg-supply = <®_vcc_3v3>; +}; + +&hdmi { + hvcc-supply = <®_ldoa>; +}; + +&lradc { + vref-supply = <®_aldo>; +}; + +®_aldo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vdd33-supply = <®_vcc_3v3>; +}; + +®_hpldo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + hpldoin-supply = <®_vcc_3v3>; +}; + +®_ldoa { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + ldo-in-supply = <®_vcc_3v3>; +}; + +&ths { + vref-supply = <®_aldo>; +}; diff --git a/arch/riscv/dts/sun20i-d1-nezha.dts b/arch/riscv/dts/sun20i-d1-nezha.dts new file mode 100644 index 00000000000..ce579430e13 --- /dev/null +++ b/arch/riscv/dts/sun20i-d1-nezha.dts @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +/dts-v1/; + +#include +#include +#include +#include + +#include "sun20i-d1.dtsi" +#include "sun20i-d1-common-regulators.dtsi" + +/ { + model = "Allwinner D1 Nezha"; + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1"; + + aliases { + ethernet0 = &emac; + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &mmc2; + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi_connector: connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_usbvbus: usbvbus { + compatible = "regulator-fixed"; + regulator-name = "usbvbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + enable-active-high; + vin-supply = <®_vcc>; + }; + + reg_vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm 0 50000 0>; + pwm-supply = <®_vcc>; + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1160000>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&codec { + allwinner,routing = "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "LINEINL", "HPOUTL", + "LINEINR", "HPOUTR", + "MICIN3", "Headset Microphone", + "Headset Microphone", "HBIAS"; + allwinner,widgets = "Microphone", "Headset Microphone", + "Headphone", "Headphone Jack"; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpu>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-0 = <&rgmii_pe_pins>; + pinctrl-names = "default"; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <®_vcc_3v3>; + status = "okay"; +}; + +&gpio { + i2s2_pb_pins: i2s2-pb-pins { + pins = "PB5", "PB6", "PB7"; + function = "i2s2"; + }; + + i2s2_pb3_din_pin: i2s2-pb3-din-pin { + pins = "PB3"; + function = "i2s2_din"; + }; + + i2s2_pb4_dout_pin: i2s2-pb4-dout-pin { + pins = "PB4"; + function = "i2s2_dout"; + }; + + ledc_pc0_pin: ledc-pc0-pin { + pins = "PC0"; + function = "ledc"; + }; + + pwm0_pd16_pin: pwm0-pd16-pin { + pins = "PD16"; + function = "pwm"; + }; + + pwm2_pd18_pin: pwm2-pd18-pin { + pins = "PD18"; + function = "pwm"; + }; + + pwm7_pd22_pin: pwm7-pd22-pin { + pins = "PD22"; + function = "pwm"; + }; + + spdif_pd22_pin: spdif-pd22-pin { + pins = "PD22"; + function = "spdif"; + }; +}; + +&hdmi { + status = "okay"; + + port { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; +}; + +&hdmi_phy { + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pb10_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pb0_pins>; + pinctrl-names = "default"; + status = "okay"; + + pcf8574a: gpio@38 { + compatible = "nxp,pcf8574a"; + #address-cells = <0>; + reg = <0x38>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = <&gpio 1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2s2 { + pinctrl-0 = <&i2s2_pb_pins>, <&i2s2_pb3_din_pin>, <&i2s2_pb4_dout_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ledc { + pinctrl-0 = <&ledc_pc0_pin>; + pinctrl-names = "default"; + status = "okay"; + + led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; +}; + +&lradc { + wakeup-source; + status = "okay"; + + button-160 { + label = "OK"; + linux,code = ; + channel = <0>; + voltage = <160000>; + }; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&gpio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + disable-wp; + vmmc-supply = <®_vcc_3v3>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + vmmc-supply = <®_vcc_3v3>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + status = "okay"; + + xr829: wifi@1 { + reg = <1>; + host-wake-gpios = <&gpio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pwm { + pinctrl-0 = <&pwm0_pd16_pin>, <&pwm2_pd18_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spdif { + pinctrl-0 = <&spdif_pd22_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot0"; + reg = <0x00000000 0x00100000>; + }; + + partition@100000 { + label = "uboot"; + reg = <0x00100000 0x00300000>; + }; + + partition@400000 { + label = "secure_storage"; + reg = <0x00400000 0x00100000>; + }; + + partition@500000 { + label = "sys"; + reg = <0x00500000 0x0fb00000>; + }; + }; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pd_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb8_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "xradio,xr829-bt"; + device-wakeup-gpios = <&gpio 6 16 GPIO_ACTIVE_LOW>; /* PG16 */ + interrupts-extended = <&gpio 6 17 IRQ_TYPE_LEVEL_LOW>; /* PG17 */ + interrupt-names = "wakeup"; + reset-gpios = <&gpio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&gpio 3 21 GPIO_ACTIVE_LOW>; /* PD21 */ + usb0_vbus_det-gpios = <&gpio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + usb0_vbus-supply = <®_usbvbus>; + usb1_vbus-supply = <®_vcc>; + status = "okay"; +}; diff --git a/arch/riscv/dts/sun20i-d1.dtsi b/arch/riscv/dts/sun20i-d1.dtsi new file mode 100644 index 00000000000..f00125ebefb --- /dev/null +++ b/arch/riscv/dts/sun20i-d1.dtsi @@ -0,0 +1,1437 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021 Samuel Holland + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + // FIXME: no riscv architecture support for cpufreq + cpu_opp_table: cpu-opp-table { + compatible = "allwinner,sun20i-d1-operating-points", + "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + + opp-1080000000 { + // FIXME: this is probably wrong now. + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1008000000>; + + // FIXME: derive a real voltage range. + opp-microvolt-speed0 = <1100000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + cpu0: cpu@0 { + // FIXME: is this the right compatible? + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_RISCV>; + clock-frequency = <24000000>; + #cooling-cells = <2>; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + operating-points-v2 = <&cpu_opp_table>; + riscv,isa = "rv64imafdc"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #address-cells = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + de: display-engine { + compatible = "allwinner,sun20i-d1-display-engine"; + // interrupts = <103 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mbus 11>; + interconnect-names = "dma-mem"; + allwinner,pipelines = <&mixer0>, <&mixer1>; + status = "disabled"; + }; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + // FIXME: depends on what T-HEAD tries to upstream. + pmu { + compatible = "thead,c900-pmu"; + }; + + thermal-zones { + cpu-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&ths 0>; + + trips { + cpu_target: cpu-target { + hysteresis = <3000>; + temperature = <85000>; + type = "passive"; + }; + + cpu-crit { + hysteresis = <0>; + temperature = <110000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + // TODO: write a binding and driver. + dsp: dsp@1700000 { + compatible = "allwinner,sun20i-d1-dsp"; + reg = <0x1700000 0x400>; + reg-names = "cfg"; + clocks = <&ccu CLK_BUS_DSP_CFG>, + <&ccu CLK_DSP>; + clock-names = "cfg", "dsp"; + resets = <&ccu RST_BUS_DSP_CFG>, + <&ccu RST_BUS_DSP_DBG>, + <&ccu RST_DSP>; + allwinner,sram = <&dsp_sram 1>; + interrupts = <136 IRQ_TYPE_LEVEL_HIGH>, + <137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dee", "pfe"; + // FIXME: this will be different for R528 (CPUX). + mboxes = <&riscv_msgbox MBOX_USER_DSP MBOX_RX>, + <&dsp_msgbox MBOX_USER_RISCV MBOX_TX>; + mbox-names = "rx", "tx"; + }; + + dsp_wdt: watchdog@1700400 { + compatible = "allwinner,sun20i-d1-wdt"; + reg = <0x1700400 0x20>; + clocks = <&osc24M>; + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>; + status = "reserved"; + }; + + // TODO: write a binding and driver. + dsp_msgbox: mailbox@1701000 { + compatible = "allwinner,sun20i-d1-msgbox"; + reg = <0x1701000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX1>; + resets = <&ccu RST_BUS_MSGBOX1>; + interrupts = <139 IRQ_TYPE_LEVEL_HIGH>, + <140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + #mbox-cells = <2>; + }; + + ve: video-codec@1c0e000 { + compatible = "allwinner,sun20i-d1-video-engine"; + reg = <0x1c0e000 0x2000>; + clocks = <&ccu CLK_BUS_VE>, + <&ccu CLK_VE>, + <&ccu CLK_MBUS_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + allwinner,sram = <&ve_sram 1>; + interconnects = <&mbus 4>; + interconnect-names = "dma-mem"; + interrupts = <82 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&iommu 0>; + }; + + gpio: pinctrl@2000000 { + compatible = "allwinner,sun20i-d1-pinctrl"; + #address-cells = <0>; + reg = <0x2000000 0x800>; + clocks = <&ccu CLK_APB0>, + <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>, + <87 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <91 IRQ_TYPE_LEVEL_HIGH>, + <93 IRQ_TYPE_LEVEL_HIGH>, + <95 IRQ_TYPE_LEVEL_HIGH>; + // FIXME: not in binding, should we add these? + interrupt-names = "pb", "pc", "pd", "pe", "pf", "pg"; + interrupt-controller; + #interrupt-cells = <3>; + + /omit-if-no-ref/ + i2c0_pb10_pins: i2c0-pb10-pins { + pins = "PB10", "PB11"; + function = "i2c0"; + }; + + /omit-if-no-ref/ + i2c2_pb0_pins: i2c2-pb0-pins { + pins = "PB0", "PB1"; + function = "i2c2"; + }; + + /omit-if-no-ref/ + i2c3_pb6_pins: i2c3-pb6-pins { + pins = "PB6", "PB7"; + function = "i2c3"; + }; + + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", + "PD18", "PD19", "PD20", "PD21"; + function = "lcd0"; + }; + + /omit-if-no-ref/ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; + function = "mmc1"; + }; + + /omit-if-no-ref/ + mmc2_pins: mmc2-pins { + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; + function = "mmc2"; + }; + + /omit-if-no-ref/ + rgmii_pe_pins: rgmii-pe-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE11", "PE12", "PE13", "PE14", "PE15"; + function = "emac"; + }; + + /omit-if-no-ref/ + rmii_pe_pins: rmii-pe-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9"; + function = "emac"; + }; + + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pb_pins: spi1-pb-pins { + pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_pd_pins: spi1-pd-pins { + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15"; + function = "spi1"; + }; + + /omit-if-no-ref/ + uart0_pb8_pins: uart0-pb8-pins { + pins = "PB8", "PB9"; + function = "uart0"; + }; + + /omit-if-no-ref/ + uart1_pg6_pins: uart1-pg6-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; + }; + + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x2000c00 0x400>; + clocks = <&ccu CLK_BUS_PWM>, <&osc24M>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_PWM>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ccu: clock-controller@2001000 { + compatible = "allwinner,sun20i-d1-ccu"; + reg = <0x2001000 0x1000>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + // TODO: write a binding and driver. + ir_tx: irled@2003000 { + compatible = "allwinner,sun20i-d1-ir-tx"; + reg = <0x2003000 0x400>; + clocks = <&ccu CLK_BUS_IR_TX>, + <&osc24M>, + <&ccu CLK_IR_TX>; + clock-names = "bus", "pclk", "mclk"; + resets = <&ccu RST_BUS_IR_TX>; + dmas = <&dma 13>; + dma-names = "tx"; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ledc: led-controller@2008000 { + compatible = "allwinner,sun20i-d1-ledc", + "allwinner,sun50i-r329-ledc"; + reg = <0x2008000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_LEDC>; + dmas = <&dma 42>; + dma-names = "tx"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a binding and driver. + gpadc: adc@2009000 { + compatible = "allwinner,sun20i-d1-gpadc"; + reg = <0x2009000 0x400>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + dmas = <&dma 12>; + dma-names = "rx"; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ths: temperature-sensor@2009400 { + compatible = "allwinner,sun20i-d1-ths"; + reg = <0x2009400 0x400>; + clocks = <&ccu CLK_BUS_THS>, <&osc24M>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_THS>; + interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; + nvmem-cells = <&ths_calib>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + + lradc: keys@2009800 { + compatible = "allwinner,sun20i-d1-lradc", + "allwinner,sun50i-r329-lradc"; + reg = <0x2009800 0x400>; + clocks = <&ccu CLK_BUS_LRADC>; + resets = <&ccu RST_BUS_LRADC>; + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a binding and driver. + tpadc: touchscreen@2009c00 { + compatible = "allwinner,sun20i-d1-ts"; + reg = <0x2009c00 0x400>; + clocks = <&ccu CLK_BUS_TPADC>, <&ccu CLK_TPADC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_TPADC>; + dmas = <&dma 13>; + dma-names = "rx"; + interrupts = <78 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // FIXME: this driver probably needs updates. + iommu: iommu@2010000 { + compatible = "allwinner,sun20i-d1-iommu"; + reg = <0x2010000 0x10000>; + clocks = <&ccu CLK_BUS_IOMMU>; + interrupts = <80 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + codec: audio-codec@2030000 { + compatible = "allwinner,sun20i-d1-audio-codec"; + reg = <0x2030000 0x1000>; + clocks = <&ccu CLK_BUS_AUDIO>, + <&ccu CLK_AUDIO_ADC>, + <&ccu CLK_AUDIO_DAC>, + <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "bus", "adc", "dac", "hosc", "losc"; + resets = <&ccu RST_BUS_AUDIO>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + + regulators { + reg_aldo: aldo { + regulator-name = "aldo"; + }; + + reg_hpldo: hpldo { + regulator-name = "hpldo"; + }; + }; + + }; + + // TODO: try the posted driver. + dmic: dmic@2031000 { + compatible = "allwinner,sun20i-d1-dmic"; + reg = <0x2031000 0x400>; + clocks = <&ccu CLK_BUS_DMIC>, + <&ccu CLK_DMIC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_DMIC>; + dmas = <&dma 8>; + dma-names = "rx"; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s0: i2s@2032000 { + compatible = "allwinner,sun20i-d1-i2s"; + reg = <0x2032000 0x1000>; + clocks = <&ccu CLK_BUS_I2S0>, + <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S0>; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1: i2s@2033000 { + compatible = "allwinner,sun20i-d1-i2s"; + reg = <0x2033000 0x1000>; + clocks = <&ccu CLK_BUS_I2S1>, + <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S1>; + dmas = <&dma 4>, <&dma 4>; + dma-names = "rx", "tx"; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + // TODO: how to integrate ASRC? same or separate node? + i2s2: i2s@2034000 { + compatible = "allwinner,sun20i-d1-i2s"; + reg = <0x2034000 0x1000>; + clocks = <&ccu CLK_BUS_I2S2>, + <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S2>; + dmas = <&dma 5>, <&dma 5>; + dma-names = "rx", "tx"; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + // TODO: add receive functionality + spdif: spdif@2036000 { + compatible = "allwinner,sun20i-d1-spdif"; + reg = <0x2036000 0x400>; + clocks = <&ccu CLK_BUS_SPDIF>, + <&ccu CLK_SPDIF_RX>, + <&ccu CLK_SPDIF_TX>; + clock-names = "apb", "rx", "tx"; + resets = <&ccu RST_BUS_SPDIF>; + dmas = <&dma 2>, <&dma 2>; + dma-names = "rx", "tx"; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + timer: timer@2050000 { + compatible = "allwinner,sun20i-d1-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x2050000 0xa0>; + clocks = <&osc24M>; + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>, + <76 IRQ_TYPE_LEVEL_HIGH>; + }; + + wdt: watchdog@20500a0 { + compatible = "allwinner,sun20i-d1-wdt-reset", + "allwinner,sun20i-d1-wdt"; + reg = <0x20500a0 0x20>; + clocks = <&osc24M>; + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; + status = "reserved"; + }; + + // TODO: write a driver. + uart0: serial@2500000 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2500000 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 14>, <&dma 14>; + dma-names = "rx", "tx"; + fifo-size = <64>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver, add IDMA? + uart1: serial@2500400 { + compatible = "allwinner,sun20i-d1-uart1", + "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2500400 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver. + uart2: serial@2500800 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2500800 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 16>, <&dma 16>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver. + uart3: serial@2500c00 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2500c00 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 17>, <&dma 17>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver. + uart4: serial@2501000 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2501000 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + dmas = <&dma 18>, <&dma 18>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver. + uart5: serial@2501400 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2501400 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + dmas = <&dma 19>, <&dma 19>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c0: i2c@2502000 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + dmas = <&dma 43>, <&dma 43>; + dma-names = "rx", "tx"; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@2502400 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + dmas = <&dma 44>, <&dma 44>; + dma-names = "rx", "tx"; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c2: i2c@2502800 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + dmas = <&dma 45>, <&dma 45>; + dma-names = "rx", "tx"; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c3: i2c@2502c00 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + dmas = <&dma 46>, <&dma 46>; + dma-names = "rx", "tx"; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + syscon: syscon@3000000 { + compatible = "allwinner,sun20i-d1-system-control"; + reg = <0x3000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + regulators { + reg_ldoa: ldoa { + regulator-name = "ldoa"; + }; + + reg_ldob: ldob { + regulator-name = "ldob"; + }; + }; + + sram@400000 { + compatible = "mmio-sram"; + reg = <0x400000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400000 0x20000>; + + /* + * This can be further divided into DSP IRAM, + * DSP DRAM0, and DSP DRAM1, but the mapping + * of all three is controlled by a single bit. + */ + dsp_sram: sram-section@0 { + compatible = "allwinner,sun20i-d1-dsp-sram"; + reg = <0 0x20000>; + }; + }; + + // FIXME: Address is not verified. It is copied from A64/H6. + sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x1d00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1d00000 0x40000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun20i-d1-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0 0x40000>; + }; + }; + }; + + dma: dma-controller@3002000 { + compatible = "allwinner,sun20i-d1-dma"; + reg = <0x3002000 0x1000>; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + dma-channels = <16>; + dma-requests = <48>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>, + <142 IRQ_TYPE_LEVEL_HIGH>; + }; + + msgbox: mailbox@3003000 { + compatible = "allwinner,sun20i-d1-msgbox"; + reg = <0x3003000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX0>; + resets = <&ccu RST_BUS_MSGBOX0>; + interrupts = <101 IRQ_TYPE_LEVEL_HIGH>, + <102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + #mbox-cells = <2>; + }; + + hwspinlock: hwlock@3005000 { + compatible = "allwinner,sun20i-d1-hwspinlock", + "allwinner,sun6i-a31-hwspinlock"; + reg = <0x3005000 0x1000>; + clocks = <&ccu CLK_BUS_SPINLOCK>; + resets = <&ccu RST_BUS_SPINLOCK>; + interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; + }; + + sid: efuse@3006000 { + compatible = "allwinner,sun20i-d1-sid", + "allwinner,sun50i-a64-sid"; + reg = <0x3006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: cpu-speed-grade@0 { + reg = <0x0 0x2>; + }; + + ths_calib: ths-calib@14 { + reg = <0x14 0x4>; + }; + }; + + // TODO: write a binding and driver. + hstimer: timer@3008000 { + compatible = "allwinner,sun20i-d1-hstimer", + "allwinner,sun50i-h6-hstimer"; + reg = <0x3008000 0x1000>; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>, + <72 IRQ_TYPE_LEVEL_HIGH>; + }; + + crypto: crypto@3040000 { + compatible = "allwinner,sun20i-d1-crypto"; + reg = <0x3040000 0x800>; + clocks = <&ccu CLK_BUS_CE>, + <&ccu CLK_CE>, + <&ccu CLK_MBUS_CE>, + <&rtc CLK_IOSC>; + clock-names = "bus", "mod", "ram", "trng"; + resets = <&ccu RST_BUS_CE>; + interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; + }; + + // TODO: write a binding and driver. + mbus: dram-controller@3102000 { + compatible = "allwinner,sun20i-d1-mbus"; + reg = <0x3102000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&ccu CLK_BUS_DRAM>, + <&ccu CLK_DRAM>, + <&ccu CLK_MBUS>; + clock-names = "bus", "dram", "mbus"; + dma-ranges = <0 0x40000000 0x80000000>; + #interconnect-cells = <1>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + }; + + mmc0: mmc@4020000 { + compatible = "allwinner,sun20i-d1-mmc"; + reg = <0x4020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + cap-sd-highspeed; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + no-mmc; + status = "disabled"; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun20i-d1-mmc"; + reg = <0x4021000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + cap-sd-highspeed; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + no-mmc; + status = "disabled"; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun20i-d1-emmc"; + reg = <0x4022000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + cap-mmc-highspeed; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + no-sd; + no-sdio; + status = "disabled"; + }; + + spi0: spi@4025000 { + compatible = "allwinner,sun20i-d1-spi", + "allwinner,sun50i-r329-spi"; + reg = <0x4025000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + spi1: spi@4026000 { + compatible = "allwinner,sun20i-d1-spi-dbi", + "allwinner,sun50i-r329-spi-dbi", + "allwinner,sun50i-r329-spi"; + reg = <0x4026000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + usb_otg: usb@4100000 { + compatible = "allwinner,sun20i-d1-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x4100000 0x400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + dmas = <&dma 30>, <&dma 30>, + <&dma 31>, <&dma 31>, + <&dma 32>, <&dma 32>, + <&dma 33>, <&dma 33>, + <&dma 34>, <&dma 34>; + dma-names = "ep1_rx", "ep1_tx", + "ep2_rx", "ep2_tx", + "ep3_rx", "ep3_tx", + "ep4_rx", "ep4_tx", + "ep5_rx", "ep5_tx"; + extcon = <&usbphy 0>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: phy@4100400 { + compatible = "allwinner,sun20i-d1-usb-phy"; + reg = <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1"; + clocks = <&osc24M>, + <&osc24M>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + #phy-cells = <1>; + status = "disabled"; + }; + + ehci0: usb@4101000 { + compatible = "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg = <0x4101000 0x100>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@4101400 { + compatible = "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg = <0x4101400 0x100>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@4200000 { + compatible = "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg = <0x4200000 0x100>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@4200400 { + compatible = "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg = <0x4200400 0x100>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + emac: ethernet@4500000 { + compatible = "allwinner,sun20i-d1-emac", + "allwinner,sun50i-a64-emac"; + reg = <0x4500000 0x10000>; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + syscon = <&syscon>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + display_clocks: clock-controller@5000000 { + compatible = "allwinner,sun20i-d1-de2-clk", + "allwinner,sun50i-h5-de2-clk"; + reg = <0x5000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@5100000 { + compatible = "allwinner,sun20i-d1-de2-mixer-0"; + reg = <0x5100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + iommus = <&iommu 2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon_top_mixer0: endpoint { + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@5200000 { + compatible = "allwinner,sun20i-d1-de2-mixer-1"; + reg = <0x5200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER1>; + iommus = <&iommu 2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + + mixer1_out_tcon_top_mixer1: endpoint { + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + + deinterlace: deinterlace@5400000 { + reg = <0x5400000 0x10000>; + interconnects = <&mbus 10>; + interconnect-names = "dma-mem"; + interrupts = <104 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&iommu 4>; + }; + + g2d: g2d@5410000 { + reg = <0x5410000 0x40000>; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&iommu 3>; + }; + + dsi: dsi@5450000 { + reg = <0x5450000 0x2000>; + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; + }; + + tcon_top: tcon-top@5460000 { + compatible = "allwinner,sun20i-d1-tcon-top"; + reg = <0x5460000 0x1000>; + clocks = <&ccu CLK_BUS_DPSS_TOP>, + <&ccu CLK_TCON_TV>, + <&ccu CLK_TVE>, + <&ccu CLK_MIPI_DSI>; + clock-names = "bus", + "tcon-tv0", + "tve0", + "dsi"; + clock-output-names = "tcon-top-tv0", + "tcon-top-dsi"; + resets = <&ccu RST_BUS_DPSS_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer0_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon_top_mixer1>; + }; + }; + + tcon_top_mixer1_out: port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + reg = <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint { + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_tcon_top>; + }; + }; + }; + }; + + tcon_lcd0: lcd-controller@5461000 { + compatible = "allwinner,sun20i-d1-tcon-lcd"; + reg = <0x5461000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_LCD0>, + <&ccu CLK_TCON_LCD0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON_LCD0>, + <&ccu RST_BUS_LVDS0>; + reset-names = "lcd", "lvds"; + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; + }; + + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; + }; + }; + + tcon_lcd0_out: port@1 { + reg = <1>; + }; + }; + }; + + tcon_tv0: lcd-controller@5470000 { + compatible = "allwinner,sun20i-d1-tcon-tv"; + reg = <0x5470000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_TV>, + <&tcon_top CLK_TCON_TOP_TV0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV>; + reset-names = "lcd"; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + reg = <1>; + + tcon_tv0_out_tcon_top_hdmi: endpoint { + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + hdmi: hdmi@5500000 { + compatible = "allwinner,sun20i-d1-dw-hdmi"; + reg = <0x5500000 0x10000>; + reg-io-width = <1>; + clocks = <&ccu CLK_BUS_HDMI>, + <&ccu CLK_HDMI_24M>, + <&tcon_top CLK_TCON_TOP_TV0>, + <&ccu CLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "tmds", "cec"; + resets = <&ccu RST_BUS_HDMI_MAIN>, <&ccu RST_BUS_HDMI_SUB>; + reset-names = "ctrl", "sub"; + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hdmi_phy>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in_tcon_top: endpoint { + remote-endpoint = <&tcon_top_hdmi_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: phy@5510000 { + compatible = "allwinner,sun20i-d1-hdmi-phy"; + reg = <0x5510000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_24M>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_HDMI_MAIN>; + reset-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + tve_top: video-codec@5600000 { + reg = <0x5600000 0x4000>; + }; + + tve0: video-codec@5604000 { + reg = <0x5604000 0x4000>; + interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; + }; + + csi: csi@5800000 { + reg = <0x5800000 0x400000>; + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>, + <112 IRQ_TYPE_LEVEL_HIGH>, + <116 IRQ_TYPE_LEVEL_HIGH>, + <122 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mbus 7>; + interconnect-names = "dma-mem"; + iommus = <&iommu 1>; + }; + + tvd_top: video-codec@5c00000 { + reg = <0x5c00000 0x1000>; + interconnects = <&mbus 6>; + interconnect-names = "dma-mem"; + }; + + tvd0: video-codec@5c01000 { + reg = <0x5c01000 0x1000>; + interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@6010000 { + compatible = "allwinner,sun20i-d1-intc"; + reg = <0x6010000 0x100>; + #address-cells = <0>; + clocks = <&ccu CLK_BUS_RISCV_CFG>; + resets = <&ccu RST_BUS_RISCV_CFG>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + riscv_wdt: watchdog@6011000 { + compatible = "allwinner,sun20i-d1-wdt"; + reg = <0x6011000 0x20>; + clocks = <&osc24M>; + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>; + }; + + riscv_msgbox: mailbox@601f000 { + compatible = "allwinner,sun20i-d1-msgbox"; + reg = <0x601f000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX2>; + resets = <&ccu RST_BUS_MSGBOX2>; + interrupts = <144 IRQ_TYPE_LEVEL_HIGH>, + <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + #mbox-cells = <2>; + }; + + r_ccu: clock-controller@7010000 { + compatible = "allwinner,sun20i-d1-r-ccu"; + reg = <0x7010000 0x400>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_DIV3>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + }; + + r_ir_rx: ir@7040000 { + compatible = "allwinner,sun20i-d1-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x7040000 0x400>; + clocks = <&r_ccu CLK_BUS_R_IR_RX>, <&r_ccu CLK_R_IR_RX>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_BUS_R_IR_RX>; + interrupts = <167 IRQ_TYPE_LEVEL_HIGH>; + }; + + // TODO: audit all blocks for hidden use of CLK_DCXO24M + rtc: rtc@7090000 { + compatible = "allwinner,sun20i-d1-rtc", + "allwinner,sun50i-r329-rtc"; + reg = <0x7090000 0x400>; + clocks = <&r_ccu CLK_BUS_R_RTC>, + <&osc24M>, + <&r_ccu CLK_R_AHB>; + clock-names = "bus", "hosc", "ahb"; + #clock-cells = <1>; + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>; + }; + + plic: interrupt-controller@10000000 { + compatible = "allwinner,sun20i-d1-plic", + "thead,c900-plic"; + reg = <0x10000000 0x4000000>; + #address-cells = <0>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu0_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + riscv,ndev = <176>; + }; + + clint: clint@14000000 { + compatible = "allwinner,sun20i-d1-clint", + "thead,c900-clint"; + reg = <0x14000000 0xc000>; + reg-io-width = <4>; + interrupts-extended = <&cpu0_intc 3>, + <&cpu0_intc 7>; + }; + }; +}; diff --git a/arch/riscv/dts/sunxi-u-boot.dtsi b/arch/riscv/dts/sunxi-u-boot.dtsi new file mode 100644 index 00000000000..c2935745699 --- /dev/null +++ b/arch/riscv/dts/sunxi-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "binman.dtsi" diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 084a8b0c6ca..6eee18dd6a7 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -1,5 +1,24 @@ +menu "Board-specific options" + depends on ARCH_SUNXI || TARGET_SUNXI + +choice + prompt "sunxi SoC Variant" + +config MACH_SUN20I + bool "sun20i (Allwinner D1)" + depends on RISCV + select GENERIC_RISCV + select SPL_DM if SPL + imply SYSRESET_SBI + +endchoice + +config NR_DRAM_BANKS + default 1 + choice prompt "SPL Image Type" + depends on SPL default SPL_IMAGE_TYPE_SUNXI_EGON config SPL_IMAGE_TYPE_SUNXI_EGON @@ -22,3 +41,72 @@ config SPL_IMAGE_TYPE string default "sunxi_egon" if SPL_IMAGE_TYPE_SUNXI_EGON default "sunxi_toc0" if SPL_IMAGE_TYPE_SUNXI_TOC0 + +config SPL_MAX_SIZE + hex + default SUNXI_SRAM_SIZE + +config SPL_OPENSBI_LOAD_ADDR + default 0x40000000 + +config SUNXI_SRAM_ADDRESS + hex + default 0x20000 if MACH_SUN20I + +config SUNXI_SRAM_SIZE + hex + default 0x28000 if MACH_SUN20I + +config SYS_BOARD + default "sunxi" + +config SYS_CONFIG_NAME + default "sun20i" if MACH_SUN20I + +config SYS_CPU + default "generic" if MACH_SUN20I + +config SYS_SOC + default "sunxi" + +config SYS_TEXT_BASE + default 0x4a000000 if MACH_SUN20I + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CLK + select DM_ETH if NET + select DM_GPIO + select DM_I2C if I2C + select DM_SERIAL + select DM_SPI if SPI + select GPIO + select MMC_SUNXI_HAS_NEW_MODE if MMC_SUNXI + select OF_HAS_PRIOR_STAGE + select PHY_SUN4I_USB if USB + select PINCTRL + select SPL_CLK if SPL_DM + select SPL_GPIO if SPL_DM + select SPL_OF_CONTROL if SPL_DM + select SPL_PINCTRL if SPL_DM + select SPL_SEPARATE_BSS if SPL + select SUPPORT_SPL + imply CMD_MMC + imply CMD_USB + imply DISTRO_DEFAULTS + imply FIT + imply MMC + imply SPL + imply SPL_SPI if SPI + imply SPL_MMC if MMC + imply SUNXI_GPIO + imply SYS_I2C_MVTWSI + imply SYS_NS16550 + imply SYSRESET + imply USB_EHCI_GENERIC + imply USB_EHCI_HCD + imply USB_OHCI_GENERIC + imply USB_OHCI_HCD + imply WDT + +endmenu diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index d96b7897b6c..aea2aac8a1e 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -6,7 +6,8 @@ # # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y += board.o +obj-$(CONFIG_ARCH_SUNXI) += board.o +obj-$(CONFIG_TARGET_SUNXI) += board-riscv.o obj-$(CONFIG_SUN7I_GMAC) += gmac.o obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o diff --git a/board/sunxi/board-riscv.c b/board/sunxi/board-riscv.c new file mode 100644 index 00000000000..3dccd5c40f5 --- /dev/null +++ b/board/sunxi/board-riscv.c @@ -0,0 +1,23 @@ +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void *board_fdt_blob_setup(int *err) +{ + *err = 0; + + return (void *)(ulong)gd->arch.firmware_fdt_addr; +} + +int board_init(void) +{ + /* https://lore.kernel.org/u-boot/31587574-4cd1-02da-9761-0134ac82b94b@sholland.org/ */ + return cpu_probe_all(); +} + +uint32_t spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 69adcf66fea..a57f22e46e7 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -175,7 +175,7 @@ config SPL_TEXT_BASE hex "SPL Text Base" default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I - default 0x20060 if SUN50I_GEN_H6 + default 0x20060 if SUN50I_GEN_H6 || MACH_SUN20I default 0x00060 if ARCH_SUNXI default 0xfffc0000 if ARCH_ZYNQMP default 0x0 @@ -1323,7 +1323,7 @@ config SPL_OPTEE_IMAGE config SPL_OPENSBI bool "Support RISC-V OpenSBI" - depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE + depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE && SPL_LOAD_FIT help OpenSBI is an open-source implementation of the RISC-V Supervisor Binary Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC diff --git a/configs/nezha_defconfig b/configs/nezha_defconfig new file mode 100644 index 00000000000..8f5d772b276 --- /dev/null +++ b/configs/nezha_defconfig @@ -0,0 +1,31 @@ +CONFIG_RISCV=y +CONFIG_DEFAULT_DEVICE_TREE="sun20i-d1-nezha" +CONFIG_TARGET_SUNXI=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +# CONFIG_SPL_SMP is not set +CONFIG_SYS_LOAD_ADDR=0x4a000000 +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SPI=y +CONFIG_CMD_WDT=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_PHY_REALTEK=y +CONFIG_SUN8I_EMAC=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f5b553172c2..bfcb295f4b9 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_NPCM) += nuvoton/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SOCFPGA) += altera/ -obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o @@ -41,6 +40,7 @@ obj-$(CONFIG_CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o +obj-$(CONFIG_CLK_SUNXI) += sunxi/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o obj-$(CONFIG_CLK_VERSAL) += clk_versal.o diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 9680fb1690b..a757d949cdf 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -1,6 +1,6 @@ config CLK_SUNXI bool "Clock support for Allwinner SoCs" - depends on CLK && ARCH_SUNXI + depends on CLK && (ARCH_SUNXI || TARGET_SUNXI) select DM_RESET select SPL_DM_RESET if SPL_CLK default y @@ -98,6 +98,7 @@ config CLK_SUN8I_H3 config CLK_SUN20I_D1 bool "Clock driver for Allwinner D1" + default MACH_SUN20I help This enables common clock driver support for platforms based on Allwinner D1 SoC. diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 33a4b6f30db..b2424a4b1e4 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -19,14 +19,14 @@ if PHYLIB config PHY_ADDR_ENABLE bool "Limit phy address" - default y if ARCH_SUNXI + default y if (ARCH_SUNXI || TARGET_SUNXI) help Select this if you want to control which phy address is used if PHY_ADDR_ENABLE config PHY_ADDR int "PHY address" - default 1 if ARCH_SUNXI + default 1 if (ARCH_SUNXI || TARGET_SUNXI) default 0 help The address of PHY on MII bus. Usually in range of 0 to 31. diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig index 619b6a797a6..52af8f9c247 100644 --- a/drivers/phy/allwinner/Kconfig +++ b/drivers/phy/allwinner/Kconfig @@ -3,7 +3,7 @@ # config PHY_SUN4I_USB bool "Allwinner Sun4I USB PHY driver" - depends on ARCH_SUNXI + depends on (ARCH_SUNXI || TARGET_SUNXI) select DM_REGULATOR select PHY help diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index b57714111b5..2428703b220 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -137,7 +137,7 @@ config RESET_MTMIPS config RESET_SUNXI bool "RESET support for Allwinner SoCs" - depends on DM_RESET && ARCH_SUNXI + depends on DM_RESET && (ARCH_SUNXI || TARGET_SUNXI) default y help This enables support for common reset driver for diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2bc..7adeb6a4ab5 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -403,7 +403,7 @@ config SOFT_SPI config SPI_SUNXI bool "Allwinner SoC SPI controllers" - default ARCH_SUNXI + default (ARCH_SUNXI || TARGET_SUNXI) help Enable the Allwinner SoC SPi controller driver. diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 9ba3b9e43c9..8cde4ca53d2 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -40,7 +40,7 @@ if USB_GADGET config USB_GADGET_MANUFACTURER string "Vendor name of the USB device" - default "Allwinner Technology" if ARCH_SUNXI + default "Allwinner Technology" if (ARCH_SUNXI || TARGET_SUNXI) default "Rockchip" if ARCH_ROCKCHIP default "U-Boot" help @@ -49,7 +49,7 @@ config USB_GADGET_MANUFACTURER config USB_GADGET_VENDOR_NUM hex "Vendor ID of the USB device" - default 0x1f3a if ARCH_SUNXI + default 0x1f3a if (ARCH_SUNXI || TARGET_SUNXI) default 0x2207 if ARCH_ROCKCHIP default 0x0 help @@ -59,7 +59,7 @@ config USB_GADGET_VENDOR_NUM config USB_GADGET_PRODUCT_NUM hex "Product ID of the USB device" - default 0x1010 if ARCH_SUNXI + default 0x1010 if (ARCH_SUNXI || TARGET_SUNXI) default 0x310a if ROCKCHIP_RK3036 default 0x310c if ROCKCHIP_RK3128 default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288 diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index 51f876cd711..37e3f8f9fba 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -67,7 +67,7 @@ config USB_MUSB_PIC32 config USB_MUSB_SUNXI bool "Enable sunxi OTG / DRC USB controller" - depends on ARCH_SUNXI + depends on (ARCH_SUNXI || TARGET_SUNXI) select USB_MUSB_PIO_ONLY default y ---help--- diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index c3eb8a8aec1..487efb6c828 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -28,7 +28,7 @@ config WATCHDOG_TIMEOUT_MSECS default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX7 || ARCH_VF610 default 30000 if ARCH_SOCFPGA - default 16000 if ARCH_SUNXI + default 16000 if (ARCH_SUNXI || TARGET_SUNXI) default 60000 help Watchdog timeout in msec @@ -306,7 +306,7 @@ config WDT_STM32MP config WDT_SUNXI bool "Allwinner sunxi watchdog timer support" - depends on WDT && ARCH_SUNXI + depends on WDT && (ARCH_SUNXI || TARGET_SUNXI) default y help Enable support for the watchdog timer in Allwinner sunxi SoCs. diff --git a/include/configs/sun20i.h b/include/configs/sun20i.h new file mode 100644 index 00000000000..640e740810e --- /dev/null +++ b/include/configs/sun20i.h @@ -0,0 +1,68 @@ +#include + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* FIXME: Need a real clock driver! */ +#define CONFIG_SYS_NS16550_CLK 24000000 +#define CONFIG_SYS_TCLK 24000000 + +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#endif + +#define CONFIG_SYS_INIT_SP_ADDR 0x4fe00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ +#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 +#define CONFIG_SPL_STACK 0x00048000 + +#define SDRAM_OFFSET(x) 0x4##x +#define BOOTM_SIZE __stringify(0xa000000) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0200000)) +#define KERNEL_COMP_ADDR_R __stringify(SDRAM_OFFSET(4000000)) +#define KERNEL_COMP_SIZE __stringify(0xb000000) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000)) + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=" BOOTM_SIZE "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ + "kernel_comp_size=" KERNEL_COMP_SIZE "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" + +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#ifdef CONFIG_CMD_DHCP +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_DHCP(func) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h new file mode 100644 index 00000000000..4c2697fd32b --- /dev/null +++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ + +#define CLK_R_AHB 0 + +#define CLK_BUS_R_TIMER 2 +#define CLK_BUS_R_TWD 3 +#define CLK_BUS_R_PPU 4 +#define CLK_R_IR_RX 5 +#define CLK_BUS_R_IR_RX 6 +#define CLK_BUS_R_RTC 7 +#define CLK_BUS_R_CPUCFG 8 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h new file mode 100644 index 00000000000..c845493e4d3 --- /dev/null +++ b/include/dt-bindings/clock/sun6i-rtc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ + +#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ +#define _DT_BINDINGS_CLK_SUN6I_RTC_H_ + +#define CLK_OSC32K 0 +#define CLK_OSC32K_FANOUT 1 +#define CLK_IOSC 2 + +#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */ diff --git a/include/dt-bindings/mailbox/sun20i-d1-msgbox.h b/include/dt-bindings/mailbox/sun20i-d1-msgbox.h new file mode 100644 index 00000000000..3d6533de98c --- /dev/null +++ b/include/dt-bindings/mailbox/sun20i-d1-msgbox.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ +#define _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ + +/* First cell: channel (transmitting user) */ +#define MBOX_USER_CPUX 0 +#define MBOX_USER_DSP 1 +#define MBOX_USER_RISCV 2 + +/* Second cell: direction (RX if phandle references local mailbox, else TX) */ +#define MBOX_RX 0 +#define MBOX_TX 1 + +#endif /* _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h new file mode 100644 index 00000000000..d93d6423d28 --- /dev/null +++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_TWD 1 +#define RST_BUS_R_PPU 2 +#define RST_BUS_R_IR_RX 3 +#define RST_BUS_R_RTC 4 +#define RST_BUS_R_CPUCFG 5 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */ diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index f047d4e0941..e8e9772a95a 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -271,6 +271,10 @@ INPUTS-y += $(obj)/sunxi-spl-with-ecc.bin endif endif +ifdef CONFIG_TARGET_SUNXI +INPUTS-y += $(obj)/sunxi-spl.bin +endif + ifeq ($(CONFIG_SYS_SOC),"at91") INPUTS-y += $(obj)/boot.bin endif