Merge branch '2023-01-20-finish-CONFIG-migration-work'

- Merge in the final batch of CONFIG to Kconfig/CFG migration work. This
  includes a fix for a number of ns16550 or similar UARTs due to a
  migration bug. We also pull in a revert for enabling CONFIG_VIDEO on
  tools-only_defconfig.

.azure-pipelines.yml

@@ -64,7 +64,8 @@ stages:
       # If grep succeeds and finds a match the test fails as we should
       # have no matches.
       - script: git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
-                  include/configs `find arch -name config.h` && exit 1 || exit 0
+                  :^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
+                  :^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
 
   - job: cppcheck
     displayName: 'Static code analysis with cppcheck'

.gitlab-ci.yml

@@ -131,7 +131,8 @@ check for new CONFIG symbols outside Kconfig:
     # If grep succeeds and finds a match the test fails as we should
     # have no matches.
     - git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
-        include/configs `find arch -name config.h` && exit 1 || exit 0
+        :^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
+        :^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
 
 # QA jobs for code analytics
 # static code analysis with cppcheck (we can add --enable=all later)

README

@@ -445,12 +445,12 @@ The following options need to be configured:
 		example "env grep" and "setexpr".
 
 - Watchdog:
-		CONFIG_SYS_WATCHDOG_FREQ
+		CFG_SYS_WATCHDOG_FREQ
 		Some platforms automatically call WATCHDOG_RESET()
 		from the timer interrupt handler every
-		CONFIG_SYS_WATCHDOG_FREQ interrupts. If not set by the
+		CFG_SYS_WATCHDOG_FREQ interrupts. If not set by the
 		board configuration file, a default of CONFIG_SYS_HZ/2
-		(i.e. 500) is used. Setting CONFIG_SYS_WATCHDOG_FREQ
+		(i.e. 500) is used. Setting CFG_SYS_WATCHDOG_FREQ
 		to 0 disables calling WATCHDOG_RESET() from the timer
 		interrupt.
 
@@ -523,7 +523,7 @@ The following options need to be configured:
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 
-			CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
+			CFG_SYS_DAVINCI_EMAC_PHY_COUNT
 			Define this if you have more then 3 PHYs.
 
 		CONFIG_FTGMAC100
@@ -653,7 +653,7 @@ The following options need to be configured:
 		To enable the ULPI layer support, define CONFIG_USB_ULPI and
 		CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
 		If your ULPI phy needs a different reference clock than the
-		standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
+		standard 24 MHz then you have to define CFG_ULPI_REF_CLK to
 		the appropriate value in Hz.
 
 - MMC Support:
@@ -734,7 +734,7 @@ The following options need to be configured:
 		4th and following
 		BOOTP requests:		delay 0 ... 8 sec
 
-		CONFIG_BOOTP_ID_CACHE_SIZE
+		CFG_BOOTP_ID_CACHE_SIZE
 
 		BOOTP packets are uniquely identified using a 32-bit ID. The
 		server will copy the ID from client requests to responses and
@@ -747,7 +747,7 @@ The following options need to be configured:
 		time is too long, U-Boot will retransmit requests. In order
 		to allow earlier responses to still be accepted after these
 		retransmissions, U-Boot's BOOTP client keeps a small cache of
-		IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this
+		IDs. The CFG_BOOTP_ID_CACHE_SIZE controls the size of this
 		cache. The default is to keep IDs for up to four outstanding
 		requests. Increasing this will allow U-Boot to accept offers
 		from a BOOTP client in networks with unusually high latency.
@@ -832,11 +832,11 @@ The following options need to be configured:
 		status LED backend implementation. Define CONFIG_LED_STATUS_GPIO
 		to include the gpio_led driver in the U-Boot binary.
 
-		CONFIG_GPIO_LED_INVERTED_TABLE
+		CFG_GPIO_LED_INVERTED_TABLE
 		Some GPIO connected LEDs may have inverted polarity in which
 		case the GPIO high value corresponds to LED off state and
 		GPIO low value corresponds to LED on state.
-		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
+		In such cases CFG_GPIO_LED_INVERTED_TABLE may be defined
 		with a list of GPIO LEDs that have inverted polarity.
 
 - I2C Support:
@@ -993,7 +993,7 @@ The following options need to be configured:
 		SPI EEPROM, also an instance works with Crystal A/D and
 		D/As on the SACSng board)
 
-		CONFIG_SYS_SPI_MXC_WAIT
+		CFG_SYS_SPI_MXC_WAIT
 		Timeout for waiting until spi transfer completed.
 		default: (CONFIG_SYS_HZ/100)     /* 10 ms */
 
@@ -1023,7 +1023,7 @@ The following options need to be configured:
 		If defined, a function that provides delays in the FPGA
 		configuration driver.
 
-		CONFIG_SYS_FPGA_CHECK_ERROR
+		CFG_SYS_FPGA_CHECK_ERROR
 
 		Check for configuration errors during FPGA bitfile
 		loading. For example, abort during Virtex II
@@ -1319,7 +1319,7 @@ Configuration Settings:
 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
 		undefine this when you're short of memory.
 
-- CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
+- CFG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
 		width of the commands listed in the 'help' command output.
 
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to

arch/Kconfig.nxp

@@ -256,6 +256,20 @@ config SYS_FSL_ESDHC_BE
 config SYS_FSL_IFC_BE
 	bool
 
+config SYS_FSL_IFC_BANK_COUNT
+	int "Maximum banks of Integrated flash controller"
+	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
+		ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
+		ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
+		ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
+		ARCH_BSC9132
+	default 3 if ARCH_BSC9131 || ARCH_BSC9132
+	default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
+			ARCH_B4420 || ARCH_P1010
+	default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
+			ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
+			ARCH_T1024 || ARCH_T2080 || ARCH_C29X
+
 config FSL_QIXIS
 	bool "Enable QIXIS support"
 	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
@@ -272,4 +286,13 @@ config HAS_FSL_DR_USB
 config SYS_DPAA_FMAN
 	bool
 
+config SYS_FSL_SRDS_1
+	bool
+
+config SYS_FSL_SRDS_2
+	bool
+
+config SYS_HAS_SERDES
+	bool
+
 endmenu

arch/arc/Kconfig

@@ -102,6 +102,13 @@ config ARC_MMU_V4
 
 endchoice
 
+config ARC_MMU_VER
+	int
+	default 0 if ARC_MMU_ABSENT
+	default 2 if ARC_MMU_V2
+	default 3 if ARC_MMU_V3
+	default 4 if ARC_MMU_V4
+
 config CPU_BIG_ENDIAN
 	bool "Enable Big Endian Mode"
 	help

arch/arc/include/asm/cache.h

@@ -16,16 +16,6 @@
  */
 #define ARCH_DMA_MINALIGN	128
 
-#if defined(ARC_MMU_ABSENT)
-#define CONFIG_ARC_MMU_VER 0
-#elif defined(CONFIG_ARC_MMU_V2)
-#define CONFIG_ARC_MMU_VER 2
-#elif defined(CONFIG_ARC_MMU_V3)
-#define CONFIG_ARC_MMU_VER 3
-#elif defined(CONFIG_ARC_MMU_V4)
-#define CONFIG_ARC_MMU_VER 4
-#endif
-
 #ifndef __ASSEMBLY__
 
 void cache_init(void);

arch/arm/cpu/arm1176/start.S

@@ -17,10 +17,6 @@
 #include <config.h>
 #include <linux/linkage.h>
 
-#ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE	CFG_SYS_UBOOT_BASE
-#endif
-
 /*
  *************************************************************************
  *
@@ -88,7 +84,7 @@ cpu_init_crit:
 
 	/* Prepare to disable the MMU */
 	adr	r2, mmu_disable_phys
-	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_TEXT_BASE)
+	sub	r2, r2, #(CFG_SYS_UBOOT_BASE - CONFIG_TEXT_BASE)
 	b	mmu_disable
 
 	.align 5

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -93,19 +93,6 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_HAS_CCI400
 	bool
 
-config SYS_FSL_SRDS_1
-	bool
-
-config SYS_FSL_SRDS_2
-	bool
-
-config SYS_HAS_SERDES
-	bool
-
-config SYS_FSL_IFC_BANK_COUNT
-	int "Maximum banks of Integrated flash controller"
-	default 8
-
 config SYS_FSL_ERRATUM_A008407
 	bool
 

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -525,13 +525,6 @@ config SYS_CCI400_OFFSET
 	  Offset for CCI400 base
 	  CCI400 base addr = CCSRBAR + CCI400_OFFSET
 
-config SYS_FSL_IFC_BANK_COUNT
-	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
-	default 4 if ARCH_LS1043A
-	default 4 if ARCH_LS1046A
-	default 8 if ARCH_LS2080A || ARCH_LS1088A
-
 config SYS_FSL_HAS_CCI400
 	bool
 
@@ -574,18 +567,9 @@ config SYS_DP_DDR_BASE_PHY
 	  DDR controller uses this value as the base address for binding.
 	  It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 
-config SYS_FSL_SRDS_1
-	bool
-
-config SYS_FSL_SRDS_2
-	bool
-
 config SYS_NXP_SRDS_3
 	bool
 
-config SYS_HAS_SERDES
-	bool
-
 config FSL_TZASC_1
 	bool
 

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -91,8 +91,8 @@ static struct cpu_type cpu_type_list[] = {
 #define EARLY_PGTABLE_SIZE 0x5000
 static struct mm_region early_map[] = {
 #ifdef CONFIG_FSL_LSCH3
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+	{ CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE,
+	  CFG_SYS_FSL_CCSR_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -101,26 +101,26 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
 	{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
-	  CONFIG_SYS_FSL_QSPI_SIZE1,
+	  CFG_SYS_FSL_QSPI_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
 #ifdef CONFIG_FSL_IFC
 	/* For IFC Region #1, only the first 4MB is cache-enabled */
-	{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+	{ CFG_SYS_FSL_IFC_BASE1, CFG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1_1,
+	  CFG_SYS_FSL_IFC_SIZE1_1,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
-	{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+	{ CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
-	  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+	  CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
-	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+	  CFG_SYS_FSL_IFC_SIZE1 - CFG_SYS_FSL_IFC_SIZE1_1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
-	{ CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+	{ CFG_SYS_FLASH_BASE, CFG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1,
+	  CFG_SYS_FSL_IFC_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
 #endif
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+	{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1,
+	  CFG_SYS_FSL_DRAM_SIZE1,
 #if defined(CONFIG_TFABOOT) || \
 	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
@@ -131,31 +131,31 @@ static struct mm_region early_map[] = {
 	},
 #ifdef CONFIG_FSL_IFC
 	/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
-	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+	{ CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
-	  CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+	  CFG_SYS_FLASH_BASE - CFG_SYS_FSL_IFC_BASE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
 #endif
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+	{ CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE,
+	  CFG_SYS_FSL_DCSR_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+	{ CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2,
+	  CFG_SYS_FSL_DRAM_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-#ifdef CONFIG_SYS_FSL_DRAM_BASE3
+#ifdef CFG_SYS_FSL_DRAM_BASE3
-	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+	{ CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
-	  CONFIG_SYS_FSL_DRAM_SIZE3,
+	  CFG_SYS_FSL_DRAM_SIZE3,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 #endif
 #elif defined(CONFIG_FSL_LSCH2)
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+	{ CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE,
+	  CFG_SYS_FSL_CCSR_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -163,23 +163,23 @@ static struct mm_region early_map[] = {
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+	{ CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE,
+	  CFG_SYS_FSL_DCSR_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
-	  CONFIG_SYS_FSL_QSPI_SIZE,
+	  CFG_SYS_FSL_QSPI_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
 #ifdef CONFIG_FSL_IFC
-	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+	{ CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
-	  CONFIG_SYS_FSL_IFC_SIZE,
+	  CFG_SYS_FSL_IFC_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
 #endif
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+	{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1,
+	  CFG_SYS_FSL_DRAM_SIZE1,
 #if defined(CONFIG_TFABOOT) || \
 	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
@@ -188,8 +188,8 @@ static struct mm_region early_map[] = {
 #endif
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+	{ CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2,
+	  CFG_SYS_FSL_DRAM_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
@@ -199,8 +199,8 @@ static struct mm_region early_map[] = {
 
 static struct mm_region final_map[] = {
 #ifdef CONFIG_FSL_LSCH3
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+	{ CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE,
+	  CFG_SYS_FSL_CCSR_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -208,52 +208,52 @@ static struct mm_region final_map[] = {
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+	{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1,
+	  CFG_SYS_FSL_DRAM_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 	{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
-	  CONFIG_SYS_FSL_QSPI_SIZE1,
+	  CFG_SYS_FSL_QSPI_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
-	  CONFIG_SYS_FSL_QSPI_SIZE2,
+	  CFG_SYS_FSL_QSPI_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #ifdef CONFIG_FSL_IFC
-	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+	{ CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
-	  CONFIG_SYS_FSL_IFC_SIZE2,
+	  CFG_SYS_FSL_IFC_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #endif
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+	{ CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE,
+	  CFG_SYS_FSL_DCSR_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
+	{ CFG_SYS_FSL_MC_BASE, CFG_SYS_FSL_MC_BASE,
-	  CONFIG_SYS_FSL_MC_SIZE,
+	  CFG_SYS_FSL_MC_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
+	{ CFG_SYS_FSL_NI_BASE, CFG_SYS_FSL_NI_BASE,
-	  CONFIG_SYS_FSL_NI_SIZE,
+	  CFG_SYS_FSL_NI_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	/* For QBMAN portal, only the first 64MB is cache-enabled */
-	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+	{ CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
-	  CONFIG_SYS_FSL_QBMAN_SIZE_1,
+	  CFG_SYS_FSL_QBMAN_SIZE_1,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 	},
-	{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+	{ CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
-	  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+	  CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
-	  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+	  CFG_SYS_FSL_QBMAN_SIZE - CFG_SYS_FSL_QBMAN_SIZE_1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -295,29 +295,29 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #endif
-	{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
+	{ CFG_SYS_FSL_WRIOP1_BASE, CFG_SYS_FSL_WRIOP1_BASE,
-	  CONFIG_SYS_FSL_WRIOP1_SIZE,
+	  CFG_SYS_FSL_WRIOP1_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
+	{ CFG_SYS_FSL_AIOP1_BASE, CFG_SYS_FSL_AIOP1_BASE,
-	  CONFIG_SYS_FSL_AIOP1_SIZE,
+	  CFG_SYS_FSL_AIOP1_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
+	{ CFG_SYS_FSL_PEBUF_BASE, CFG_SYS_FSL_PEBUF_BASE,
-	  CONFIG_SYS_FSL_PEBUF_SIZE,
+	  CFG_SYS_FSL_PEBUF_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+	{ CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2,
+	  CFG_SYS_FSL_DRAM_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-#ifdef CONFIG_SYS_FSL_DRAM_BASE3
+#ifdef CFG_SYS_FSL_DRAM_BASE3
-	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+	{ CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
-	  CONFIG_SYS_FSL_DRAM_SIZE3,
+	  CFG_SYS_FSL_DRAM_SIZE3,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
@@ -328,8 +328,8 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+	{ CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE,
+	  CFG_SYS_FSL_CCSR_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -337,34 +337,34 @@ static struct mm_region final_map[] = {
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+	{ CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE,
+	  CFG_SYS_FSL_DCSR_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
-	  CONFIG_SYS_FSL_QSPI_SIZE,
+	  CFG_SYS_FSL_QSPI_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #ifdef CONFIG_FSL_IFC
-	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+	{ CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
-	  CONFIG_SYS_FSL_IFC_SIZE,
+	  CFG_SYS_FSL_IFC_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
 #endif
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+	{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1,
+	  CFG_SYS_FSL_DRAM_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+	{ CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
-	  CONFIG_SYS_FSL_QBMAN_SIZE,
+	  CFG_SYS_FSL_QBMAN_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+	{ CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2,
+	  CFG_SYS_FSL_DRAM_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
@@ -385,8 +385,8 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #endif
-	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+	{ CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
-	  CONFIG_SYS_FSL_DRAM_SIZE3,
+	  CFG_SYS_FSL_DRAM_SIZE3,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
@@ -536,13 +536,13 @@ static inline void final_mmu_setup(void)
 		 * table.
 		 */
 		switch (final_map[index].virt) {
-		case CONFIG_SYS_FSL_DRAM_BASE1:
+		case CFG_SYS_FSL_DRAM_BASE1:
 			final_map[index].virt = gd->bd->bi_dram[0].start;
 			final_map[index].phys = gd->bd->bi_dram[0].start;
 			final_map[index].size = gd->bd->bi_dram[0].size;
 			break;
-#ifdef CONFIG_SYS_FSL_DRAM_BASE2
+#ifdef CFG_SYS_FSL_DRAM_BASE2
-		case CONFIG_SYS_FSL_DRAM_BASE2:
+		case CFG_SYS_FSL_DRAM_BASE2:
 #if (CONFIG_NR_DRAM_BANKS >= 2)
 			final_map[index].virt = gd->bd->bi_dram[1].start;
 			final_map[index].phys = gd->bd->bi_dram[1].start;
@@ -552,8 +552,8 @@ static inline void final_mmu_setup(void)
 #endif
 		break;
 #endif
-#ifdef CONFIG_SYS_FSL_DRAM_BASE3
+#ifdef CFG_SYS_FSL_DRAM_BASE3
-		case CONFIG_SYS_FSL_DRAM_BASE3:
+		case CFG_SYS_FSL_DRAM_BASE3:
 #if (CONFIG_NR_DRAM_BANKS >= 3)
 			final_map[index].virt = gd->bd->bi_dram[2].start;
 			final_map[index].phys = gd->bd->bi_dram[2].start;
@@ -1566,7 +1566,7 @@ void update_early_mmu_table(void)
 	if (!gd->arch.tlb_addr)
 		return;
 
-	if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
+	if (gd->ram_size <= CFG_SYS_FSL_DRAM_SIZE1) {
 		mmu_change_region_attr(
 					CFG_SYS_SDRAM_BASE,
 					gd->ram_size,

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -48,10 +48,11 @@ void get_sys_info(struct sys_info *sys_info)
 	unsigned long cluster_clk;
 
 	sys_info->freq_systembus = sysclk;
-#ifndef CONFIG_CLUSTER_CLK_FREQ
+#ifdef CONFIG_CLUSTER_CLK_FREQ
-#define CONFIG_CLUSTER_CLK_FREQ	get_board_sys_clk()
-#endif
 	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
+#else
+	cluster_clk = get_board_sys_clk();
+#endif
 
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
 	sys_info->freq_ddrbus = get_board_ddr_clk();

arch/arm/cpu/armv8/u-boot.lds

@@ -51,10 +51,12 @@ SECTIONS
 	}
 
 #ifndef CONFIG_ARMV8_SECURE_BASE
-#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_SECURE_BASE
 #define __ARMV8_PSCI_STACK_IN_RAM
+#else
+#define __ARMV8_SECURE_BASE	CONFIG_ARMV8_SECURE_BASE
 #endif
-	.secure_text CONFIG_ARMV8_SECURE_BASE :
+	.secure_text __ARMV8_SECURE_BASE :
 		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
 	{
 		*(._secure.text)

arch/arm/cpu/u-boot.lds

@@ -77,11 +77,13 @@ SECTIONS
 	}
 
 #ifndef CONFIG_ARMV7_SECURE_BASE
-#define CONFIG_ARMV7_SECURE_BASE
+#define __ARMV7_SECURE_BASE
 #define __ARMV7_PSCI_STACK_IN_RAM
+#else
+#define __ARMV7_SECURE_BASE	CONFIG_ARMV7_SECURE_BASE
 #endif
 
-	.secure_text CONFIG_ARMV7_SECURE_BASE :
+	.secure_text __ARMV7_SECURE_BASE :
 		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
 	{
 		*(._secure.text)

arch/arm/include/asm/arch-fsl-layerscape/cpu.h

@@ -8,32 +8,32 @@
 #define _FSL_LAYERSCAPE_CPU_H
 
 #ifdef CONFIG_FSL_LSCH3
-#define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
+#define CFG_SYS_FSL_CCSR_BASE	0x00000000
-#define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
+#define CFG_SYS_FSL_CCSR_SIZE	0x10000000
 #define CFG_SYS_FSL_QSPI_BASE1	0x20000000
-#define CONFIG_SYS_FSL_QSPI_SIZE1	0x10000000
+#define CFG_SYS_FSL_QSPI_SIZE1	0x10000000
 #ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_IFC_BASE1	0x30000000
+#define CFG_SYS_FSL_IFC_BASE1	0x30000000
-#define CONFIG_SYS_FSL_IFC_SIZE1	0x10000000
+#define CFG_SYS_FSL_IFC_SIZE1	0x10000000
-#define CONFIG_SYS_FSL_IFC_SIZE1_1	0x400000
+#define CFG_SYS_FSL_IFC_SIZE1_1	0x400000
 #endif
-#define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
+#define CFG_SYS_FSL_DRAM_BASE1	0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
+#define CFG_SYS_FSL_DRAM_SIZE1	0x80000000
 #define CFG_SYS_FSL_QSPI_BASE2	0x400000000
-#define CONFIG_SYS_FSL_QSPI_SIZE2	0x100000000
+#define CFG_SYS_FSL_QSPI_SIZE2	0x100000000
 #ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_IFC_BASE2	0x500000000
+#define CFG_SYS_FSL_IFC_BASE2	0x500000000
-#define CONFIG_SYS_FSL_IFC_SIZE2	0x100000000
+#define CFG_SYS_FSL_IFC_SIZE2	0x100000000
 #endif
-#define CONFIG_SYS_FSL_DCSR_BASE	0x700000000
+#define CFG_SYS_FSL_DCSR_BASE	0x700000000
-#define CONFIG_SYS_FSL_DCSR_SIZE	0x40000000
+#define CFG_SYS_FSL_DCSR_SIZE	0x40000000
-#define CONFIG_SYS_FSL_MC_BASE		0x80c000000
+#define CFG_SYS_FSL_MC_BASE		0x80c000000
-#define CONFIG_SYS_FSL_MC_SIZE		0x4000000
+#define CFG_SYS_FSL_MC_SIZE		0x4000000
-#define CONFIG_SYS_FSL_NI_BASE		0x810000000
+#define CFG_SYS_FSL_NI_BASE		0x810000000
-#define CONFIG_SYS_FSL_NI_SIZE		0x8000000
+#define CFG_SYS_FSL_NI_SIZE		0x8000000
-#define CONFIG_SYS_FSL_QBMAN_BASE	0x818000000
+#define CFG_SYS_FSL_QBMAN_BASE	0x818000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
+#define CFG_SYS_FSL_QBMAN_SIZE	0x8000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
+#define CFG_SYS_FSL_QBMAN_SIZE_1	0x4000000
 #ifdef CONFIG_ARCH_LS2080A
 #define CFG_SYS_PCIE1_PHYS_SIZE	0x200000000
 #define CFG_SYS_PCIE2_PHYS_SIZE	0x200000000
@@ -49,45 +49,45 @@
 #define SYS_PCIE5_PHYS_SIZE		0x800000000
 #define SYS_PCIE6_PHYS_SIZE		0x800000000
 #endif
-#define CONFIG_SYS_FSL_WRIOP1_BASE	0x4300000000
+#define CFG_SYS_FSL_WRIOP1_BASE	0x4300000000
-#define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
+#define CFG_SYS_FSL_WRIOP1_SIZE	0x100000000
-#define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
+#define CFG_SYS_FSL_AIOP1_BASE	0x4b00000000
-#define CONFIG_SYS_FSL_AIOP1_SIZE	0x100000000
+#define CFG_SYS_FSL_AIOP1_SIZE	0x100000000
 #if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
-#define CONFIG_SYS_FSL_PEBUF_BASE	0x4c00000000
+#define CFG_SYS_FSL_PEBUF_BASE	0x4c00000000
 #else
-#define CONFIG_SYS_FSL_PEBUF_BASE	0x1c00000000
+#define CFG_SYS_FSL_PEBUF_BASE	0x1c00000000
 #endif
-#define CONFIG_SYS_FSL_PEBUF_SIZE	0x400000000
+#define CFG_SYS_FSL_PEBUF_SIZE	0x400000000
 #ifdef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_DRAM_BASE2	0x2080000000
+#define CFG_SYS_FSL_DRAM_BASE2	0x2080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2	0x1F80000000
+#define CFG_SYS_FSL_DRAM_SIZE2	0x1F80000000
-#define CONFIG_SYS_FSL_DRAM_BASE3	0x6000000000
+#define CFG_SYS_FSL_DRAM_BASE3	0x6000000000
-#define CONFIG_SYS_FSL_DRAM_SIZE3	0x2000000000
+#define CFG_SYS_FSL_DRAM_SIZE3	0x2000000000
 #else
-#define CONFIG_SYS_FSL_DRAM_BASE2	0x8080000000
+#define CFG_SYS_FSL_DRAM_BASE2	0x8080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2	0x7F80000000
+#define CFG_SYS_FSL_DRAM_SIZE2	0x7F80000000
 #endif
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_CCSR_BASE	0x1000000
+#define CFG_SYS_FSL_CCSR_BASE	0x1000000
-#define CONFIG_SYS_FSL_CCSR_SIZE	0xf000000
+#define CFG_SYS_FSL_CCSR_SIZE	0xf000000
-#define CONFIG_SYS_FSL_DCSR_BASE	0x20000000
+#define CFG_SYS_FSL_DCSR_BASE	0x20000000
-#define CONFIG_SYS_FSL_DCSR_SIZE	0x4000000
+#define CFG_SYS_FSL_DCSR_SIZE	0x4000000
 #define CFG_SYS_FSL_QSPI_BASE	0x40000000
-#define CONFIG_SYS_FSL_QSPI_SIZE	0x20000000
+#define CFG_SYS_FSL_QSPI_SIZE	0x20000000
-#define CONFIG_SYS_FSL_IFC_BASE		0x60000000
+#define CFG_SYS_FSL_IFC_BASE		0x60000000
-#define CONFIG_SYS_FSL_IFC_SIZE		0x20000000
+#define CFG_SYS_FSL_IFC_SIZE		0x20000000
-#define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
+#define CFG_SYS_FSL_DRAM_BASE1	0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
+#define CFG_SYS_FSL_DRAM_SIZE1	0x80000000
-#define CONFIG_SYS_FSL_QBMAN_BASE	0x500000000
+#define CFG_SYS_FSL_QBMAN_BASE	0x500000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE	0x10000000
+#define CFG_SYS_FSL_QBMAN_SIZE	0x10000000
-#define CONFIG_SYS_FSL_DRAM_BASE2	0x880000000
+#define CFG_SYS_FSL_DRAM_BASE2	0x880000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
+#define CFG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
 #define CFG_SYS_PCIE1_PHYS_SIZE	0x800000000
 #define CFG_SYS_PCIE2_PHYS_SIZE	0x800000000
 #define CFG_SYS_PCIE3_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_FSL_DRAM_BASE3	0x8800000000
+#define CFG_SYS_FSL_DRAM_BASE3	0x8800000000
-#define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
+#define CFG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
 #endif
 
 int fsl_qoriq_core_to_cluster(unsigned int core);

arch/arm/include/asm/arch-rockchip/ddr_rk3288.h

@@ -360,7 +360,7 @@ check_member(rk3288_msch, devtodev, 0x003c);
 #define PCTL_STAT_MSK			7
 #define INIT_MEM			0
 #define CONFIG				1
-#define CONFIG_REQ			2
+#define CFG_REQ			2
 #define ACCESS				3
 #define ACCESS_REQ			4
 #define LOW_POWER			5

arch/arm/include/asm/arch-rockchip/sdram_rk322x.h

@@ -415,7 +415,7 @@ struct rk322x_base_params {
 #define PCTL_STAT_MASK			7
 #define INIT_MEM			0
 #define CONFIG				1
-#define CONFIG_REQ			2
+#define CFG_REQ			2
 #define ACCESS				3
 #define ACCESS_REQ			4
 #define LOW_POWER			5

arch/arm/include/asm/arch-sunxi/i2c.h

@@ -14,7 +14,7 @@
 #define CFG_I2C_MVTWSI_BASE1	SUNXI_TWI1_BASE
 #endif
 #ifdef CONFIG_R_I2C_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
+#define CFG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
 #endif
 
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */

arch/arm/lib/lib1funcs.S

@@ -15,12 +15,11 @@
 
 /*
  * U-Boot compatibility bit, define empty UNWIND() macro as, since we
- * do not support stack unwinding and define CONFIG_AEABI to make all
+ * do not support stack unwinding to make all of the functions available
- * of the functions available without diverging from Linux code.
+ * without diverging from Linux code.
  */
 #ifdef __UBOOT__
 #define UNWIND(x...)
-#define CONFIG_AEABI
 #endif
 
 .macro ARM_DIV_BODY dividend, divisor, result, curbit
@@ -314,8 +313,6 @@ UNWIND(.fnend)
 ENDPROC(__modsi3)
 .popsection
 
-#ifdef CONFIG_AEABI
-
 .pushsection .text.__aeabi_uidivmod, "ax"
 ENTRY(__aeabi_uidivmod)
 UNWIND(.fnstart)
@@ -348,8 +345,6 @@ UNWIND(.fnend)
 ENDPROC(__aeabi_idivmod)
 .popsection
 
-#endif
-
 .pushsection .text.Ldiv0, "ax"
 Ldiv0:
 UNWIND(.fnstart)

arch/arm/mach-at91/include/mach/at91rm9200.h

@@ -126,6 +126,4 @@
 #define ATMEL_PIO_PORTS		4	/* theese SoCs have 4 PIO */
 #define ATMEL_PMC_UHP		AT91RM9200_PMC_UHP
 
-#define CONFIG_SYS_ATMEL_CPU_NAME	"AT91RM9200"
-
 #endif

arch/arm/mach-omap2/fdt-common.c

@@ -17,8 +17,8 @@
 #ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
 #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
 #endif
-#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
+#ifndef CFG_SECURE_RUNTIME_RESV_SRAM_SZ
-#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#define CFG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
 #endif
 
 int ft_hs_disable_rng(void *fdt, struct bd_info *bd)

arch/arm/mach-omap2/omap5/fdt.c

@@ -19,8 +19,8 @@
 #ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
 #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
 #endif
-#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
+#ifndef CFG_SECURE_RUNTIME_RESV_SRAM_SZ
-#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#define CFG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
 #endif
 
 static u32 hs_irq_skip[] = {
@@ -92,7 +92,7 @@ static int ft_hs_fixup_crossbar(void *fdt, struct bd_info *bd)
 }
 
 #if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
-    (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
+    (CFG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
 static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd)
 {
 	const char *path;
@@ -116,7 +116,7 @@ static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd)
 	temp[0] = cpu_to_fdt32(0);
 	/* reservation size */
 	temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
-				   CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
+				   CFG_SECURE_RUNTIME_RESV_SRAM_SZ));
 	fdt_delprop(fdt, offs, "reg");
 	ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
 	if (ret < 0) {

arch/arm/mach-rmobile/include/mach/rcar-mstp.h

@@ -22,78 +22,78 @@
 #define mstp_setclrbits_le32(addr, set, clear) \
 		mstp_setclrbits(le32, addr, set, clear)
 
-#ifndef CONFIG_SMSTP0_ENA
+#ifndef CFG_SMSTP0_ENA
-#define CONFIG_SMSTP0_ENA	0x00
+#define CFG_SMSTP0_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP1_ENA
+#ifndef CFG_SMSTP1_ENA
-#define CONFIG_SMSTP1_ENA	0x00
+#define CFG_SMSTP1_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP2_ENA
+#ifndef CFG_SMSTP2_ENA
-#define CONFIG_SMSTP2_ENA	0x00
+#define CFG_SMSTP2_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP3_ENA
+#ifndef CFG_SMSTP3_ENA
-#define CONFIG_SMSTP3_ENA	0x00
+#define CFG_SMSTP3_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP4_ENA
+#ifndef CFG_SMSTP4_ENA
-#define CONFIG_SMSTP4_ENA	0x00
+#define CFG_SMSTP4_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP5_ENA
+#ifndef CFG_SMSTP5_ENA
-#define CONFIG_SMSTP5_ENA	0x00
+#define CFG_SMSTP5_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP6_ENA
+#ifndef CFG_SMSTP6_ENA
-#define CONFIG_SMSTP6_ENA	0x00
+#define CFG_SMSTP6_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP7_ENA
+#ifndef CFG_SMSTP7_ENA
-#define CONFIG_SMSTP7_ENA	0x00
+#define CFG_SMSTP7_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP8_ENA
+#ifndef CFG_SMSTP8_ENA
-#define CONFIG_SMSTP8_ENA	0x00
+#define CFG_SMSTP8_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP9_ENA
+#ifndef CFG_SMSTP9_ENA
-#define CONFIG_SMSTP9_ENA	0x00
+#define CFG_SMSTP9_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP10_ENA
+#ifndef CFG_SMSTP10_ENA
-#define CONFIG_SMSTP10_ENA	0x00
+#define CFG_SMSTP10_ENA	0x00
 #endif
-#ifndef CONFIG_SMSTP11_ENA
+#ifndef CFG_SMSTP11_ENA
-#define CONFIG_SMSTP11_ENA	0x00
+#define CFG_SMSTP11_ENA	0x00
 #endif
 
-#ifndef CONFIG_RMSTP0_ENA
+#ifndef CFG_RMSTP0_ENA
-#define CONFIG_RMSTP0_ENA	0x00
+#define CFG_RMSTP0_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP1_ENA
+#ifndef CFG_RMSTP1_ENA
-#define CONFIG_RMSTP1_ENA	0x00
+#define CFG_RMSTP1_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP2_ENA
+#ifndef CFG_RMSTP2_ENA
-#define CONFIG_RMSTP2_ENA	0x00
+#define CFG_RMSTP2_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP3_ENA
+#ifndef CFG_RMSTP3_ENA
-#define CONFIG_RMSTP3_ENA	0x00
+#define CFG_RMSTP3_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP4_ENA
+#ifndef CFG_RMSTP4_ENA
-#define CONFIG_RMSTP4_ENA	0x00
+#define CFG_RMSTP4_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP5_ENA
+#ifndef CFG_RMSTP5_ENA
-#define CONFIG_RMSTP5_ENA	0x00
+#define CFG_RMSTP5_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP6_ENA
+#ifndef CFG_RMSTP6_ENA
-#define CONFIG_RMSTP6_ENA	0x00
+#define CFG_RMSTP6_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP7_ENA
+#ifndef CFG_RMSTP7_ENA
-#define CONFIG_RMSTP7_ENA	0x00
+#define CFG_RMSTP7_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP8_ENA
+#ifndef CFG_RMSTP8_ENA
-#define CONFIG_RMSTP8_ENA	0x00
+#define CFG_RMSTP8_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP9_ENA
+#ifndef CFG_RMSTP9_ENA
-#define CONFIG_RMSTP9_ENA	0x00
+#define CFG_RMSTP9_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP10_ENA
+#ifndef CFG_RMSTP10_ENA
-#define CONFIG_RMSTP10_ENA	0x00
+#define CFG_RMSTP10_ENA	0x00
 #endif
-#ifndef CONFIG_RMSTP11_ENA
+#ifndef CFG_RMSTP11_ENA
-#define CONFIG_RMSTP11_ENA	0x00
+#define CFG_RMSTP11_ENA	0x00
 #endif
 
 struct mstp_ctl {

arch/arm/mach-rockchip/rk3036/sdram_rk3036.c

@@ -198,7 +198,7 @@ enum {
 	/* PCTL_STAT */
 	INIT_MEM			= 0,
 	CONFIG,
-	CONFIG_REQ,
+	CFG_REQ,
 	ACCESS,
 	ACCESS_REQ,
 	LOW_POWER,

arch/arm/mach-tegra/tegra20/warmboot_avp.c

@@ -34,7 +34,7 @@ void wb_start(void)
 	u32 reg;
 
 	/* enable JTAG & TBE */
-	writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
+	writel(CFG_CTL_TBE | CFG_CTL_JTAG, &apb_misc->cfg_ctl);
 
 	/* Are we running where we're supposed to be? */
 	asm volatile (

arch/arm/mach-tegra/tegra20/warmboot_avp.h

@@ -19,8 +19,8 @@
 
 #define USEC_CFG_DIVISOR_MASK		0xffff
 
-#define CONFIG_CTL_TBE			(1 << 7)
+#define CFG_CTL_TBE			(1 << 7)
-#define CONFIG_CTL_JTAG			(1 << 6)
+#define CFG_CTL_JTAG			(1 << 6)
 
 #define CPU_RST				(1 << 0)
 #define CLK_ENB_CPU			(1 << 0)

arch/m68k/cpu/mcf523x/interrupts.c

@@ -13,7 +13,7 @@
 
 int interrupt_init(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 	setbits_be32(&intp->imrl0, 0x1);
@@ -25,10 +25,10 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
-	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
 	clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
-	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
+	clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
 }
 #endif

arch/m68k/cpu/mcf52x2/interrupts.c

@@ -37,10 +37,10 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+	intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
 
 	clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
-	setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
+	setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
@@ -49,7 +49,7 @@ void dtimer_intr_setup(void)
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 #if defined(CONFIG_M5208)
@@ -66,11 +66,11 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
-	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
 	clrbits_be32(&intp->imrl0, 0x00000001);
-	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
+	clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
@@ -87,7 +87,7 @@ int interrupt_init(void)
 void dtimer_intr_setup(void)
 {
 	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
-	mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
+	mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */

arch/m68k/cpu/mcf530x/interrupts.c

@@ -24,6 +24,6 @@ void dtimer_intr_setup(void)
 	/* clearing TIMER2 mask, so enabling the related interrupt */
 	out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400);
 	/* set TIMER2 interrupt priority */
-	out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI);
+	out_8(&icr->icr2, CFG_SYS_TMRINTR_PRI);
 }
 #endif

arch/m68k/cpu/mcf532x/interrupts.c

@@ -13,7 +13,7 @@
 
 int interrupt_init(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 	setbits_be32(&intp->imrh0, 0xffffffff);
@@ -26,9 +26,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
-	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
-	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+	clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK);
 }
 #endif

arch/m68k/cpu/mcf5445x/interrupts.c

@@ -16,7 +16,7 @@
 
 int interrupt_init(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 	setbits_be32(&intp->imrh0, 0xffffffff);
@@ -29,9 +29,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
-	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
-	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+	clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK);
 }
 #endif

arch/m68k/include/asm/cache.h

@@ -11,21 +11,21 @@
 
 #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
     defined(CONFIG_MCF52x2)
-#define CONFIG_CF_V2
+#define CFG_CF_V2
 #endif
 
 #if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
     defined(CONFIG_MCF5301x)
-#define CONFIG_CF_V3
+#define CFG_CF_V3
 #endif
 
 #if defined(CONFIG_MCF5441x)
-#define CONFIG_CF_V4E		/* Four Extra ACRn */
+#define CFG_CF_V4E		/* Four Extra ACRn */
 #endif
 
 /* ***** CACR ***** */
 /* V2 Core */
-#ifdef CONFIG_CF_V2
+#ifdef CFG_CF_V2
 
 #define CF_CACR_CENB		(1 << 31)
 #define CF_CACR_CPD		(1 << 28)
@@ -46,10 +46,10 @@
 #define CF_CACR_EUSP		(1 << 4)
 #endif				/* CONFIG_MCF5249 || CONFIG_MCF5253 */
 
-#endif				/* CONFIG_CF_V2 */
+#endif				/* CFG_CF_V2 */
 
 /* V3 Core */
-#ifdef CONFIG_CF_V3
+#ifdef CFG_CF_V3
 
 #define CF_CACR_EC		(1 << 31)
 #define CF_CACR_ESB		(1 << 29)
@@ -65,10 +65,10 @@
 #define CF_CACR_DW		(1 << 5)
 #define CF_CACR_EUSP		(1 << 4)
 
-#endif				/* CONFIG_CF_V3 */
+#endif				/* CFG_CF_V3 */
 
 /* V4 Core */
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 
 #define CF_CACR_DEC		(1 << 31)
 #define CF_CACR_DW		(1 << 30)
@@ -116,7 +116,7 @@
 #define CF_ACR_WP		(1 << 2)
 
 /* V2 Core */
-#ifdef CONFIG_CF_V2
+#ifdef CFG_CF_V2
 #define CF_ACR_CM		(1 << 6)
 #define CF_ACR_BWE		(1 << 5)
 #else
@@ -126,10 +126,10 @@
 #define CF_ACR_CM_CB		(1 << 5)
 #define CF_ACR_CM_P		(2 << 5)
 #define CF_ACR_CM_IP		(3 << 5)
-#endif				/* CONFIG_CF_V2 */
+#endif				/* CFG_CF_V2 */
 
 /* V4 Core */
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 #define CF_ACR_AMM		(1 << 10)
 #define CF_ACR_SP		(1 << 3)
 #endif				/* CONFIG_CF_V4 */
@@ -159,24 +159,24 @@
 #define CFG_SYS_CACHE_ACR2	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR3
+#ifndef CFG_SYS_CACHE_ACR3
-#define CONFIG_SYS_CACHE_ACR3	0
+#define CFG_SYS_CACHE_ACR3	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR4
+#ifndef CFG_SYS_CACHE_ACR4
-#define CONFIG_SYS_CACHE_ACR4	0
+#define CFG_SYS_CACHE_ACR4	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR5
+#ifndef CFG_SYS_CACHE_ACR5
-#define CONFIG_SYS_CACHE_ACR5	0
+#define CFG_SYS_CACHE_ACR5	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR6
+#ifndef CFG_SYS_CACHE_ACR6
-#define CONFIG_SYS_CACHE_ACR6	0
+#define CFG_SYS_CACHE_ACR6	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR7
+#ifndef CFG_SYS_CACHE_ACR7
-#define CONFIG_SYS_CACHE_ACR7	0
+#define CFG_SYS_CACHE_ACR7	0
 #endif
 
 #define CF_ADDRMASK(x)		(((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)

arch/m68k/include/asm/coldfire/intctrl.h

@@ -12,7 +12,7 @@
 #if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
     defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
     defined(CONFIG_M547x)
-#	define	CONFIG_SYS_CF_INTC_REG1
+#	define	CFG_SYS_CF_INTC_REG1
 #endif
 
 typedef struct int0_ctrl {
@@ -23,7 +23,7 @@ typedef struct int0_ctrl {
 	u32 imrl0;		/* 0x0C Mask Low */
 	u32 frch0;		/* 0x10 Force High */
 	u32 frcl0;		/* 0x14 Force Low */
-#if defined(CONFIG_SYS_CF_INTC_REG1)
+#if defined(CFG_SYS_CF_INTC_REG1)
 	u8 irlr;		/* 0x18 */
 	u8 iacklpr;		/* 0x19 */
 	u16 res1[19];		/* 0x1a - 0x3c */
@@ -64,7 +64,7 @@ typedef struct int1_ctrl {
 	u32 imrl1;		/* 0x0C Mask Low */
 	u32 frch1;		/* 0x10 Force High */
 	u32 frcl1;		/* 0x14 Force Low */
-#if defined(CONFIG_SYS_CF_INTC_REG1)
+#if defined(CFG_SYS_CF_INTC_REG1)
 	u8 irlr;		/* 0x18 */
 	u8 iacklpr;		/* 0x19 */
 	u16 res1[19];		/* 0x1a - 0x3c */
@@ -192,7 +192,7 @@ typedef struct intgack_ctrl1 {
 #define INTC_IACKLPR_PRI(x)		((x) & 0x0F)
 #define INTC_IACKLPR_PRI_MASK		(0xF0)
 
-#if defined(CONFIG_SYS_CF_INTC_REG1)
+#if defined(CFG_SYS_CF_INTC_REG1)
 #define INTC_ICR_IL(x)			(((x) & 0x07) << 3)
 #define INTC_ICR_IL_MASK		(0xC7)
 #define INTC_ICR_IP(x)			((x) & 0x07)

arch/m68k/include/asm/immap.h

@@ -13,67 +13,65 @@
 #include <asm/immap_520x.h>
 #include <asm/m520x.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND		(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CFG_SYS_TMRINTR_PRI		(6)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M520x */
 
 #ifdef CONFIG_M5235
 #include <asm/immap_5235.h>
 #include <asm/m5235.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CFG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5235 */
 
 #ifdef CONFIG_M5249
 #include <asm/immap_5249.h>
 #include <asm/m5249.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS		(64)
+#define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CFG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
-#define CONFIG_SYS_TMRINTR_NO		(31)
+#define CFG_SYS_TMRINTR_NO		(31)
-#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
+#define CFG_SYS_TMRINTR_MASK	(0x00000400)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CFG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5249 */
 
@@ -82,21 +80,21 @@
 #include <asm/m5249.h>
 #include <asm/m5253.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS		(64)
+#define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CFG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
-#define CONFIG_SYS_TMRINTR_NO		(27)
+#define CFG_SYS_TMRINTR_NO		(27)
-#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
+#define CFG_SYS_TMRINTR_MASK	(0x00000400)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
+#define CFG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5253 */
 
@@ -104,45 +102,43 @@
 #include <asm/immap_5271.h>
 #include <asm/m5271.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E) /* Interrupt level 3, priority 6 */
+#define CFG_SYS_TMRINTR_PRI		(0x1E) /* Interrupt level 3, priority 6 */
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5271 */
 
 #ifdef CONFIG_M5272
 #include <asm/immap_5272.h>
 #include <asm/m5272.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS		(64)
+#define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_TMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_TMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_TMR3)
+#define CFG_SYS_TMR_BASE		(MMAP_TMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
+#define CFG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
-#define CONFIG_SYS_TMRINTR_NO		(INT_TMR3)
+#define CFG_SYS_TMRINTR_NO		(INT_TMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(INT_ISR_INT24)
+#define CFG_SYS_TMRINTR_MASK	(INT_ISR_INT24)
-#define CONFIG_SYS_TMRINTR_PEND	(0)
+#define CFG_SYS_TMRINTR_PEND	(0)
-#define CONFIG_SYS_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
+#define CFG_SYS_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5272 */
 
@@ -150,23 +146,21 @@
 #include <asm/immap_5275.h>
 #include <asm/m5275.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(192)
+#define CFG_SYS_NUM_IRQS		(192)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
+#define CFG_SYS_TMRINTR_PRI		(0x1E)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5275 */
 
@@ -174,22 +168,21 @@
 #include <asm/immap_5282.h>
 #include <asm/m5282.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_NUM_IRQS		(128)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CFG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5282 */
 
@@ -197,23 +190,23 @@
 #include <asm/immap_5307.h>
 #include <asm/m5307.h>
 
-#define CONFIG_SYS_UART_BASE            (MMAP_UART0 + \
+#define CFG_SYS_UART_BASE            (MMAP_UART0 + \
 					(CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_INTR_BASE            (MMAP_INTC)
+#define CFG_SYS_INTR_BASE            (MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS             (64)
+#define CFG_SYS_NUM_IRQS             (64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE          (MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE          (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE             (MMAP_DTMR1)
+#define CFG_SYS_TMR_BASE             (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *) \
+#define CFG_SYS_TMRPND_REG		(((volatile intctrl_t *) \
-					(CONFIG_SYS_INTR_BASE))->ipr)
+					(CFG_SYS_INTR_BASE))->ipr)
-#define CONFIG_SYS_TMRINTR_NO           (31)
+#define CFG_SYS_TMRINTR_NO           (31)
-#define CONFIG_SYS_TMRINTR_MASK		(0x00000400)
+#define CFG_SYS_TMRINTR_MASK		(0x00000400)
-#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND		(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI          (MCFSIM_ICR_AUTOVEC | \
+#define CFG_SYS_TMRINTR_PRI          (MCFSIM_ICR_AUTOVEC | \
 					MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
-#define CONFIG_SYS_TIMER_PRESCALER      (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER      (((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif                          /* CONFIG_M5307 */
 
@@ -221,61 +214,55 @@
 #include <asm/immap_5301x.h>
 #include <asm/m5301x.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
-#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND		(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CFG_SYS_TMRINTR_PRI		(6)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5301x */
 
 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
 #include <asm/immap_5329.h>
 #include <asm/m5329.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CFG_SYS_TMRINTR_PRI		(6)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5329 && CONFIG_M5373 */
 
 #if defined(CONFIG_M54418)
 #include <asm/immap_5441x.h>
 #include <asm/m5441x.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
-#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-
 #if (CFG_SYS_UART_PORT < 4)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + \
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + \
 					(CFG_SYS_UART_PORT * 0x4000))
 #else
-#define CONFIG_SYS_UART_BASE		(MMAP_UART4 + \
+#define CFG_SYS_UART_BASE		(MMAP_UART4 + \
 					((CFG_SYS_UART_PORT - 4) * 0x4000))
 #endif
 
@@ -283,18 +270,18 @@
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG	(((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRPND_REG	(((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND		(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CFG_SYS_TMRINTR_PRI		(6)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(192)
+#define CFG_SYS_NUM_IRQS		(192)
 
 #endif				/* CONFIG_M54418 */
 
@@ -303,9 +290,6 @@
 #include <asm/m547x_8x.h>
 
 #ifdef CONFIG_FSLDMAFEC
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
-#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-
 #define FEC0_RX_TASK		0
 #define FEC0_TX_TASK		1
 #define FEC0_RX_PRIORITY	6
@@ -320,21 +304,21 @@
 #define FEC1_TX_INIT		31
 #endif
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
 
 #ifdef CONFIG_SLTTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
+#define CFG_SYS_UDELAY_BASE		(MMAP_SLT1)
-#define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
+#define CFG_SYS_TMR_BASE		(MMAP_SLT0)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
+#define CFG_SYS_TMRINTR_PRI		(0x1E)
-#define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#define CFG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_NUM_IRQS		(128)
 
 #ifdef CONFIG_PCI
 #define CFG_SYS_PCI_BAR0		(0x40000000)

arch/m68k/lib/cache.c

@@ -33,12 +33,12 @@ void icache_enable(void)
 
 	*cf_icache_status = 1;
 
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2));
-	__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
+	__asm__ __volatile__("movec %0, %%acr3"::"r"(CFG_SYS_CACHE_ACR3));
-#if defined(CONFIG_CF_V4E)
+#if defined(CFG_CF_V4E)
-	__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
+	__asm__ __volatile__("movec %0, %%acr6"::"r"(CFG_SYS_CACHE_ACR6));
-	__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
+	__asm__ __volatile__("movec %0, %%acr7"::"r"(CFG_SYS_CACHE_ACR7));
 #endif
 #else
 	__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
@@ -55,10 +55,10 @@ void icache_disable(void)
 	*cf_icache_status = 0;
 	icache_invalid();
 
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
 	__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
-#if defined(CONFIG_CF_V4E)
+#if defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
 	__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
 #endif
@@ -88,12 +88,12 @@ void dcache_enable(void)
 	dcache_invalid();
 	*cf_dcache_status = 1;
 
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
 	__asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
-#if defined(CONFIG_CF_V4E)
+#if defined(CFG_CF_V4E)
-	__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
+	__asm__ __volatile__("movec %0, %%acr4"::"r"(CFG_SYS_CACHE_ACR4));
-	__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
+	__asm__ __volatile__("movec %0, %%acr5"::"r"(CFG_SYS_CACHE_ACR5));
 #endif
 #endif
 
@@ -109,10 +109,10 @@ void dcache_disable(void)
 
 	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
 
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
 	__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
-#if defined(CONFIG_CF_V4E)
+#if defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
 	__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
 #endif
@@ -121,7 +121,7 @@ void dcache_disable(void)
 
 void dcache_invalid(void)
 {
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	u32 temp;
 
 	temp = CFG_SYS_DCACHE_INV;

arch/m68k/lib/interrupts.c

@@ -14,7 +14,7 @@
 #include <asm/immap.h>
 #include <asm/ptrace.h>
 
-#define	NR_IRQS		(CONFIG_SYS_NUM_IRQS)
+#define	NR_IRQS		(CFG_SYS_NUM_IRQS)
 
 /*
  * Interrupt vector functions.

arch/m68k/lib/time.c

@@ -21,23 +21,23 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static volatile ulong timestamp = 0;
 
-#ifndef CONFIG_SYS_WATCHDOG_FREQ
+#ifndef CFG_SYS_WATCHDOG_FREQ
-#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
+#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
 #endif
 
 #if defined(CONFIG_MCFTMR)
-#ifndef CONFIG_SYS_UDELAY_BASE
+#ifndef CFG_SYS_UDELAY_BASE
 #	error	"uDelay base not defined!"
 #endif
 
-#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
+#if !defined(CFG_SYS_TMR_BASE) || !defined(CFG_SYS_INTR_BASE) || !defined(CFG_SYS_TMRINTR_NO) || !defined(CFG_SYS_TMRINTR_MASK)
 #	error	"TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
 #endif
 extern void dtimer_intr_setup(void);
 
 void __udelay(unsigned long usec)
 {
-	volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
+	volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_UDELAY_BASE);
 	uint start, now, tmp;
 
 	while (usec > 0) {
@@ -52,7 +52,7 @@ void __udelay(unsigned long usec)
 		timerp->tcn = 0;
 		/* set period to 1 us */
 		timerp->tmr =
-		    CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
+		    CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
 		    DTIM_DTMR_RST_EN;
 
 		start = now = timerp->tcn;
@@ -63,15 +63,15 @@ void __udelay(unsigned long usec)
 
 void dtimer_interrupt(void *not_used)
 {
-	volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
+	volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
 
 	/* check for timer interrupt asserted */
-	if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
+	if ((CFG_SYS_TMRPND_REG & CFG_SYS_TMRINTR_MASK) == CFG_SYS_TMRINTR_PEND) {
 		timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
 		timestamp++;
 
 		#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
-		if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
+		if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0) {
 			schedule();
 		}
 		#endif    /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
@@ -81,7 +81,7 @@ void dtimer_interrupt(void *not_used)
 
 int timer_init(void)
 {
-	volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
+	volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
 
 	timestamp = 0;
 
@@ -92,7 +92,7 @@ int timer_init(void)
 	timerp->tmr = DTIM_DTMR_RST_RST;
 
 	/* initialize and enable timer interrupt */
-	irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
+	irq_install_handler(CFG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
 
 	timerp->tcn = 0;
 	timerp->trr = 1000;	/* Interrupt every ms */
@@ -100,7 +100,7 @@ int timer_init(void)
 	dtimer_intr_setup();
 
 	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
-	timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
+	timerp->tmr = CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
 	    DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
 
 	return 0;

arch/mips/mach-mtmips/mt7621/spl/start.S

@@ -17,8 +17,8 @@
 #include "../mt7621.h"
 #include "dram.h"
 
-#ifndef CONFIG_SYS_INIT_SP_ADDR
+#ifndef CFG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_INIT_SP_ADDR	(CFG_SYS_SDRAM_BASE + \
+#define CFG_SYS_INIT_SP_ADDR	(CFG_SYS_SDRAM_BASE + \
 				CFG_SYS_INIT_SP_OFFSET)
 #endif
 
@@ -31,7 +31,7 @@
 
 	.macro setup_stack_gd
 	li	t0, -16
-	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
+	PTR_LI	t1, CFG_SYS_INIT_SP_ADDR
 	and	sp, t1, t0		# force 16 byte alignment
 	PTR_SUBU \
 		sp, sp, GD_SIZE		# reserve space for gd
@@ -201,7 +201,7 @@ ENTRY(_start)
 
 #if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
 	/* Set malloc base */
-	li	t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15)
+	li	t0, (CFG_SYS_INIT_SP_ADDR + 15) & (~15)
 	PTR_S	t0, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
 #endif
 

arch/powerpc/cpu/mpc83xx/bats/bats.h

@@ -1,223 +1,223 @@
 #ifdef CONFIG_BAT0
-#define CONFIG_SYS_IBAT0L (\
+#define CFG_SYS_IBAT0L (\
 		(CONFIG_BAT0_BASE) |\
 		(CONFIG_BAT0_PAGE_PROTECTION) |\
 		(CONFIG_BAT0_WIMG_ICACHE) \
 		)
-#define CONFIG_SYS_IBAT0U (\
+#define CFG_SYS_IBAT0U (\
 		(CONFIG_BAT0_BASE) |\
 		(CONFIG_BAT0_LENGTH) |\
 		(CONFIG_BAT0_VALID_BITS) \
 		)
-#define CONFIG_SYS_DBAT0L (\
+#define CFG_SYS_DBAT0L (\
 		(CONFIG_BAT0_BASE) |\
 		(CONFIG_BAT0_PAGE_PROTECTION) |\
 		(CONFIG_BAT0_WIMG_DCACHE) \
 		)
-#define CONFIG_SYS_DBAT0U (\
+#define CFG_SYS_DBAT0U (\
 		(CONFIG_BAT0_BASE) |\
 		(CONFIG_BAT0_LENGTH) |\
 		(CONFIG_BAT0_VALID_BITS) \
 		)
 #else
-#define CONFIG_SYS_IBAT0L (0)
+#define CFG_SYS_IBAT0L (0)
-#define CONFIG_SYS_IBAT0U (0)
+#define CFG_SYS_IBAT0U (0)
-#define CONFIG_SYS_DBAT0L (0)
+#define CFG_SYS_DBAT0L (0)
-#define CONFIG_SYS_DBAT0U (0)
+#define CFG_SYS_DBAT0U (0)
 #endif /* CONFIG_BAT0 */
 
 #ifdef CONFIG_BAT1
-#define CONFIG_SYS_IBAT1L (\
+#define CFG_SYS_IBAT1L (\
 		(CONFIG_BAT1_BASE) |\
 		(CONFIG_BAT1_PAGE_PROTECTION) |\
 		(CONFIG_BAT1_WIMG_ICACHE) \
 		)
-#define CONFIG_SYS_IBAT1U (\
+#define CFG_SYS_IBAT1U (\
 		(CONFIG_BAT1_BASE) |\
 		(CONFIG_BAT1_LENGTH) |\
 		(CONFIG_BAT1_VALID_BITS) \
 		)
-#define CONFIG_SYS_DBAT1L (\
+#define CFG_SYS_DBAT1L (\
 		(CONFIG_BAT1_BASE) |\
 		(CONFIG_BAT1_PAGE_PROTECTION) |\
 		(CONFIG_BAT1_WIMG_DCACHE) \
 		)
-#define CONFIG_SYS_DBAT1U (\
+#define CFG_SYS_DBAT1U (\
 		(CONFIG_BAT1_BASE) |\
 		(CONFIG_BAT1_LENGTH) |\
 		(CONFIG_BAT1_VALID_BITS) \
 		)
 #else
-#define CONFIG_SYS_IBAT1L (0)
+#define CFG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
+#define CFG_SYS_IBAT1U (0)
-#define CONFIG_SYS_DBAT1L (0)
+#define CFG_SYS_DBAT1L (0)
-#define CONFIG_SYS_DBAT1U (0)
+#define CFG_SYS_DBAT1U (0)
 #endif /* CONFIG_BAT1 */
 
 #ifdef CONFIG_BAT2
-#define CONFIG_SYS_IBAT2L (\
+#define CFG_SYS_IBAT2L (\
 		(CONFIG_BAT2_BASE) |\
 		(CONFIG_BAT2_PAGE_PROTECTION) |\
 		(CONFIG_BAT2_WIMG_ICACHE) \
 		)
-#define CONFIG_SYS_IBAT2U (\
+#define CFG_SYS_IBAT2U (\
 		(CONFIG_BAT2_BASE) |\
 		(CONFIG_BAT2_LENGTH) |\
 		(CONFIG_BAT2_VALID_BITS) \
 		)
-#define CONFIG_SYS_DBAT2L (\
+#define CFG_SYS_DBAT2L (\
 		(CONFIG_BAT2_BASE) |\
 		(CONFIG_BAT2_PAGE_PROTECTION) |\
 		(CONFIG_BAT2_WIMG_DCACHE) \
 		)
-#define CONFIG_SYS_DBAT2U (\
+#define CFG_SYS_DBAT2U (\
 		(CONFIG_BAT2_BASE) |\
 		(CONFIG_BAT2_LENGTH) |\
 		(CONFIG_BAT2_VALID_BITS) \
 		)
 #else
-#define CONFIG_SYS_IBAT2L (0)
+#define CFG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
+#define CFG_SYS_IBAT2U (0)
-#define CONFIG_SYS_DBAT2L (0)
+#define CFG_SYS_DBAT2L (0)
-#define CONFIG_SYS_DBAT2U (0)
+#define CFG_SYS_DBAT2U (0)
 #endif /* CONFIG_BAT2 */
 
 #ifdef CONFIG_BAT3
-#define CONFIG_SYS_IBAT3L (\
+#define CFG_SYS_IBAT3L (\
 		(CONFIG_BAT3_BASE) |\
 		(CONFIG_BAT3_PAGE_PROTECTION) |\
 		(CONFIG_BAT3_WIMG_ICACHE) \
 		)
-#define CONFIG_SYS_IBAT3U (\
+#define CFG_SYS_IBAT3U (\
 		(CONFIG_BAT3_BASE) |\
 		(CONFIG_BAT3_LENGTH) |\
 		(CONFIG_BAT3_VALID_BITS) \
 		)
-#define CONFIG_SYS_DBAT3L (\
+#define CFG_SYS_DBAT3L (\
 		(CONFIG_BAT3_BASE) |\
 		(CONFIG_BAT3_PAGE_PROTECTION) |\
 		(CONFIG_BAT3_WIMG_DCACHE) \
 		)
-#define CONFIG_SYS_DBAT3U (\
+#define CFG_SYS_DBAT3U (\
 		(CONFIG_BAT3_BASE) |\
 		(CONFIG_BAT3_LENGTH) |\
 		(CONFIG_BAT3_VALID_BITS) \
 		)
 #else
-#define CONFIG_SYS_IBAT3L (0)
+#define CFG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
+#define CFG_SYS_IBAT3U (0)
-#define CONFIG_SYS_DBAT3L (0)
+#define CFG_SYS_DBAT3L (0)
-#define CONFIG_SYS_DBAT3U (0)
+#define CFG_SYS_DBAT3U (0)
 #endif /* CONFIG_BAT3 */
 
 #ifdef CONFIG_BAT4
-#define CONFIG_SYS_IBAT4L (\
+#define CFG_SYS_IBAT4L (\
 		(CONFIG_BAT4_BASE) |\
 		(CONFIG_BAT4_PAGE_PROTECTION) |\
 		(CONFIG_BAT4_WIMG_ICACHE) \
 		)
-#define CONFIG_SYS_IBAT4U (\
+#define CFG_SYS_IBAT4U (\
 		(CONFIG_BAT4_BASE) |\
 		(CONFIG_BAT4_LENGTH) |\
 		(CONFIG_BAT4_VALID_BITS) \
 		)
-#define CONFIG_SYS_DBAT4L (\
+#define CFG_SYS_DBAT4L (\
 		(CONFIG_BAT4_BASE) |\
 		(CONFIG_BAT4_PAGE_PROTECTION) |\
 		(CONFIG_BAT4_WIMG_DCACHE) \
 		)
-#define CONFIG_SYS_DBAT4U (\
+#define CFG_SYS_DBAT4U (\
 		(CONFIG_BAT4_BASE) |\
 		(CONFIG_BAT4_LENGTH) |\
 		(CONFIG_BAT4_VALID_BITS) \
 		)
 #else
-#define CONFIG_SYS_IBAT4L (0)
+#define CFG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
+#define CFG_SYS_IBAT4U (0)
-#define CONFIG_SYS_DBAT4L (0)
+#define CFG_SYS_DBAT4L (0)
-#define CONFIG_SYS_DBAT4U (0)
+#define CFG_SYS_DBAT4U (0)
 #endif /* CONFIG_BAT4 */
 
 #ifdef CONFIG_BAT5
-#define CONFIG_SYS_IBAT5L (\
+#define CFG_SYS_IBAT5L (\
 		(CONFIG_BAT5_BASE) |\
 		(CONFIG_BAT5_PAGE_PROTECTION) |\
 		(CONFIG_BAT5_WIMG_ICACHE) \
 		)
-#define CONFIG_SYS_IBAT5U (\
+#define CFG_SYS_IBAT5U (\
 		(CONFIG_BAT5_BASE) |\
 		(CONFIG_BAT5_LENGTH) |\
 		(CONFIG_BAT5_VALID_BITS) \
 		)
-#define CONFIG_SYS_DBAT5L (\
+#define CFG_SYS_DBAT5L (\
 		(CONFIG_BAT5_BASE) |\
 		(CONFIG_BAT5_PAGE_PROTECTION) |\
 		(CONFIG_BAT5_WIMG_DCACHE) \
 		)
-#define CONFIG_SYS_DBAT5U (\
+#define CFG_SYS_DBAT5U (\
 		(CONFIG_BAT5_BASE) |\
 		(CONFIG_BAT5_LENGTH) |\
 		(CONFIG_BAT5_VALID_BITS) \
 		)
 #else
-#define CONFIG_SYS_IBAT5L (0)
+#define CFG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
+#define CFG_SYS_IBAT5U (0)
-#define CONFIG_SYS_DBAT5L (0)
+#define CFG_SYS_DBAT5L (0)
-#define CONFIG_SYS_DBAT5U (0)
+#define CFG_SYS_DBAT5U (0)
 #endif /* CONFIG_BAT5 */
 
 #ifdef CONFIG_BAT6
-#define CONFIG_SYS_IBAT6L (\
+#define CFG_SYS_IBAT6L (\
 		(CONFIG_BAT6_BASE) |\
 		(CONFIG_BAT6_PAGE_PROTECTION) |\
 		(CONFIG_BAT6_WIMG_ICACHE) \
 		)
-#define CONFIG_SYS_IBAT6U (\
+#define CFG_SYS_IBAT6U (\
 		(CONFIG_BAT6_BASE) |\
 		(CONFIG_BAT6_LENGTH) |\
 		(CONFIG_BAT6_VALID_BITS) \
 		)
-#define CONFIG_SYS_DBAT6L (\
+#define CFG_SYS_DBAT6L (\
 		(CONFIG_BAT6_BASE) |\
 		(CONFIG_BAT6_PAGE_PROTECTION) |\
 		(CONFIG_BAT6_WIMG_DCACHE) \
 		)
-#define CONFIG_SYS_DBAT6U (\
+#define CFG_SYS_DBAT6U (\
 		(CONFIG_BAT6_BASE) |\
 		(CONFIG_BAT6_LENGTH) |\
 		(CONFIG_BAT6_VALID_BITS) \
 		)
 #else
-#define CONFIG_SYS_IBAT6L (0)
+#define CFG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
+#define CFG_SYS_IBAT6U (0)
-#define CONFIG_SYS_DBAT6L (0)
+#define CFG_SYS_DBAT6L (0)
-#define CONFIG_SYS_DBAT6U (0)
+#define CFG_SYS_DBAT6U (0)
 #endif /* CONFIG_BAT6 */
 
 #ifdef CONFIG_BAT7
-#define CONFIG_SYS_IBAT7L (\
+#define CFG_SYS_IBAT7L (\
 		(CONFIG_BAT7_BASE) |\
 		(CONFIG_BAT7_PAGE_PROTECTION) |\
 		(CONFIG_BAT7_WIMG_ICACHE) \
 		)
-#define CONFIG_SYS_IBAT7U (\
+#define CFG_SYS_IBAT7U (\
 		(CONFIG_BAT7_BASE) |\
 		(CONFIG_BAT7_LENGTH) |\
 		(CONFIG_BAT7_VALID_BITS) \
 		)
-#define CONFIG_SYS_DBAT7L (\
+#define CFG_SYS_DBAT7L (\
 		(CONFIG_BAT7_BASE) |\
 		(CONFIG_BAT7_PAGE_PROTECTION) |\
 		(CONFIG_BAT7_WIMG_DCACHE) \
 		)
-#define CONFIG_SYS_DBAT7U (\
+#define CFG_SYS_DBAT7U (\
 		(CONFIG_BAT7_BASE) |\
 		(CONFIG_BAT7_LENGTH) |\
 		(CONFIG_BAT7_VALID_BITS) \
 		)
 #else
-#define CONFIG_SYS_IBAT7L (0)
+#define CFG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
+#define CFG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L (0)
+#define CFG_SYS_DBAT7L (0)
-#define CONFIG_SYS_DBAT7U (0)
+#define CFG_SYS_DBAT7U (0)
 #endif /* CONFIG_BAT7 */

arch/powerpc/cpu/mpc83xx/cpu_init.c

@@ -208,24 +208,24 @@ void cpu_init_f (volatile immap_t * im)
 	init_early_memctl_regs();
 
 	/* Local Access window setup */
-#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
+#if defined(CFG_SYS_LBLAWBAR0_PRELIM) && defined(CFG_SYS_LBLAWAR0_PRELIM)
-	im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
+	im->sysconf.lblaw[0].bar = CFG_SYS_LBLAWBAR0_PRELIM;
-	im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
+	im->sysconf.lblaw[0].ar = CFG_SYS_LBLAWAR0_PRELIM;
 #else
-#error	CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
+#error	CFG_SYS_LBLAWBAR0_PRELIM & CFG_SYS_LBLAWAR0_PRELIM must be defined
 #endif
 
-#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
+#if defined(CFG_SYS_LBLAWBAR1_PRELIM) && defined(CFG_SYS_LBLAWAR1_PRELIM)
-	im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
+	im->sysconf.lblaw[1].bar = CFG_SYS_LBLAWBAR1_PRELIM;
-	im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
+	im->sysconf.lblaw[1].ar = CFG_SYS_LBLAWAR1_PRELIM;
 #endif
-#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+#if defined(CFG_SYS_LBLAWBAR2_PRELIM) && defined(CFG_SYS_LBLAWAR2_PRELIM)
-	im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
+	im->sysconf.lblaw[2].bar = CFG_SYS_LBLAWBAR2_PRELIM;
-	im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
+	im->sysconf.lblaw[2].ar = CFG_SYS_LBLAWAR2_PRELIM;
 #endif
-#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
+#if defined(CFG_SYS_LBLAWBAR3_PRELIM) && defined(CFG_SYS_LBLAWAR3_PRELIM)
-	im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
+	im->sysconf.lblaw[3].bar = CFG_SYS_LBLAWBAR3_PRELIM;
-	im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
+	im->sysconf.lblaw[3].ar = CFG_SYS_LBLAWAR3_PRELIM;
 #endif
 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 	im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;

arch/powerpc/cpu/mpc83xx/hid/hid.h

@@ -1,4 +1,4 @@
-#define CONFIG_SYS_HID0_FINAL ( \
+#define CFG_SYS_HID0_FINAL ( \
 	CONFIG_HID0_FINAL_ABE_BIT |\
 	CONFIG_HID0_FINAL_CLKOUT |\
 	CONFIG_HID0_FINAL_DCE_BIT |\
@@ -24,7 +24,7 @@
 	CONFIG_HID0_FINAL_SLEEP_BIT \
 )
 
-#define CONFIG_SYS_HID0_INIT ( \
+#define CFG_SYS_HID0_INIT ( \
 	CONFIG_HID0_INIT_ABE_BIT |\
 	CONFIG_HID0_INIT_CLKOUT |\
 	CONFIG_HID0_INIT_DCE_BIT |\
@@ -50,12 +50,12 @@
 
 #ifdef CONFIG_TARGET_IDS8313
 /* IDS8313 defines a reserved bit; keep to not break compatibility */
-#define CONFIG_HID2_SPECIAL 0x00020000
+#define CFG_HID2_SPECIAL 0x00020000
 #else
-#define CONFIG_HID2_SPECIAL 0x0
+#define CFG_HID2_SPECIAL 0x0
 #endif
 
-#define CONFIG_SYS_HID2 ( \
+#define CFG_SYS_HID2 ( \
 	CONFIG_HID2_LET_BIT |\
 	CONFIG_HID2_IFEB_BIT |\
 	CONFIG_HID2_MESISTATE_BIT |\
@@ -68,5 +68,5 @@
 	CONFIG_HID2_IWLCK |\
 	CONFIG_HID2_ICWP_BIT |\
 	CONFIG_HID2_DWLCK |\
-	CONFIG_HID2_SPECIAL \
+	CFG_HID2_SPECIAL \
 )

arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h

@@ -1,4 +1,4 @@
-#define CONFIG_SYS_HRCW_LOW (\
+#define CFG_SYS_HRCW_LOW (\
 	(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
 	(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
 	(CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\
@@ -9,7 +9,7 @@
 	(CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \
 	)
 
-#define CONFIG_SYS_HRCW_HIGH (\
+#define CFG_SYS_HRCW_HIGH (\
 	(CONFIG_PCI_HOST_MODE << (31 - 0)) |\
 	(CONFIG_PCI_64BIT_MODE << (31 - 1)) |\
 	(CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\

arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h

@@ -1,55 +1,55 @@
 #if defined(CONFIG_LBLAW0)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM \
+#define CFG_SYS_LBLAWBAR0_PRELIM \
 	CONFIG_LBLAW0_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (\
+#define CFG_SYS_LBLAWAR0_PRELIM (\
 	CONFIG_LBLAW0_ENABLE_BIT |\
 	CONFIG_LBLAW0_LENGTH \
 )
 #endif
 
 #if defined(CONFIG_LBLAW1)
-#define CONFIG_SYS_LBLAWBAR1_PRELIM \
+#define CFG_SYS_LBLAWBAR1_PRELIM \
 	CONFIG_LBLAW1_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (\
+#define CFG_SYS_LBLAWAR1_PRELIM (\
 	CONFIG_LBLAW1_ENABLE_BIT |\
 	CONFIG_LBLAW1_LENGTH \
 )
 #endif
 
 #if defined(CONFIG_LBLAW2)
-#define CONFIG_SYS_LBLAWBAR2_PRELIM \
+#define CFG_SYS_LBLAWBAR2_PRELIM \
 	CONFIG_LBLAW2_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (\
+#define CFG_SYS_LBLAWAR2_PRELIM (\
 	CONFIG_LBLAW2_ENABLE_BIT |\
 	CONFIG_LBLAW2_LENGTH \
 )
 #endif
 
 #if defined(CONFIG_LBLAW3)
-#define CONFIG_SYS_LBLAWBAR3_PRELIM \
+#define CFG_SYS_LBLAWBAR3_PRELIM \
 	CONFIG_LBLAW3_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (\
+#define CFG_SYS_LBLAWAR3_PRELIM (\
 	CONFIG_LBLAW3_ENABLE_BIT |\
 	CONFIG_LBLAW3_LENGTH \
 )
 #endif
 
 #ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
+#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR0_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
+#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR0_PRELIM
 #endif
 
 #ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR1_PRELIM
 #endif
 
 #ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM
+#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR2_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM
+#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR2_PRELIM
 #endif
 
 #ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM
+#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR3_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM
+#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR3_PRELIM
 #endif

arch/powerpc/cpu/mpc83xx/spd_sdram.c

@@ -66,8 +66,8 @@ void board_add_ram_info(int use_default)
 }
 
 #ifdef CONFIG_SPD_EEPROM
-#ifndef	CONFIG_SYS_READ_SPD
+#ifndef	CFG_SYS_READ_SPD
-#define CONFIG_SYS_READ_SPD	i2c_read
+#define CFG_SYS_READ_SPD	i2c_read
 #endif
 #ifndef SPD_EEPROM_OFFSET
 #define SPD_EEPROM_OFFSET	0
@@ -167,7 +167,7 @@ long int spd_sdram()
 	isync();
 
 	/* Read SPD parameters with I2C */
-	CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
+	CFG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
 		SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
 #ifdef SPD_DEBUG
 	spd_debug(&spd);

arch/powerpc/cpu/mpc83xx/spl_minimal.c

@@ -73,14 +73,14 @@ void cpu_init_f (volatile immap_t * im)
 
 #if defined(CFG_SYS_NAND_BR_PRELIM)  \
 	&& defined(CFG_SYS_NAND_OR_PRELIM) \
-	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
+	&& defined(CFG_SYS_NAND_LBLAWBAR_PRELIM) \
-	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
+	&& defined(CFG_SYS_NAND_LBLAWAR_PRELIM)
 	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
 	set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
-	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
+	im->sysconf.lblaw[0].bar = CFG_SYS_NAND_LBLAWBAR_PRELIM;
-	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
+	im->sysconf.lblaw[0].ar = CFG_SYS_NAND_LBLAWAR_PRELIM;
 #else
-#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
+#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CFG_SYS_NAND_LBLAWBAR_PRELIM & CFG_SYS_NAND_LBLAWAR_PRELIM must be defined
 #endif
 }
 

arch/powerpc/cpu/mpc83xx/start.S

@@ -46,7 +46,7 @@
 
 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
 	!defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_SYS_FLASHBOOT
+#define CFG_SYS_FLASHBOOT
 #endif
 
 /*
@@ -81,8 +81,8 @@
 	.fill	8,1,(((w)>> 8)&0xff);	\
 	.fill	8,1,(((w)    )&0xff)
 
-	_HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
+	_HRCW_TABLE_ENTRY(CFG_SYS_HRCW_LOW)
-	_HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
+	_HRCW_TABLE_ENTRY(CFG_SYS_HRCW_HIGH)
 
 /*
  * Magic number and version string - put it after the HRCW since it
@@ -180,7 +180,7 @@ _start: /* time t 0 */
 
 	bl	init_e300_core
 
-#ifdef CONFIG_SYS_FLASHBOOT
+#ifdef CFG_SYS_FLASHBOOT
 
 	/* Inflate flash location so it appears everywhere, calculate */
 	/* the absolute address in final location of the FLASH, jump  */
@@ -196,7 +196,7 @@ in_flash:
 #if 1 /* Remapping flash with LAW0. */
 	bl remap_flash_by_law0
 #endif
-#endif	/* CONFIG_SYS_FLASHBOOT */
+#endif	/* CFG_SYS_FLASHBOOT */
 
 	/* setup the bats */
 	bl	setup_bats
@@ -525,18 +525,18 @@ init_e300_core: /* time t 10 */
 	/* - force invalidation of data and instruction caches  */
 	/*------------------------------------------------------*/
 
-	lis	r3, CONFIG_SYS_HID0_INIT@h
+	lis	r3, CFG_SYS_HID0_INIT@h
-	ori	r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
+	ori	r3, r3, (CFG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
 	SYNC
 	mtspr	HID0, r3
 
-	lis	r3, CONFIG_SYS_HID0_FINAL@h
+	lis	r3, CFG_SYS_HID0_FINAL@h
-	ori	r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
+	ori	r3, r3, (CFG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
 	SYNC
 	mtspr	HID0, r3
 
-	lis	r3, CONFIG_SYS_HID2@h
+	lis	r3, CFG_SYS_HID2@h
-	ori	r3, r3, CONFIG_SYS_HID2@l
+	ori	r3, r3, CFG_SYS_HID2@l
 	SYNC
 	mtspr	HID2, r3
 
@@ -550,131 +550,131 @@ setup_bats:
 	addis	r0, r0, 0x0000
 
 	/* IBAT 0 */
-	addis	r4, r0, CONFIG_SYS_IBAT0L@h
+	addis	r4, r0, CFG_SYS_IBAT0L@h
-	ori	r4, r4, CONFIG_SYS_IBAT0L@l
+	ori	r4, r4, CFG_SYS_IBAT0L@l
-	addis	r3, r0, CONFIG_SYS_IBAT0U@h
+	addis	r3, r0, CFG_SYS_IBAT0U@h
-	ori	r3, r3, CONFIG_SYS_IBAT0U@l
+	ori	r3, r3, CFG_SYS_IBAT0U@l
 	mtspr	IBAT0L, r4
 	mtspr	IBAT0U, r3
 
 	/* DBAT 0 */
-	addis	r4, r0, CONFIG_SYS_DBAT0L@h
+	addis	r4, r0, CFG_SYS_DBAT0L@h
-	ori	r4, r4, CONFIG_SYS_DBAT0L@l
+	ori	r4, r4, CFG_SYS_DBAT0L@l
-	addis	r3, r0, CONFIG_SYS_DBAT0U@h
+	addis	r3, r0, CFG_SYS_DBAT0U@h
-	ori	r3, r3, CONFIG_SYS_DBAT0U@l
+	ori	r3, r3, CFG_SYS_DBAT0U@l
 	mtspr	DBAT0L, r4
 	mtspr	DBAT0U, r3
 
 	/* IBAT 1 */
-	addis	r4, r0, CONFIG_SYS_IBAT1L@h
+	addis	r4, r0, CFG_SYS_IBAT1L@h
-	ori	r4, r4, CONFIG_SYS_IBAT1L@l
+	ori	r4, r4, CFG_SYS_IBAT1L@l
-	addis	r3, r0, CONFIG_SYS_IBAT1U@h
+	addis	r3, r0, CFG_SYS_IBAT1U@h
-	ori	r3, r3, CONFIG_SYS_IBAT1U@l
+	ori	r3, r3, CFG_SYS_IBAT1U@l
 	mtspr	IBAT1L, r4
 	mtspr	IBAT1U, r3
 
 	/* DBAT 1 */
-	addis	r4, r0, CONFIG_SYS_DBAT1L@h
+	addis	r4, r0, CFG_SYS_DBAT1L@h
-	ori	r4, r4, CONFIG_SYS_DBAT1L@l
+	ori	r4, r4, CFG_SYS_DBAT1L@l
-	addis	r3, r0, CONFIG_SYS_DBAT1U@h
+	addis	r3, r0, CFG_SYS_DBAT1U@h
-	ori	r3, r3, CONFIG_SYS_DBAT1U@l
+	ori	r3, r3, CFG_SYS_DBAT1U@l
 	mtspr	DBAT1L, r4
 	mtspr	DBAT1U, r3
 
 	/* IBAT 2 */
-	addis	r4, r0, CONFIG_SYS_IBAT2L@h
+	addis	r4, r0, CFG_SYS_IBAT2L@h
-	ori	r4, r4, CONFIG_SYS_IBAT2L@l
+	ori	r4, r4, CFG_SYS_IBAT2L@l
-	addis	r3, r0, CONFIG_SYS_IBAT2U@h
+	addis	r3, r0, CFG_SYS_IBAT2U@h
-	ori	r3, r3, CONFIG_SYS_IBAT2U@l
+	ori	r3, r3, CFG_SYS_IBAT2U@l
 	mtspr	IBAT2L, r4
 	mtspr	IBAT2U, r3
 
 	/* DBAT 2 */
-	addis	r4, r0, CONFIG_SYS_DBAT2L@h
+	addis	r4, r0, CFG_SYS_DBAT2L@h
-	ori	r4, r4, CONFIG_SYS_DBAT2L@l
+	ori	r4, r4, CFG_SYS_DBAT2L@l
-	addis	r3, r0, CONFIG_SYS_DBAT2U@h
+	addis	r3, r0, CFG_SYS_DBAT2U@h
-	ori	r3, r3, CONFIG_SYS_DBAT2U@l
+	ori	r3, r3, CFG_SYS_DBAT2U@l
 	mtspr	DBAT2L, r4
 	mtspr	DBAT2U, r3
 
 	/* IBAT 3 */
-	addis	r4, r0, CONFIG_SYS_IBAT3L@h
+	addis	r4, r0, CFG_SYS_IBAT3L@h
-	ori	r4, r4, CONFIG_SYS_IBAT3L@l
+	ori	r4, r4, CFG_SYS_IBAT3L@l
-	addis	r3, r0, CONFIG_SYS_IBAT3U@h
+	addis	r3, r0, CFG_SYS_IBAT3U@h
-	ori	r3, r3, CONFIG_SYS_IBAT3U@l
+	ori	r3, r3, CFG_SYS_IBAT3U@l
 	mtspr	IBAT3L, r4
 	mtspr	IBAT3U, r3
 
 	/* DBAT 3 */
-	addis	r4, r0, CONFIG_SYS_DBAT3L@h
+	addis	r4, r0, CFG_SYS_DBAT3L@h
-	ori	r4, r4, CONFIG_SYS_DBAT3L@l
+	ori	r4, r4, CFG_SYS_DBAT3L@l
-	addis	r3, r0, CONFIG_SYS_DBAT3U@h
+	addis	r3, r0, CFG_SYS_DBAT3U@h
-	ori	r3, r3, CONFIG_SYS_DBAT3U@l
+	ori	r3, r3, CFG_SYS_DBAT3U@l
 	mtspr	DBAT3L, r4
 	mtspr	DBAT3U, r3
 
 #ifdef CONFIG_HIGH_BATS
 	/* IBAT 4 */
-	addis   r4, r0, CONFIG_SYS_IBAT4L@h
+	addis   r4, r0, CFG_SYS_IBAT4L@h
-	ori     r4, r4, CONFIG_SYS_IBAT4L@l
+	ori     r4, r4, CFG_SYS_IBAT4L@l
-	addis   r3, r0, CONFIG_SYS_IBAT4U@h
+	addis   r3, r0, CFG_SYS_IBAT4U@h
-	ori     r3, r3, CONFIG_SYS_IBAT4U@l
+	ori     r3, r3, CFG_SYS_IBAT4U@l
 	mtspr   IBAT4L, r4
 	mtspr   IBAT4U, r3
 
 	/* DBAT 4 */
-	addis   r4, r0, CONFIG_SYS_DBAT4L@h
+	addis   r4, r0, CFG_SYS_DBAT4L@h
-	ori     r4, r4, CONFIG_SYS_DBAT4L@l
+	ori     r4, r4, CFG_SYS_DBAT4L@l
-	addis   r3, r0, CONFIG_SYS_DBAT4U@h
+	addis   r3, r0, CFG_SYS_DBAT4U@h
-	ori     r3, r3, CONFIG_SYS_DBAT4U@l
+	ori     r3, r3, CFG_SYS_DBAT4U@l
 	mtspr   DBAT4L, r4
 	mtspr   DBAT4U, r3
 
 	/* IBAT 5 */
-	addis   r4, r0, CONFIG_SYS_IBAT5L@h
+	addis   r4, r0, CFG_SYS_IBAT5L@h
-	ori     r4, r4, CONFIG_SYS_IBAT5L@l
+	ori     r4, r4, CFG_SYS_IBAT5L@l
-	addis   r3, r0, CONFIG_SYS_IBAT5U@h
+	addis   r3, r0, CFG_SYS_IBAT5U@h
-	ori     r3, r3, CONFIG_SYS_IBAT5U@l
+	ori     r3, r3, CFG_SYS_IBAT5U@l
 	mtspr   IBAT5L, r4
 	mtspr   IBAT5U, r3
 
 	/* DBAT 5 */
-	addis   r4, r0, CONFIG_SYS_DBAT5L@h
+	addis   r4, r0, CFG_SYS_DBAT5L@h
-	ori     r4, r4, CONFIG_SYS_DBAT5L@l
+	ori     r4, r4, CFG_SYS_DBAT5L@l
-	addis   r3, r0, CONFIG_SYS_DBAT5U@h
+	addis   r3, r0, CFG_SYS_DBAT5U@h
-	ori     r3, r3, CONFIG_SYS_DBAT5U@l
+	ori     r3, r3, CFG_SYS_DBAT5U@l
 	mtspr   DBAT5L, r4
 	mtspr   DBAT5U, r3
 
 	/* IBAT 6 */
-	addis   r4, r0, CONFIG_SYS_IBAT6L@h
+	addis   r4, r0, CFG_SYS_IBAT6L@h
-	ori     r4, r4, CONFIG_SYS_IBAT6L@l
+	ori     r4, r4, CFG_SYS_IBAT6L@l
-	addis   r3, r0, CONFIG_SYS_IBAT6U@h
+	addis   r3, r0, CFG_SYS_IBAT6U@h
-	ori     r3, r3, CONFIG_SYS_IBAT6U@l
+	ori     r3, r3, CFG_SYS_IBAT6U@l
 	mtspr   IBAT6L, r4
 	mtspr   IBAT6U, r3
 
 	/* DBAT 6 */
-	addis   r4, r0, CONFIG_SYS_DBAT6L@h
+	addis   r4, r0, CFG_SYS_DBAT6L@h
-	ori     r4, r4, CONFIG_SYS_DBAT6L@l
+	ori     r4, r4, CFG_SYS_DBAT6L@l
-	addis   r3, r0, CONFIG_SYS_DBAT6U@h
+	addis   r3, r0, CFG_SYS_DBAT6U@h
-	ori     r3, r3, CONFIG_SYS_DBAT6U@l
+	ori     r3, r3, CFG_SYS_DBAT6U@l
 	mtspr   DBAT6L, r4
 	mtspr   DBAT6U, r3
 
 	/* IBAT 7 */
-	addis   r4, r0, CONFIG_SYS_IBAT7L@h
+	addis   r4, r0, CFG_SYS_IBAT7L@h
-	ori     r4, r4, CONFIG_SYS_IBAT7L@l
+	ori     r4, r4, CFG_SYS_IBAT7L@l
-	addis   r3, r0, CONFIG_SYS_IBAT7U@h
+	addis   r3, r0, CFG_SYS_IBAT7U@h
-	ori     r3, r3, CONFIG_SYS_IBAT7U@l
+	ori     r3, r3, CFG_SYS_IBAT7U@l
 	mtspr   IBAT7L, r4
 	mtspr   IBAT7U, r3
 
 	/* DBAT 7 */
-	addis   r4, r0, CONFIG_SYS_DBAT7L@h
+	addis   r4, r0, CFG_SYS_DBAT7L@h
-	ori     r4, r4, CONFIG_SYS_DBAT7L@l
+	ori     r4, r4, CFG_SYS_DBAT7L@l
-	addis   r3, r0, CONFIG_SYS_DBAT7U@h
+	addis   r3, r0, CFG_SYS_DBAT7U@h
-	ori     r3, r3, CONFIG_SYS_DBAT7U@l
+	ori     r3, r3, CFG_SYS_DBAT7U@l
 	mtspr   DBAT7L, r4
 	mtspr   DBAT7U, r3
 #endif
@@ -1095,7 +1095,7 @@ unlock_ram_in_cache:
 #endif /* !MINIMAL_SPL */
 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
 
-#ifdef CONFIG_SYS_FLASHBOOT
+#ifdef CFG_SYS_FLASHBOOT
 map_flash_by_law1:
 	/* When booting from ROM (Flash or EPROM), clear the  */
 	/* Address Mask in OR0 so ROM appears everywhere      */
@@ -1182,4 +1182,4 @@ remap_flash_by_law0:
 	twi 0,r4,0
 	isync
 	blr
-#endif /* CONFIG_SYS_FLASHBOOT */
+#endif /* CFG_SYS_FLASHBOOT */

arch/powerpc/cpu/mpc85xx/Kconfig

@@ -313,6 +313,8 @@ config ARCH_B4860
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_SRDS_1
+	select SYS_FSL_SRDS_2
 	select SYS_FSL_SRIO_LIODN
 	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select SYS_FSL_USB1_PHY_ENABLE
@@ -780,6 +782,7 @@ config ARCH_T1024
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SINGLE_SOURCE_CLK
+	select SYS_FSL_SRDS_1
 	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select SYS_FSL_USB_DUAL_PHY_ENABLE
 	select FSL_IFC
@@ -813,6 +816,7 @@ config ARCH_T1040
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SINGLE_SOURCE_CLK
+	select SYS_FSL_SRDS_1
 	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select SYS_FSL_USB_DUAL_PHY_ENABLE
 	select FSL_IFC
@@ -845,6 +849,7 @@ config ARCH_T1042
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SINGLE_SOURCE_CLK
+	select SYS_FSL_SRDS_1
 	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select SYS_FSL_USB_DUAL_PHY_ENABLE
 	select FSL_IFC
@@ -880,6 +885,8 @@ config ARCH_T2080
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_SRDS_1
+	select SYS_FSL_SRDS_2
 	select SYS_FSL_SRIO_LIODN
 	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select SYS_FSL_USB_DUAL_PHY_ENABLE
@@ -921,6 +928,8 @@ config ARCH_T4240
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_SRDS_1
+	select SYS_FSL_SRDS_2
 	select SYS_FSL_SRIO_LIODN
 	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select SYS_FSL_USB_DUAL_PHY_ENABLE
@@ -1198,9 +1207,6 @@ config SYS_FSL_ERRATUM_SRIO_A004034
 config SYS_FSL_ERRATUM_USB14
 	bool
 
-config SYS_HAS_SERDES
-	bool
-
 config SYS_P4080_ERRATUM_CPU22
 	bool
 

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -73,11 +73,11 @@ void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
 	get_sys_info(&sysinfo);
 	if (sysinfo.diff_sysclk == 1) {
 		clrbits_be32(&usb_phy->pllprg[1],
-			     CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+			     CFG_SYS_FSL_USB_PLLPRG2_MFI);
 		setbits_be32(&usb_phy->pllprg[1],
-			     CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+			     CFG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
-			     CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+			     CFG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
-			     CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+			     CFG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
 		}
 }
 #endif
@@ -89,18 +89,18 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
 	u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
 
 	/* Increase Disconnect Threshold by 50mV */
-	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+	xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
 						INC_DCNT_THRESHOLD_50MV;
 	/* Enable programming of USB High speed Disconnect threshold */
-	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+	xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
 	out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
 
 	xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
 	/* Increase Disconnect Threshold by 50mV */
-	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+	xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
 						INC_DCNT_THRESHOLD_50MV;
 	/* Enable programming of USB High speed Disconnect threshold */
-	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+	xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
 	out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
 #else
 
@@ -108,22 +108,22 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
 	u32 status = in_be32(&usb_phy->status1);
 
 	u32 squelch_prog_rd_0_2 =
-		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+		(status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
-			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+			& CFG_SYS_FSL_USB_SQUELCH_PROG_MASK;
 
 	u32 squelch_prog_rd_3_5 =
-		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+		(status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
-			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+			& CFG_SYS_FSL_USB_SQUELCH_PROG_MASK;
 
 	setbits_be32(&usb_phy->config1,
-		     CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+		     CFG_SYS_FSL_USB_HS_DISCNCT_INC);
 	setbits_be32(&usb_phy->config2,
-		     CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+		     CFG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
 
-	temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+	temp = squelch_prog_rd_0_2 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
 	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 
-	temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+	temp = squelch_prog_rd_3_5 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
 	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 #endif
 }
@@ -827,7 +827,7 @@ int cpu_init_r(void)
 			fsl_erratum_a006261_workaround(usb_phy1);
 #endif
 		out_be32(&usb_phy1->usb_enable_override,
-				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+				CFG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
 #endif
 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
@@ -839,7 +839,7 @@ int cpu_init_r(void)
 			fsl_erratum_a006261_workaround(usb_phy2);
 #endif
 		out_be32(&usb_phy2->usb_enable_override,
-				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+				CFG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
 #endif
 
@@ -861,25 +861,25 @@ int cpu_init_r(void)
 		struct ccsr_usb_phy __iomem *usb_phy =
 			(void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
 		setbits_be32(&usb_phy->pllprg[1],
-			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
+			     CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
-			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
+			     CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
-			     CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
+			     CFG_SYS_FSL_USB_PLLPRG2_MFI |
-			     CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+			     CFG_SYS_FSL_USB_PLLPRG2_PLL_EN);
 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 		usb_single_source_clk_configure(usb_phy);
 #endif
 		setbits_be32(&usb_phy->port1.ctrl,
-			     CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+			     CFG_SYS_FSL_USB_CTRL_PHY_EN);
 		setbits_be32(&usb_phy->port1.drvvbuscfg,
-			     CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+			     CFG_SYS_FSL_USB_DRVVBUS_CR_EN);
 		setbits_be32(&usb_phy->port1.pwrfltcfg,
-			     CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+			     CFG_SYS_FSL_USB_PWRFLT_CR_EN);
 		setbits_be32(&usb_phy->port2.ctrl,
-			     CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+			     CFG_SYS_FSL_USB_CTRL_PHY_EN);
 		setbits_be32(&usb_phy->port2.drvvbuscfg,
-			     CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+			     CFG_SYS_FSL_USB_DRVVBUS_CR_EN);
 		setbits_be32(&usb_phy->port2.pwrfltcfg,
-			     CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+			     CFG_SYS_FSL_USB_PWRFLT_CR_EN);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 		if (has_erratum_a006261())

arch/powerpc/cpu/mpc85xx/fdt.c

@@ -92,7 +92,6 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 	}
 
 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
-#define	CONFIG_MEM_HOLE_16M	0x1000000
 	/*
 	 * Extract hwconfig from environment.
 	 * Search for tdm entry in hwconfig.
@@ -103,8 +102,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 
 	/* Reserve the memory hole created by TDM LAW, so OSes dont use it */
 	if (tdm_hwconfig_enabled) {
-		off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+		off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE, SZ_16);
-				      CONFIG_MEM_HOLE_16M);
 		if (off < 0)
 			printf("Failed  to reserve memory for tdm: %s\n",
 			       fdt_strerror(off));
@@ -534,7 +532,7 @@ void fdt_fixup_dma3(void *blob)
 	int nodeoff;
 	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
-#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
+#define CFG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
 #if defined(CONFIG_ARCH_T2080)
 	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 				    FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
@@ -556,7 +554,7 @@ void fdt_fixup_dma3(void *blob)
 	case 16:
 #endif
 		nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
-							CONFIG_SYS_ELO3_DMA3);
+							CFG_SYS_ELO3_DMA3);
 		if (nodeoff > 0)
 			fdt_status_disabled(blob, nodeoff);
 		else
@@ -618,11 +616,11 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 	fdt_add_enet_stashing(blob);
 
-#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
+#ifndef CFG_FSL_TBCLK_EXTRA_DIV
-#define CONFIG_FSL_TBCLK_EXTRA_DIV 1
+#define CFG_FSL_TBCLK_EXTRA_DIV 1
 #endif
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-		"timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
+		"timebase-frequency", get_tbclk() / CFG_FSL_TBCLK_EXTRA_DIV,
 		1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"bus-frequency", bd->bi_busfreq, 1);

arch/powerpc/cpu/mpc85xx/liodn.c

@@ -255,14 +255,14 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
 }
 #endif
 
-#define CONFIG_SYS_MAX_PCI_EPS		8
+#define CFG_SYS_MAX_PCI_EPS		8
 
 static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
 					int ep_liodn_start)
 {
 	int off, pci_idx = 0, pci_cnt = 0, i, rc;
 	const uint32_t *base_liodn;
-	uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 };
+	uint32_t liodn_offs[CFG_SYS_MAX_PCI_EPS + 1] = { 0 };
 
 	/*
 	 * Count the number of pci nodes.
@@ -282,7 +282,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
 			       path, fdt_strerror(rc));
 			continue;
 		}
-		for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
+		for (i = 0; i < CFG_SYS_MAX_PCI_EPS; i++)
 			liodn_offs[i + 1] = ep_liodn_start +
 					i * pci_cnt + pci_idx - *base_liodn;
 		rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",

arch/powerpc/cpu/mpc8xxx/fsl_pamu.c

@@ -240,8 +240,8 @@ int pamu_init(void)
 	spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES;
 
 	/* Allocate space for Primary PAACT Table */
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_PPAACT_ADDR))
+#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_PPAACT_ADDR))
-	ppaact = (void *)CONFIG_SPL_PPAACT_ADDR;
+	ppaact = (void *)CFG_SPL_PPAACT_ADDR;
 #else
 	ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size);
 	if (!ppaact)
@@ -250,8 +250,8 @@ int pamu_init(void)
 	memset(ppaact, 0, ppaact_size);
 
 	/* Allocate space for Secondary PAACT Table */
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPAACT_ADDR))
+#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_SPAACT_ADDR))
-	sec = (void *)CONFIG_SPL_SPAACT_ADDR;
+	sec = (void *)CFG_SPL_SPAACT_ADDR;
 #else
 	sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size);
 	if (!sec)
@@ -266,7 +266,7 @@ int pamu_init(void)
 	spaact_lim = spaact_phys + spaact_size;
 
 	/* Configure all PAMU's */
-	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+	for (i = 0; i < CFG_NUM_PAMU; i++) {
 		regs = (struct ccsr_pamu *)base_addr;
 
 		out_be32(&regs->ppbah, ppaact_phys >> 32);
@@ -293,7 +293,7 @@ void pamu_enable(void)
 {
 	u32 i = 0;
 	u32 base_addr = CFG_SYS_PAMU_ADDR;
-	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+	for (i = 0; i < CFG_NUM_PAMU; i++) {
 		setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
 			     PAMU_PCR_PE);
 		sync();
@@ -307,7 +307,7 @@ void pamu_reset(void)
 	u32 base_addr = CFG_SYS_PAMU_ADDR;
 	struct ccsr_pamu *regs;
 
-	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+	for (i = 0; i < CFG_NUM_PAMU; i++) {
 		regs = (struct ccsr_pamu *)base_addr;
 	/* Clear PPAACT Base register */
 		out_be32(&regs->ppbah, 0);
@@ -331,7 +331,7 @@ void pamu_disable(void)
 	u32 base_addr = CFG_SYS_PAMU_ADDR;
 
 
-	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+	for (i = 0; i < CFG_NUM_PAMU; i++) {
 		clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
 		sync();
 		base_addr += PAMU_OFFSET;

arch/powerpc/include/asm/config_mpc85xx.h

@@ -16,9 +16,6 @@
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
-#elif defined(CONFIG_ARCH_P1010)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
-
 #elif defined(CONFIG_ARCH_P1021)
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
@@ -85,11 +82,6 @@
 #define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
-#elif defined(CONFIG_ARCH_BSC9131)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
-
-#elif defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 
 #elif defined(CONFIG_ARCH_T4240)
 #ifdef CONFIG_ARCH_T4240
@@ -104,13 +96,10 @@
 #define CFG_SYS_NUM_FM2_DTSEC	8
 #define CFG_SYS_NUM_FM2_10GEC	1
 #endif
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
 #define CFG_SYS_FSL_SRDS_3
 #define CFG_SYS_FSL_SRDS_4
 #define CFG_SYS_NUM_FMAN		2
 #define CFG_SYS_PME_CLK		0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM1_CLK		3
 #define CFG_SYS_FM2_CLK		3
 #define CFG_SYS_FM_MURAM_SIZE	0x60000
@@ -119,11 +108,8 @@
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_FM1_CLK		0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CFG_SYS_FM_MURAM_SIZE	0x60000
 
 #ifdef CONFIG_ARCH_B4860
@@ -141,12 +127,10 @@
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
 #define CFG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_SRDS_1
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	5
 #define CFG_PME_PLAT_CLK_DIV		2
 #define CFG_SYS_PME_CLK		CFG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_FM_PLAT_CLK_DIV	1
 #define CFG_SYS_FM1_CLK		CFG_FM_PLAT_CLK_DIV
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
@@ -157,11 +141,9 @@
 
 #elif defined(CONFIG_ARCH_T1024)
 #define CFG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_SRDS_1
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	4
 #define CFG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM1_CLK		0
 #define CFG_QBMAN_CLK_DIV		1
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
@@ -173,11 +155,9 @@
 #elif defined(CONFIG_ARCH_T2080)
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
-#define CONFIG_SYS_FSL_SRDS_1
 #if defined(CONFIG_ARCH_T2080)
 #define CFG_SYS_NUM_FM1_DTSEC	8
 #define CFG_SYS_NUM_FM1_10GEC	4
-#define CONFIG_SYS_FSL_SRDS_2
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -185,13 +165,11 @@
 #define CFG_PME_PLAT_CLK_DIV		1
 #define CFG_SYS_PME_CLK		CFG_PME_PLAT_CLK_DIV
 #define CFG_SYS_FM1_CLK		0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 
 
 #elif defined(CONFIG_ARCH_C29X)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
 #endif

arch/powerpc/include/asm/fsl_pamu.h

@@ -6,7 +6,7 @@
 #ifndef __PAMU_H
 #define __PAMU_H
 
-#define CONFIG_NUM_PAMU		16
+#define CFG_NUM_PAMU		16
 #define NUM_PPAACT_ENTRIES	512
 #define NUM_SPAACT_ENTRIES	256
 

arch/powerpc/include/asm/fsl_secure_boot.h

@@ -41,10 +41,10 @@
  * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
  * due to space crunch on CPC and thus malloc will not work.
  */
-#define CONFIG_SPL_PPAACT_ADDR		0x2e000000
+#define CFG_SPL_PPAACT_ADDR		0x2e000000
-#define CONFIG_SPL_SPAACT_ADDR		0x2f000000
+#define CFG_SPL_SPAACT_ADDR		0x2f000000
-#define CONFIG_SPL_JR0_LIODN_S		454
+#define CFG_SPL_JR0_LIODN_S		454
-#define CONFIG_SPL_JR0_LIODN_NS		458
+#define CFG_SPL_JR0_LIODN_NS		458
 #endif /* ifdef CONFIG_SPL_BUILD */
 
 #ifndef CONFIG_SPL_BUILD

arch/powerpc/include/asm/processor.h

@@ -979,37 +979,6 @@
 #define PVR_5200	0x80822011
 #define PVR_5200B	0x80822014
 
-/*
- * 405EX/EXr CHIP_21 Errata
- */
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX1_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX1_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x0
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX2_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX2_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x1
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR1_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR1_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x2
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR2_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR2_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x3
-#endif
-
 /*
  * System Version Register
  */

arch/powerpc/lib/bootm.c

@@ -41,8 +41,8 @@ static ulong get_sp (void);
 extern void ft_fixup_num_cores(void *blob);
 static void set_clocks_in_mhz (struct bd_info *kbd);
 
-#ifndef CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
+#ifndef CFG_SYS_LINUX_LOWMEM_MAX_SIZE
-#define CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE	(768*1024*1024)
+#define CFG_SYS_LINUX_LOWMEM_MAX_SIZE	(768*1024*1024)
 #endif
 
 static void boot_jump_linux(struct bootm_headers *images)
@@ -133,7 +133,7 @@ void arch_lmb_reserve(struct lmb *lmb)
 #endif
 
 	size = min(bootm_size, get_effective_memsize());
-	size = min(size, (ulong)CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE);
+	size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE);
 
 	if (size < bootm_size) {
 		ulong base = bootmap_base + size;

arch/powerpc/lib/interrupts.c

@@ -17,8 +17,8 @@
 #include <asm/ptrace.h>
 
 #ifndef CONFIG_MPC83XX_TIMER
-#ifndef CONFIG_SYS_WATCHDOG_FREQ
+#ifndef CFG_SYS_WATCHDOG_FREQ
-#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
+#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
 #endif
 
 static unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
@@ -80,7 +80,7 @@ void timer_interrupt(struct pt_regs *regs)
 	timestamp++;
 
 #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
-	if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
+	if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0)
 		schedule();
 #endif    /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
 

arch/riscv/include/asm/encoding.h

@@ -93,7 +93,7 @@
 #define DEFAULT_RSTVEC		0x00001000
 #define DEFAULT_NMIVEC		0x00001004
 #define DEFAULT_MTVEC		0x00001010
-#define CONFIG_STRING_ADDR	0x0000100C
+#define CFG_STRING_ADDR	0x0000100C
 #define EXT_IO_BASE		0x40000000
 #define DRAM_BASE		0x80000000
 

arch/x86/include/asm/acpi/chromeos.asl

@@ -5,7 +5,7 @@
 
 #ifdef CONFIG_CHROMEOS
 
-#define CONFIG_VBOOT_VBNV_OFFSET 0x26
+#define CFG_VBOOT_VBNV_OFFSET 0x26
 
 #include <asm/acpi/vbnv_layout.h>
 
@@ -68,7 +68,7 @@ Device (CRHW)
 		Name(VNBV, Package() {
 			// See src/vendorcode/google/chromeos/Kconfig
 			// for the definition of these:
-			CONFIG_VBOOT_VBNV_OFFSET,
+			CFG_VBOOT_VBNV_OFFSET,
 			VBOOT_VBNV_BLOCK_SIZE
 		})
 		Return(VNBV)

board/alliedtelesis/x530/x530.c

@@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define MVEBU_DEV_BUS_BASE		(MVEBU_REGISTER(0x10400))
 
-#define CONFIG_NVS_LOCATION		0xf4800000
+#define CFG_NVS_LOCATION		0xf4800000
-#define CONFIG_NVS_SIZE			(512 << 10)
+#define CFG_NVS_SIZE			(512 << 10)
 
 static struct serdes_map board_serdes_map[] = {
 	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
@@ -109,7 +109,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	/* window for NVS */
-	mbus_dt_setup_win(CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
+	mbus_dt_setup_win(CFG_NVS_LOCATION, CFG_NVS_SIZE,
 			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
 
 	/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */

board/armltd/vexpress64/vexpress64.c

@@ -220,7 +220,7 @@ int board_eth_init(struct bd_info *bis)
 	int rc = 0;
 #ifndef CONFIG_DM_ETH
 #ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+	rc = smc911x_initialize(0, CFG_SMC911X_BASE);
 #endif
 #endif
 	return rc;

board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c

@@ -12,8 +12,7 @@
 
 #ifdef CONFIG_SPL_BUILD
 
-#define CONFIG_SYS_I2C_EEPROM_ADDR_P1	0x51
+#define CFG_SYS_I2C_EEPROM_ADDR_P1	0x51
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 
 static iomux_v3_cfg_t const eeprom_pads[] = {
 	IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -41,7 +40,7 @@ static int cl_eeprom_read(uint offset, uchar *buf, int len)
 	struct udevice *dev;
 	int ret;
 
-	ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1,
+	ret = i2c_get_chip_for_busnum(1, CFG_SYS_I2C_EEPROM_ADDR_P1,
 				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
 	if (ret) {
 		printf("%s: Cannot find EEPROM: %d\n", __func__, ret);
@@ -58,7 +57,7 @@ static int cl_eeprom_write(uint offset, uchar *buf, int len)
 
 	cl_eeprom_we(1);
 
-	ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1,
+	ret = i2c_get_chip_for_busnum(1, CFG_SYS_I2C_EEPROM_ADDR_P1,
 				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
 	if (ret) {
 		printf("%s: Cannot find EEPROM: %d\n", __func__, ret);

board/davinci/da8xxevm/da850evm.c

@@ -226,8 +226,8 @@ const struct lpsc_resource lpsc[] = {
 
 const int lpsc_size = ARRAY_SIZE(lpsc);
 
-#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
+#ifndef CFG_DA850_EVM_MAX_CPU_CLK
-#define CONFIG_DA850_EVM_MAX_CPU_CLK	300000000
+#define CFG_DA850_EVM_MAX_CPU_CLK	300000000
 #endif
 
 #define REV_AM18X_EVM		0x100
@@ -245,7 +245,7 @@ const int lpsc_size = ARRAY_SIZE(lpsc);
 u32 get_board_rev(void)
 {
 	char *s;
-	u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
+	u32 maxcpuclk = CFG_DA850_EVM_MAX_CPU_CLK;
 	u32 rev = 0;
 
 	s = env_get("maxcpuclk");

board/davinci/da8xxevm/omapl138_lcdk.c

@@ -139,8 +139,8 @@ const struct lpsc_resource lpsc[] = {
 
 const int lpsc_size = ARRAY_SIZE(lpsc);
 
-#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
+#ifndef CFG_DA850_EVM_MAX_CPU_CLK
-#define CONFIG_DA850_EVM_MAX_CPU_CLK	456000000
+#define CFG_DA850_EVM_MAX_CPU_CLK	456000000
 #endif
 
 int board_early_init_f(void)

board/eets/pdu001/board.c

@@ -62,8 +62,8 @@ DECLARE_GLOBAL_DATA_PTR;
  * To get the boot device from 'am33xx_spl_board_init' to
  * 'board_late_init' we therefore use a scratch register from the RTC.
  */
-#define CONFIG_SYS_RTC_SCRATCH0 0x60
+#define CFG_SYS_RTC_SCRATCH0 0x60
-#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
+#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CFG_SYS_RTC_SCRATCH0)
 
 #ifdef CONFIG_SPL_BUILD
 static void save_boot_device(void)

board/freescale/common/cadmus.c

@@ -10,8 +10,8 @@
 /*
  * CADMUS Board System Registers
  */
-#ifndef CONFIG_SYS_CADMUS_BASE_REG
+#ifndef CFG_SYS_CADMUS_BASE_REG
-#define CONFIG_SYS_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
+#define CFG_SYS_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
 #endif
 
 typedef struct cadmus_reg {
@@ -30,7 +30,7 @@ typedef struct cadmus_reg {
 unsigned int
 get_board_version(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
 
 	return cadmus->cm_ver;
 }
@@ -39,7 +39,7 @@ get_board_version(void)
 unsigned long
 get_board_sys_clk(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
 
 	uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
 
@@ -57,7 +57,7 @@ get_board_sys_clk(void)
 unsigned int
 get_pci_slot(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
 
 	/*
 	 * PCI slot in USER bits CSR[6:7] by convention.
@@ -69,7 +69,7 @@ get_pci_slot(void)
 unsigned int
 get_pci_dual(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
 
 	/*
 	 * PCI DUAL in CM_PCI[3]

board/freescale/common/fsl_chain_of_trust.c

@@ -28,9 +28,9 @@
 #endif
 
 #if defined(CONFIG_MPC85xx)
-#define CONFIG_DCFG_ADDR	CFG_SYS_MPC85xx_GUTS_ADDR
+#define CFG_DCFG_ADDR	CFG_SYS_MPC85xx_GUTS_ADDR
 #else
-#define CONFIG_DCFG_ADDR	CFG_SYS_FSL_GUTS_ADDR
+#define CFG_DCFG_ADDR	CFG_SYS_FSL_GUTS_ADDR
 #endif
 
 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
@@ -44,7 +44,7 @@ int fsl_check_boot_mode_secure(void)
 {
 	uint32_t val;
 	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_DCFG_ADDR);
 
 	val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
 	if (val == ITS_MASK)

board/freescale/common/pixis.c

@@ -149,8 +149,8 @@ static int set_px_corepll(unsigned long corepll)
 	return 1;
 }
 
-#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
+#ifndef CFG_SYS_PIXIS_VCFGEN0_ENABLE
-#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE		0x1C
+#define CFG_SYS_PIXIS_VCFGEN0_ENABLE		0x1C
 #endif
 
 /* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
@@ -159,7 +159,7 @@ static int set_px_corepll(unsigned long corepll)
  * or various other PIXIS registers to determine the values for COREPLL,
  * MPXPLL, and SYSCLK.
  *
- * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
+ * CFG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
  * register that tells the pixis to use the various PIXIS register.
  */
 static void read_from_px_regs(int set)
@@ -167,18 +167,18 @@ static void read_from_px_regs(int set)
 	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
 
 	if (set)
-		tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+		tmp = tmp | CFG_SYS_PIXIS_VCFGEN0_ENABLE;
 	else
-		tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+		tmp = tmp & ~CFG_SYS_PIXIS_VCFGEN0_ENABLE;
 
 	out_8(pixis_base + PIXIS_VCFGEN0, tmp);
 }
 
-/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
+/* CFG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
  * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
  */
-#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
+#ifndef CFG_SYS_PIXIS_VBOOT_ENABLE
-#define CONFIG_SYS_PIXIS_VBOOT_ENABLE	0x04
+#define CFG_SYS_PIXIS_VBOOT_ENABLE	0x04
 #endif
 
 /* Configure the source of the boot location
@@ -194,14 +194,14 @@ static void read_from_px_regs_altbank(int set)
 	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
 
 	if (set)
-		tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+		tmp = tmp | CFG_SYS_PIXIS_VBOOT_ENABLE;
 	else
-		tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+		tmp = tmp & ~CFG_SYS_PIXIS_VBOOT_ENABLE;
 
 	out_8(pixis_base + PIXIS_VCFGEN1, tmp);
 }
 
-/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
+/* CFG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
  * tells the PIXIS what the alternate flash bank is.
  *
  * Note that it's not really a mask.  It contains the actual LBMAP bits that
@@ -209,8 +209,8 @@ static void read_from_px_regs_altbank(int set)
  * primary bank has these bits set to 0, and the alternate bank has these
  * bits set to 1.
  */
-#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
+#ifndef CFG_SYS_PIXIS_VBOOT_MASK
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	(0x40)
+#define CFG_SYS_PIXIS_VBOOT_MASK	(0x40)
 #endif
 
 /* Tell the PIXIS to boot from the default flash bank
@@ -220,7 +220,7 @@ static void read_from_px_regs_altbank(int set)
  */
 static void clear_altbank(void)
 {
-	clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+	clrbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK);
 }
 
 /* Tell the PIXIS to boot from the alternate flash bank
@@ -230,7 +230,7 @@ static void clear_altbank(void)
  */
 static void set_altbank(void)
 {
-	setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+	setbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK);
 }
 
 /* Reset the board with watchdog disabled.

board/freescale/ls1043aqds/eth.c

@@ -314,7 +314,7 @@ int board_eth_init(struct bd_info *bis)
 		mdio_mux[i] = EMI_NONE;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -322,7 +322,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */

board/freescale/ls1043ardb/eth.c

@@ -28,7 +28,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -36,7 +36,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */

board/freescale/ls1046afrwy/eth.c

@@ -27,7 +27,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 

board/freescale/ls1046aqds/eth.c

@@ -285,7 +285,7 @@ int board_eth_init(struct bd_info *bis)
 		mdio_mux[i] = EMI_NONE;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 

board/freescale/ls1046ardb/eth.c

@@ -29,7 +29,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -37,7 +37,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */

board/freescale/p2041rdb/eth.c

@@ -139,14 +139,14 @@ int board_eth_init(struct bd_info *bis)
 	initialize_lane_to_slot();
 
 	dtsec_mdio_info.regs =
-		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+		(struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR;
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
 	/* Register the real 1G MDIO bus */
 	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the real 10G MDIO bus */

board/freescale/t102xrdb/eth_t102xrdb.c

@@ -41,7 +41,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -49,7 +49,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */

board/freescale/t104xrdb/eth.c

@@ -26,7 +26,7 @@ int board_eth_init(struct bd_info *bis)
 	printf("Initializing Fman\n");
 
 	memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
 	/* Register the real 1G MDIO bus */

board/freescale/t208xqds/eth_t208xqds.c

@@ -474,7 +474,7 @@ int board_eth_init(struct bd_info *bis)
 		mdio_mux[i] = EMI_NONE;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -482,7 +482,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */

board/freescale/t4rdb/eth.c

@@ -54,7 +54,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -62,7 +62,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */

board/logicpd/omap3som/omap3logic.c

@@ -58,7 +58,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6	0x09030000
 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7	0x00000C50
 
-#define CONFIG_SMC911X_BASE 0x08000000
+#define CFG_SMC911X_BASE 0x08000000
 
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
@@ -226,7 +226,7 @@ int board_late_init(void)
 
 #ifdef CONFIG_SMC911X
 	enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
-			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+			CFG_SMC911X_BASE, GPMC_SIZE_16M);
 #endif
 	return 0;
 }

board/renesas/blanche/blanche.c

@@ -327,7 +327,7 @@ int board_eth_init(struct bd_info *bis)
 	struct eth_device *dev;
 	uchar eth_addr[6];
 
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+	rc = smc911x_initialize(0, CFG_SMC911X_BASE);
 
 	if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
 		dev = eth_get_dev_by_index(0);

board/sysam/amcore/amcore.c

@@ -109,7 +109,7 @@ int dram_init(void)
 }
 
 static struct coldfire_serial_plat mcf5307_serial_plat = {
-	.base = CONFIG_SYS_UART_BASE,
+	.base = CFG_SYS_UART_BASE,
 	.port = 0,
 	.baudrate = CONFIG_BAUDRATE,
 };

board/ti/omap3evm/evm.c

@@ -33,7 +33,7 @@
 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
 
-#define CONFIG_SMC911X_BASE 0x2C000000
+#define CFG_SMC911X_BASE 0x2C000000
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,7 +54,7 @@ static void omap3_evm_get_revision(void)
 	unsigned int smsc_id;
 
 	/* Ethernet PHY ID is stored at ID_REV register */
-	smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
+	smsc_id = readl(CFG_SMC911X_BASE + 0x50) & 0xFFFF0000;
 	printf("Read back SMSC id 0x%x\n", smsc_id);
 
 	switch (smsc_id) {

cmd/ximg.c

@@ -27,9 +27,9 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 
-#ifndef CONFIG_SYS_XIMG_LEN
+#ifndef CFG_SYS_XIMG_LEN
 /* use 8MByte as default max gunzip size */
-#define CONFIG_SYS_XIMG_LEN	0x800000
+#define CFG_SYS_XIMG_LEN	0x800000
 #endif
 
 static int
@@ -52,7 +52,7 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 	size_t		fit_len;
 #endif
 #ifdef CONFIG_GZIP
-	uint		unc_len = CONFIG_SYS_XIMG_LEN;
+	uint		unc_len = CFG_SYS_XIMG_LEN;
 #endif
 	uint8_t		comp;
 

common/Kconfig

@@ -874,7 +874,7 @@ config UPDATE_COMMON
 
 config UPDATE_TFTP
 	bool "Auto-update using fitImage via TFTP"
-	depends on FIT
+	depends on FIT && OF_LIBFDT && !MTD_NOR_FLASH
 	select UPDATE_COMMON
 	help
 	  This option allows performing update of NOR with data in fitImage
@@ -883,16 +883,24 @@ config UPDATE_TFTP
 config UPDATE_TFTP_CNT_MAX
 	int "The number of connection retries during auto-update"
 	default 0
-	depends on UPDATE_TFTP
+	depends on UPDATE_TFTP || DFU_TFTP
 
 config UPDATE_TFTP_MSEC_MAX
 	int "Delay in mSec to wait for the TFTP server during auto-update"
 	default 100
-	depends on UPDATE_TFTP
+	depends on UPDATE_TFTP || DFU_TFTP
+
+config UPDATE_LOAD_ADDR
+	hex "Address in memory to load the update to"
+	depends on UPDATE_TFTP || DFU_TFTP
+	default 0x100000
+	help
+	  This option defines the location in memory to be used to load the
+	  update to, if 'loadaddr' is not set in the environment.
 
 config UPDATE_FIT
 	bool "Firmware update using fitImage"
-	depends on FIT
+	depends on FIT && OF_LIBFDT
 	depends on DFU
 	select UPDATE_COMMON
 	help

common/autoboot.c

@@ -40,11 +40,15 @@ DECLARE_GLOBAL_DATA_PTR;
 static int stored_bootdelay;
 static int menukey;
 
-#if !defined(CONFIG_AUTOBOOT_STOP_STR_CRYPT)
+#if defined(CONFIG_AUTOBOOT_STOP_STR_CRYPT)
-#define CONFIG_AUTOBOOT_STOP_STR_CRYPT ""
+#define AUTOBOOT_STOP_STR_CRYPT	CONFIG_AUTOBOOT_STOP_STR_CRYPT
+#else
+#define AUTOBOOT_STOP_STR_CRYPT	""
 #endif
-#if !defined(CONFIG_AUTOBOOT_STOP_STR_SHA256)
+#if defined(CONFIG_AUTOBOOT_STOP_STR_SHA256)
-#define CONFIG_AUTOBOOT_STOP_STR_SHA256 ""
+#define AUTOBOOT_STOP_STR_SHA256	CONFIG_AUTOBOOT_STOP_STR_SHA256
+#else
+#define AUTOBOOT_STOP_STR_SHA256	""
 #endif
 
 #ifdef CONFIG_AUTOBOOT_USE_MENUKEY
@@ -81,7 +85,7 @@ static int passwd_abort_crypt(uint64_t etime)
 	int err;
 
 	if (IS_ENABLED(CONFIG_AUTOBOOT_STOP_STR_ENABLE) && !crypt_env_str)
-		crypt_env_str = CONFIG_AUTOBOOT_STOP_STR_CRYPT;
+		crypt_env_str = AUTOBOOT_STOP_STR_CRYPT;
 
 	if (!crypt_env_str)
 		return 0;
@@ -160,7 +164,7 @@ static int passwd_abort_sha256(uint64_t etime)
 	int ret;
 
 	if (sha_env_str == NULL)
-		sha_env_str = CONFIG_AUTOBOOT_STOP_STR_SHA256;
+		sha_env_str = AUTOBOOT_STOP_STR_SHA256;
 
 	presskey = malloc_cache_aligned(DELAY_STOP_STR_MAX_LENGTH);
 	c = strstr(sha_env_str, ":");

common/command.c

@@ -68,7 +68,7 @@ int _do_help(struct cmd_tbl *cmd_start, int cmd_items, struct cmd_tbl *cmdtp,
 				return 1;
 			if (usage == NULL)
 				continue;
-			printf("%-*s- %s\n", CONFIG_SYS_HELP_CMD_WIDTH,
+			printf("%-*s- %s\n", CFG_SYS_HELP_CMD_WIDTH,
 			       cmd_array[i]->name, usage);
 		}
 		return 0;

common/spl/spl_fit.c

@@ -20,14 +20,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ
-#define CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ (64 * 1024)
-#endif
-
-#ifndef CONFIG_SYS_BOOTM_LEN
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)
-#endif
-
 struct spl_fit_info {
 	const void *fit;	/* Pointer to a valid FIT blob */
 	size_t ext_data_offset;	/* Offset to FIT external data (end of FIT) */
@@ -408,7 +400,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
 	if (CONFIG_IS_ENABLED(FIT_IMAGE_TINY))
 		return 0;
 
-	if (CONFIG_IS_ENABLED(LOAD_FIT_APPLY_OVERLAY)) {
+#if CONFIG_IS_ENABLED(LOAD_FIT_APPLY_OVERLAY)
 		void *tmpbuffer = NULL;
 
 		for (; ; index++) {
@@ -462,7 +454,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
 		free(tmpbuffer);
 		if (ret)
 			return ret;
-	}
+#endif
 	/* Try to make space, so we can inject details on the loadables */
 	ret = fdt_shrink_to_minimum(spl_image->fdt_addr, 8192);
 	if (ret < 0)

common/spl/spl_sata.c

@@ -17,11 +17,6 @@
 #include <fat.h>
 #include <image.h>
 
-#ifndef CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR
-/* Dummy value to make the compiler happy */
-#define CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR 0x100
-#endif
-
 static int spl_sata_load_image_raw(struct spl_image_info *spl_image,
 		struct spl_boot_device *bootdev,
 		struct blk_desc *stor_dev, unsigned long sector)
@@ -62,7 +57,7 @@ static int spl_sata_load_image_raw(struct spl_image_info *spl_image,
 static int spl_sata_load_image(struct spl_image_info *spl_image,
 			       struct spl_boot_device *bootdev)
 {
-	int err = 0;
+	int err = -ENOSYS;
 	struct blk_desc *stor_dev;
 
 	/* try to recognize storage devices immediately */
@@ -77,16 +72,14 @@ static int spl_sata_load_image(struct spl_image_info *spl_image,
 				  CONFIG_SYS_SATA_FAT_BOOT_PARTITION))
 #endif
 	{
-		err = -ENOSYS;
+#ifdef CONFIG_SPL_FS_FAT
-
+		err = spl_load_image_fat(spl_image, bootdev, stor_dev,
-		if (IS_ENABLED(CONFIG_SPL_FS_FAT)) {
+				CONFIG_SYS_SATA_FAT_BOOT_PARTITION,
-			err = spl_load_image_fat(spl_image, bootdev, stor_dev,
+				CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
-					CONFIG_SYS_SATA_FAT_BOOT_PARTITION,
+#elif defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR)
-					CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+		err = spl_sata_load_image_raw(spl_image, bootdev, stor_dev,
-		} else if (IS_ENABLED(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR)) {
+			CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR);
-			err = spl_sata_load_image_raw(spl_image, bootdev, stor_dev,
+#endif
-				CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR);
-		}
 	}
 	if (err) {
 		puts("Error loading sata device\n");

common/update.c

@@ -10,14 +10,6 @@
 #include <cpu_func.h>
 #include <image.h>
 
-#if !(defined(CONFIG_FIT) && defined(CONFIG_OF_LIBFDT))
-#error "CONFIG_FIT and CONFIG_OF_LIBFDT are required for auto-update feature"
-#endif
-
-#if defined(CONFIG_UPDATE_TFTP) && !defined(CONFIG_MTD_NOR_FLASH)
-#error "CONFIG_UPDATE_TFTP and !CONFIG_MTD_NOR_FLASH needed for legacy behaviour"
-#endif
-
 #include <command.h>
 #include <env.h>
 #include <net.h>
@@ -31,19 +23,6 @@
 /* env variable holding the location of the update file */
 #define UPDATE_FILE_ENV		"updatefile"
 
-/* set configuration defaults if needed */
-#ifndef CONFIG_UPDATE_LOAD_ADDR
-#define CONFIG_UPDATE_LOAD_ADDR	0x100000
-#endif
-
-#ifndef CONFIG_UPDATE_TFTP_MSEC_MAX
-#define CONFIG_UPDATE_TFTP_MSEC_MAX	100
-#endif
-
-#ifndef CONFIG_UPDATE_TFTP_CNT_MAX
-#define CONFIG_UPDATE_TFTP_CNT_MAX	0
-#endif
-
 extern ulong tftp_timeout_ms;
 extern int tftp_timeout_count_max;
 #ifdef CONFIG_MTD_NOR_FLASH

configs/tools-only_defconfig

@@ -30,7 +30,6 @@ CONFIG_DM_RTC=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER=y
-CONFIG_VIDEO=y
 # CONFIG_VIRTIO_MMIO is not set
 # CONFIG_VIRTIO_PCI is not set
 # CONFIG_VIRTIO_SANDBOX is not set

doc/README.davinci

@@ -58,7 +58,7 @@ Please make sure you understand the restrictions placed on this clock in the
 device specific datasheet before setting up this variable. This information is
 passed to the Linux kernel using the ATAG_REVISION atag.
 
-If "maxcpuclk" is not defined, the configuration CONFIG_DA850_EVM_MAX_CPU_CLK
+If "maxcpuclk" is not defined, the configuration CFG_DA850_EVM_MAX_CPU_CLK
 is used to obtain this information.
 
 Links

doc/README.fec_mxc

@@ -7,7 +7,7 @@ CONFIG_FEC_MXC
 CONFIG_MII
 	Must be defined if CONFIG_FEC_MXC is defined.
 
-CONFIG_FEC_MXC_SWAP_PACKET
+CFG_FEC_MXC_SWAP_PACKET
 	Forced on iff MX28.
 	Swaps the bytes order of all words(4 byte units) in the packet.
 	This should not be specified by a board file. It is cpu specific.

doc/README.socfpga

@@ -6,16 +6,6 @@ This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
 based SOCFPGA. To know more about the hardware itself, please refer to
 www.altera.com.
 
-
-socfpga_dw_mmc
---------------
-
-Here are macro and detailed configuration required to enable DesignWare SDMMC
-controller support within SOCFPGA
-
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
--> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
-
 ---------------------------------------------------------------------
 Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL
 ---------------------------------------------------------------------

doc/develop/environment.rst

@@ -18,7 +18,7 @@ The callbacks are named and associated with a function using the
 U_BOOT_ENV_CALLBACK macro in your board or driver code.
 
 These callbacks are associated with variables in one of two ways.  The
-static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
+static list can be added to by defining CFG_ENV_CALLBACK_LIST_STATIC
 in the board configuration to a string that defines a list of
 associations.  The list must be in the following format::
 

doc/usage/netconsole.rst

@@ -9,7 +9,7 @@ set either of these variables to "nc". Input and output can be
 switched independently.
 
 The default buffer size can be overridden by setting
-CONFIG_NETCONSOLE_BUFFER_SIZE.
+CFG_NETCONSOLE_BUFFER_SIZE.
 
 We use an environment variable 'ncip' to set the IP address and the
 port of the destination. The format is <ip_addr>:<port>. If <port> is

drivers/crypto/fsl/jr.c

@@ -328,7 +328,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 	caam = &caam_st;
 #endif
 	unsigned long long timeval = 0;
-	unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
+	unsigned long long timeout = CFG_USEC_DEQ_TIMEOUT;
 	struct result op;
 	int ret = 0;
 
@@ -743,8 +743,8 @@ int sec_init_idx(uint8_t sec_idx)
 	 * creating PAMU entries corresponding to these.
 	 * For normal build, these are set in set_liodns().
 	 */
-	liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
+	liodn_ns = CFG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
-	liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
+	liodn_s = CFG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
 
 	liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
 		 ~(JRNSLIODN_MASK | JRSLIODN_MASK);

drivers/crypto/fsl/jr.h

@@ -15,7 +15,7 @@
 
 #define JR_SIZE 4
 /* Timeout currently defined as 10 sec */
-#define CONFIG_USEC_DEQ_TIMEOUT	10000000U
+#define CFG_USEC_DEQ_TIMEOUT	10000000U
 
 #define DEFAULT_JR_ID		0
 #define DEFAULT_JR_LIODN	0

drivers/ddr/fsl/ctrl_regs.c

@@ -822,7 +822,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 		twot_en = popts->twot_en;
 	}
 
-	sdram_type = CONFIG_FSL_SDRAM_TYPE;
+	sdram_type = CFG_FSL_SDRAM_TYPE;
 
 	dyn_pwr = popts->dynamic_power;
 	dbw = popts->data_bus_width;
@@ -926,7 +926,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 		rcw_en = 1;
 
 	/* DDR4 can have address parity for UDIMM and discrete */
-	if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
+	if ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
 	    (!popts->registered_dimm_en)) {
 		ap_en = 0;
 	} else {
@@ -1188,7 +1188,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
 	 * handled by register chip and RCW settings.
 	 */
 	if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
-	    ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
+	    ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
 	     !popts->registered_dimm_en)) {
 		if (mclk_ps >= 935) {
 			/* for DDR4-1600/1866/2133 */
@@ -1223,7 +1223,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
 			}
 
 			if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
-			    ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
+			    ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
 			     !popts->registered_dimm_en)) {
 				if (mclk_ps >= 935) {
 					/* for DDR4-1600/1866/2133 */
@@ -1983,7 +1983,7 @@ static void set_timing_cfg_7(const unsigned int ctrl_num,
 	tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
 
 	if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
-	    CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
+	    CFG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
 		/* for DDR4 only */
 		par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1;
 		debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);

drivers/ddr/fsl/options.c

@@ -753,7 +753,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
 	defined(CONFIG_SYS_FSL_DDR4)
 	const struct dynamic_odt *pdodt = odt_unknown;
 #endif
-#if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
+#if (CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
 	ulong ddr_freq;
 #endif
 
@@ -1024,7 +1024,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
 	if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
 		if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
 			if (popts->registered_dimm_en ||
-			    (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
+			    (CFG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
 				popts->ap_en = 1;
 		}
 	}
@@ -1302,7 +1302,7 @@ done:
 
 	popts->package_3ds = pdimm->package_3ds;
 
-#if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
+#if (CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
 	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 	if (popts->registered_dimm_en) {
 		popts->rcw_override = 1;

drivers/fpga/Kconfig

@@ -153,4 +153,9 @@ config SANDBOX_FPGA
 	  This is a driver model based FPGA driver for sandbox.
 	  Currently it is a stub only, as there are no usable uclass methods yet.
 
+config MAX_FPGA_DEVICES
+	int "Maximum number of FPGA devices"
+	depends on FPGA
+	default 5
+
 endmenu

drivers/fpga/fpga.c

@@ -13,11 +13,6 @@
 #include <lattice.h>
 #include <dm/device_compat.h>
 
-/* Local definitions */
-#ifndef CONFIG_MAX_FPGA_DEVICES
-#define CONFIG_MAX_FPGA_DEVICES		5
-#endif
-
 /* Local static data */
 static int next_desc = FPGA_INVALID_DEVICE;
 static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];