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clk: exynos: Move pll code into clk-exynos7420

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PLL utilities code is only used by clk-exynos7420 driver at the moment.
Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL
clocks implementation, which is coming in the next patches.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Sam Protsenko 2024-01-10 21:09:02 -06:00 committed by Minkyu Kang
parent 8fd06aeb8a
commit 0caae9fdc2
4 changed files with 24 additions and 47 deletions
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1
drivers/clk/exynos/Makefile
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@ -3,5 +3,4 @@
# Copyright (C) 2016 Samsung Electronics
# Thomas Abraham <thomas.ab@samsung.com>
obj-y += clk-pll.o
obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o

25
drivers/clk/exynos/clk-exynos7420.c
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@ -10,8 +10,15 @@
#include <errno.h>
#include <clk-uclass.h>
#include <asm/io.h>
#include <div64.h>
#include <dt-bindings/clock/exynos7420-clk.h>
#include "clk-pll.h"
#define PLL145X_MDIV_SHIFT 16
#define PLL145X_MDIV_MASK 0x3ff
#define PLL145X_PDIV_SHIFT 8
#define PLL145X_PDIV_MASK 0x3f
#define PLL145X_SDIV_SHIFT 0
#define PLL145X_SDIV_MASK 0x7
#define DIVIDER(reg, shift, mask) \
(((readl(reg) >> shift) & mask) + 1)
@ -64,6 +71,22 @@ struct exynos7420_clk_top0_priv {
unsigned long sclk_uart2;
};
static unsigned long pll145x_get_rate(unsigned int *con1,
unsigned long fin_freq)
{
unsigned long pll_con1 = readl(con1);
unsigned long mdiv, sdiv, pdiv;
u64 fvco = fin_freq;
mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
static ulong exynos7420_topc_get_rate(struct clk *clk)
{
struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);

32
drivers/clk/exynos/clk-pll.c
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@ -1,32 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Exynos PLL helper functions for clock drivers.
* Copyright (C) 2016 Samsung Electronics
* Thomas Abraham <thomas.ab@samsung.com>
*/
#include <common.h>
#include <asm/io.h>
#include <div64.h>
#define PLL145X_MDIV_SHIFT 16
#define PLL145X_MDIV_MASK 0x3ff
#define PLL145X_PDIV_SHIFT 8
#define PLL145X_PDIV_MASK 0x3f
#define PLL145X_SDIV_SHIFT 0
#define PLL145X_SDIV_MASK 0x7
unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
{
unsigned long pll_con1 = readl(con1);
unsigned long mdiv, sdiv, pdiv;
uint64_t fvco = fin_freq;
mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}

13
drivers/clk/exynos/clk-pll.h
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@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Exynos PLL helper functions for clock drivers.
* Copyright (C) 2016 Samsung Electronics
* Thomas Abraham <thomas.ab@samsung.com>
*/
#ifndef __EXYNOS_CLK_PLL_H
#define __EXYNOS_CLK_PLL_H
unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
#endif /* __EXYNOS_CLK_PLL_H */