random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-10-13 20:36:02 +01:00
Code Issues Packages Projects Releases Wiki Activity

Convert CONFIG_SYS_L2_PL310 to Kconfig

Browse Source 
This converts CONFIG_SYS_L2_PL310 to Kconfig.

For omap2 and mvebu the 'select SYS_L2_PL310' locations were
determined using ./tools/moveconfig -i CONFIG_SYS_L2_PL310.

For mx6 I manually chose ARCH_MX6 as 'select' location. The
correctness has been verified using

	$ ./tools/moveconfig.py -f ARCH_MX6 ~SYS_L2_PL310 ~SYS_L2CACHE_OFF
	0 matches

That means whenever an ARCH_MX6 board had SYS_L2_PL310 disabled, this
was correctly reflected in SYS_L2CACHE_OFF. Thus it's safe to insert
the 'select' statement under ARCH_MX6.

Signed-off-by: Philip Oberfichtner <pro@denx.de>
This commit is contained in:
Philip Oberfichtner 2022-08-17 15:07:12 +02:00 committed by Tom Rini
parent 12bbcd6a85
commit 111688839a
38 changed files with 27 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README
View File

@ -415,8 +415,6 @@ The following options need to be configured:
the defaults discussed just above. the defaults discussed just above.
- Cache Configuration for ARM: - Cache Configuration for ARM:
CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
controller
CONFIG_SYS_PL310_BASE - Physical base address of PL310 CONFIG_SYS_PL310_BASE - Physical base address of PL310
controller register space controller register space

5
arch/arm/Kconfig
View File

@ -488,6 +488,10 @@ config TPL_SYS_THUMB_BUILD
density. For ARM architectures that support Thumb2 this flag will density. For ARM architectures that support Thumb2 this flag will
result in Thumb2 code generated by GCC. result in Thumb2 code generated by GCC.
config SYS_L2_PL310
bool "ARM PL310 L2 cache controller"
help
Enable support for ARM PL310 L2 cache controller in U-Boot
config SYS_L2CACHE_OFF config SYS_L2CACHE_OFF
bool "L2cache off" bool "L2cache off"
@ -989,6 +993,7 @@ config ARCH_MX6
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE select SYS_FSL_SEC_LE
select SYS_L2_PL310 if !SYS_L2CACHE_OFF
imply MXC_GPIO imply MXC_GPIO
imply SYS_THUMB_BUILD imply SYS_THUMB_BUILD
imply SPL_SEPARATE_BSS imply SPL_SEPARATE_BSS

1
arch/arm/mach-mvebu/Kconfig
View File

@ -14,6 +14,7 @@ config ARMADA_32BIT
select SPL_SKIP_LOWLEVEL_INIT if SPL select SPL_SKIP_LOWLEVEL_INIT if SPL
select SPL_SIMPLE_BUS if SPL select SPL_SIMPLE_BUS if SPL
select SUPPORT_SPL select SUPPORT_SPL
select SYS_L2_PL310 if !SYS_L2CACHE_OFF
select TRANSLATION_OFFSET select TRANSLATION_OFFSET
select SPL_SYS_NO_VECTOR_TABLE if SPL select SPL_SYS_NO_VECTOR_TABLE if SPL
select ARCH_VERY_EARLY_INIT select ARCH_VERY_EARLY_INIT

2
arch/arm/mach-mvebu/include/mach/config.h
View File

@ -25,8 +25,6 @@
#define MV88F78X60 /* for the DDR training bin_hdr code */ #define MV88F78X60 /* for the DDR training bin_hdr code */
#endif #endif
#define CONFIG_SYS_L2_PL310
#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
/* Needed for SPI NOR booting in SPL */ /* Needed for SPI NOR booting in SPL */

1
arch/arm/mach-omap2/Kconfig
View File

@ -96,6 +96,7 @@ config TI816X
config AM43XX config AM43XX
bool "AM43XX SoC" bool "AM43XX SoC"
select SPECIFY_CONSOLE_INDEX select SPECIFY_CONSOLE_INDEX
select SYS_L2_PL310 if !SYS_L2CACHE_OFF
imply NAND_OMAP_ELM imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC imply NAND_OMAP_GPMC
imply SPL_DM imply SPL_DM

1
configs/omap4_panda_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_OMAP2PLUS=y CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEFAULT_DEVICE_TREE="omap4-panda" CONFIG_DEFAULT_DEVICE_TREE="omap4-panda"

1
configs/omap4_sdp4430_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y CONFIG_ARCH_OMAP2PLUS=y

1
configs/poleg_evb_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_NPCM=y CONFIG_ARCH_NPCM=y
CONFIG_SYS_TEXT_BASE=0x8200 CONFIG_SYS_TEXT_BASE=0x8200
CONFIG_SYS_MALLOC_LEN=0x240000 CONFIG_SYS_MALLOC_LEN=0x240000

1
configs/socfpga_arria10_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_arria5_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_chameleonv3_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x4400 CONFIG_ENV_OFFSET=0x4400

1
configs/socfpga_cyclone5_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_dbm_soc1_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_de0_nano_soc_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_de10_nano_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_de10_standard_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_de1_soc_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_is1_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_mcvevk_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_secu1_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_SYS_MALLOC_F_LEN=0x800

1
configs/socfpga_sockit_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_socrates_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_sr1500_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/socfpga_vining_fpga_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/stemmy_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_U8500=y CONFIG_ARCH_U8500=y
CONFIG_SUPPORT_PASSING_ATAGS=y CONFIG_SUPPORT_PASSING_ATAGS=y
# CONFIG_SETUP_MEMORY_TAGS is not set # CONFIG_SETUP_MEMORY_TAGS is not set

1
include/configs/am43xx_evm.h
View File

@ -29,7 +29,6 @@
/* SPL defines. */ /* SPL defines. */
/* Enabling L2 Cache */ /* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000 #define CONFIG_SYS_PL310_BASE 0x48242000
/* /*

1
include/configs/brppt2.h
View File

@ -13,7 +13,6 @@
/* -- i.mx6 specifica -- */ /* -- i.mx6 specifica -- */
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE #define CONFIG_SYS_PL310_BASE L2_PL310_BASE
#endif /* !CONFIG_SYS_L2CACHE_OFF */ #endif /* !CONFIG_SYS_L2CACHE_OFF */

1
include/configs/cm_t43.h
View File

@ -36,7 +36,6 @@
#define CONFIG_POWER_TPS65218 #define CONFIG_POWER_TPS65218
/* Enabling L2 Cache */ /* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000 #define CONFIG_SYS_PL310_BASE 0x48242000
/* /*

1
include/configs/mx6_common.h
View File

@ -12,7 +12,6 @@
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#else #else
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE #define CONFIG_SYS_PL310_BASE L2_PL310_BASE
#endif #endif

1
include/configs/odroid.h
View File

@ -14,7 +14,6 @@
#include <configs/exynos4-common.h> #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000 #define CONFIG_SYS_PL310_BASE 0x10502000
#endif #endif

1
include/configs/poleg.h
View File

@ -7,7 +7,6 @@
#define __CONFIG_POLEG_H #define __CONFIG_POLEG_H
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/
#endif #endif

1
include/configs/socfpga_common.h
View File

@ -48,7 +48,6 @@
/* /*
* Cache * Cache
*/ */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/* /*

1
include/configs/stemmy.h
View File

@ -15,7 +15,6 @@
*/ */
/* FIXME: This should be loaded from device tree... */ /* FIXME: This should be loaded from device tree... */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0xa0412000 #define CONFIG_SYS_PL310_BASE 0xa0412000
/* Linux does not boot if FDT / initrd is loaded to end of RAM */ /* Linux does not boot if FDT / initrd is loaded to end of RAM */

1
include/configs/ti_omap4_common.h
View File

@ -12,7 +12,6 @@
#define __CONFIG_TI_OMAP4_COMMON_H #define __CONFIG_TI_OMAP4_COMMON_H
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000 #define CONFIG_SYS_PL310_BASE 0x48242000
#endif #endif

1
include/configs/trats.h
View File

@ -12,7 +12,6 @@
#include <configs/exynos4-common.h> #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000 #define CONFIG_SYS_PL310_BASE 0x10502000
#endif #endif

1
include/configs/trats2.h
View File

@ -13,7 +13,6 @@
#include <configs/exynos4-common.h> #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000 #define CONFIG_SYS_PL310_BASE 0x10502000
#endif #endif

1
include/configs/zynq-common.h
View File

@ -11,7 +11,6 @@
/* Cache options */ /* Cache options */
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
# define CONFIG_SYS_L2_PL310
# define CONFIG_SYS_PL310_BASE 0xf8f02000 # define CONFIG_SYS_PL310_BASE 0xf8f02000
#endif #endif

1
scripts/config_whitelist.txt
View File

@ -845,7 +845,6 @@ CONFIG_SYS_JFFS2_FIRST_SECTOR
CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_JFFS2_NUM_BANKS
CONFIG_SYS_KMBEC_FPGA_BASE CONFIG_SYS_KMBEC_FPGA_BASE
CONFIG_SYS_KMBEC_FPGA_SIZE CONFIG_SYS_KMBEC_FPGA_SIZE
CONFIG_SYS_L2_PL310
CONFIG_SYS_L2_SIZE CONFIG_SYS_L2_SIZE
CONFIG_SYS_L3_SIZE CONFIG_SYS_L3_SIZE
CONFIG_SYS_LATCH_ADDR CONFIG_SYS_LATCH_ADDR