ppc/p4080: Added p4080 SERDES registers & USB offset

Added immap definition for SERDES registers on p4080, the USB offset
(since it was missing) and a GPL header.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

include/asm-ppc/immap_85xx.h

@@ -6,6 +6,23 @@
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
  *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
  */
 
 #ifndef __IMMAP_85xx__
@@ -1847,17 +1864,85 @@ typedef struct ccsr_gur {
 } ccsr_gur_t;
 #endif
 
+typedef struct serdes_corenet {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+#define SRDS_RSTCTL_RST		0x80000000
+#define SRDS_RSTCTL_RSTDONE	0x40000000
+#define SRDS_RSTCTL_RSTERR	0x20000000
+		u32	pllcr0; /* PLL Control Register 0 */
+		u32	pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
+		u32	res[5];
+	} bank[3];
+	u32	res1[12];
+	u32	srdstcalcr;	/* TX Calibration Control */
+	u32	res2[3];
+	u32	srdsrcalcr;	/* RX Calibration Control */
+	u32	res3[3];
+	u32	srdsgr0;	/* General Register 0 */
+	u32	res4[11];
+	u32	srdspccr0;	/* Protocol Converter Config 0 */
+	u32	srdspccr1;	/* Protocol Converter Config 1 */
+	u32	srdspccr2;	/* Protocol Converter Config 2 */
+#define SRDS_PCCR2_RST_XGMII1		0x00800000
+#define SRDS_PCCR2_RST_XGMII2		0x00400000
+	u32	res5[197];
+	struct {
+		u32	gcr0;	/* General Control Register 0 */
+#define SRDS_GCR0_RRST			0x00400000
+#define SRDS_GCR0_1STLANE		0x00010000
+		u32	gcr1;	/* General Control Register 1 */
+#define SRDS_GCR1_REIDL_CTL_MASK	0x001f0000
+#define SRDS_GCR1_REIDL_CTL_PCIE	0x00100000
+#define SRDS_GCR1_REIDL_CTL_SRIO	0x00000000
+#define SRDS_GCR1_REIDL_CTL_SGMII	0x00040000
+#define SRDS_GCR1_OPAD_CTL		0x04000000
+		u32	res1[4];
+		u32	tecr0;	/* TX Equalization Control Reg 0 */
+#define SRDS_TECR0_TEQ_TYPE_MASK	0x30000000
+#define SRDS_TECR0_TEQ_TYPE_2LVL	0x10000000
+		u32	res3;
+		u32	ttlcr0;	/* Transition Tracking Loop Ctrl 0 */
+		u32	res4[7];
+	} lane[24];
+	u32 res6[384];
+} serdes_corenet_t;
+
+enum {
+	FSL_SRDS_B1_LANE_A = 0,
+	FSL_SRDS_B1_LANE_B = 1,
+	FSL_SRDS_B1_LANE_C = 2,
+	FSL_SRDS_B1_LANE_D = 3,
+	FSL_SRDS_B1_LANE_E = 4,
+	FSL_SRDS_B1_LANE_F = 5,
+	FSL_SRDS_B1_LANE_G = 6,
+	FSL_SRDS_B1_LANE_H = 7,
+	FSL_SRDS_B1_LANE_I = 8,
+	FSL_SRDS_B1_LANE_J = 9,
+	FSL_SRDS_B2_LANE_A = 16,
+	FSL_SRDS_B2_LANE_B = 17,
+	FSL_SRDS_B2_LANE_C = 18,
+	FSL_SRDS_B2_LANE_D = 19,
+	FSL_SRDS_B3_LANE_A = 20,
+	FSL_SRDS_B3_LANE_B = 21,
+	FSL_SRDS_B3_LANE_C = 22,
+	FSL_SRDS_B3_LANE_D = 23,
+};
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x8000
 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET		0x9000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
+#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
+#define CONFIG_SYS_MPC85xx_USB_OFFSET		0x210000
 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET	0x318000
 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET	0x31a000
 #else
@@ -1929,6 +2014,8 @@ typedef struct ccsr_gur {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)