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doc: fix board/openpiton/riscv64.rst

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* remove duplicate heading to avoid build error with 'make htmldocs'
* length of underlines must match header
* use appropriate header levels
* fix type %s/linux/Linux/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This commit is contained in:
Heinrich Schuchardt 2021-07-24 10:43:35 +02:00
parent 30c5cbf31b
commit 1364029263
1 changed files with 9 additions and 10 deletions
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19
doc/board/openpiton/riscv64.rst
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@ -3,8 +3,6 @@
Openpiton RISC-V SoC Openpiton RISC-V SoC
==================== ====================
OpenPiton RISC-V SoC
--------------------
OpenPiton is an open source, manycore processor and research platform. It is a OpenPiton is an open source, manycore processor and research platform. It is a
tiled manycore framework scalable from one to 1/2 billion cores. It supports a tiled manycore framework scalable from one to 1/2 billion cores. It supports a
number of ISAs including RISC-V with its P-Mesh cache coherence protocol and number of ISAs including RISC-V with its P-Mesh cache coherence protocol and
@ -14,21 +12,23 @@ running full-stack Debian linux.
RISC-V Standard Bootflow RISC-V Standard Bootflow
------------------------- -------------------------
Currently, OpenPiton implements RISC-V standard bootflow in the following steps Currently, OpenPiton implements RISC-V standard bootflow in the following steps
mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux
This board supports S-mode u-boot as well as M-mode SPL This board supports S-mode u-boot as well as M-mode SPL
Building OpenPition Building OpenPition
--------------------- ---------------------
If you'd like to build OpenPiton, please go to OpenPiton github repo If you'd like to build OpenPiton, please go to OpenPiton github repo
(at https://github.com/PrincetonUniversity/openpiton) to build from the latest (at https://github.com/PrincetonUniversity/openpiton) to build from the latest
changes changes
Building Images Building Images
--------------------------- ---------------
SPL SPL
--- ~~~
1. Add the RISC-V toolchain to your PATH. 1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable: 2. Setup ARCH & cross compilation environment variable:
@ -42,7 +42,7 @@ SPL
4. make 4. make
U-Boot U-Boot
------ ~~~~~~
1. Add the RISC-V toolchain to your PATH. 1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable: 2. Setup ARCH & cross compilation environment variable:
@ -55,9 +55,8 @@ U-Boot
3. make openpiton_riscv64_defconfig 3. make openpiton_riscv64_defconfig
4. make 4. make
opensbi opensbi
------- ~~~~~~~
1. Add the RISC-V toolchain to your PATH. 1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable: 2. Setup ARCH & cross compilation environment variable:
@ -70,9 +69,9 @@ opensbi
3. Go to OpenSBI directory 3. Go to OpenSBI directory
4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin> 4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin>
Using fw_payload.bin with Linux
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Using fw_payload.bin with linux
-------------------------------
Put the generated fw_payload.bin into the /boot directory on the root filesystem, Put the generated fw_payload.bin into the /boot directory on the root filesystem,
plug in the SD card, then flash the bitstream. Linux will boot automatically. plug in the SD card, then flash the bitstream. Linux will boot automatically.
@ -81,7 +80,7 @@ Booting
Once you plugin the sdcard and power up, you should see the U-Boot prompt. Once you plugin the sdcard and power up, you should see the U-Boot prompt.
Sample Dual-core Debian boot log from OpenPiton Sample Dual-core Debian boot log from OpenPiton
----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. code-block:: none .. code-block:: none