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sunxi: psci: Avoid hanging when CPU 0 is hot-unplugged

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Do not try to send an SGI from CPU 0 to itself. Since FIQs are masked
when entering monitor mode, this will hang. Plus, CPU 0 cannot fully
power itself off anyway. Instead, have it turn FIQs back on and continue
servicing SGIs from other cores.

Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland 2021-10-09 22:00:22 -05:00
parent 883e3ec5d6
commit 14de263f01
1 changed files with 17 additions and 3 deletions
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20
arch/arm/cpu/armv7/sunxi/psci.c
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@ -38,6 +38,15 @@
#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4) #define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc) #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
static inline u32 __secure cp15_read_mpidr(void)
{
u32 val;
asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
return val;
}
static void __secure cp15_write_cntp_tval(u32 tval) static void __secure cp15_write_cntp_tval(u32 tval)
{ {
asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval)); asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@ -281,9 +290,14 @@ s32 __secure psci_cpu_off(void)
{ {
psci_cpu_off_common(); psci_cpu_off_common();
/* Ask CPU0 via SGI15 to pull the rug... */ if (cp15_read_mpidr() & 3) {
writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); /* Ask CPU0 via SGI15 to pull the rug... */
dsb(); writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
dsb();
} else {
/* Unmask FIQs to service SGI15. */
asm volatile ("cpsie f");
}
/* Wait to be turned off */ /* Wait to be turned off */
while (1) while (1)