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phy: cadence: Sierra: Prepare driver to add support for multilink configurations

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Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
This commit is contained in:
Swapnil Jakhade 2022-01-28 13:41:40 +05:30 committed by Tom Rini
parent 3c1d89ff76
commit 14ed6703be
1 changed files with 135 additions and 53 deletions
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188
drivers/phy/cadence/phy-cadence-sierra.c
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@ -28,6 +28,9 @@
#include <dt-bindings/phy/phy-cadence.h> #include <dt-bindings/phy/phy-cadence.h>
#include <regmap.h> #include <regmap.h>
#define NUM_SSC_MODE 3
#define NUM_PHY_TYPE 3
/* PHY register offsets */ /* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0 #define SIERRA_COMMON_CDB_OFFSET 0x0
#define SIERRA_MACRO_ID_REG 0x0 #define SIERRA_MACRO_ID_REG 0x0
@ -214,8 +217,20 @@ struct cdns_sierra_pll_mux {
#define reset_control_deassert(rst) cdns_reset_deassert(rst) #define reset_control_deassert(rst) cdns_reset_deassert(rst)
#define reset_control reset_ctl #define reset_control reset_ctl
enum cdns_sierra_phy_type {
TYPE_NONE,
TYPE_PCIE,
TYPE_USB
};
enum cdns_sierra_ssc_mode {
NO_SSC,
EXTERNAL_SSC,
INTERNAL_SSC
};
struct cdns_sierra_inst { struct cdns_sierra_inst {
u32 phy_type; enum cdns_sierra_phy_type phy_type;
u32 num_lanes; u32 num_lanes;
u32 mlane; u32 mlane;
struct reset_ctl_bulk *lnk_rst; struct reset_ctl_bulk *lnk_rst;
@ -226,18 +241,19 @@ struct cdns_reg_pairs {
u32 off; u32 off;
}; };
struct cdns_sierra_vals {
const struct cdns_reg_pairs *reg_pairs;
u32 num_regs;
};
struct cdns_sierra_data { struct cdns_sierra_data {
u32 id_value; u32 id_value;
u8 block_offset_shift; u8 block_offset_shift;
u8 reg_offset_shift; u8 reg_offset_shift;
u32 pcie_cmn_regs; struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
u32 pcie_ln_regs; [NUM_SSC_MODE];
u32 usb_cmn_regs; struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
u32 usb_ln_regs; [NUM_SSC_MODE];
struct cdns_reg_pairs *pcie_cmn_vals;
struct cdns_reg_pairs *pcie_ln_vals;
struct cdns_reg_pairs *usb_cmn_vals;
struct cdns_reg_pairs *usb_ln_vals;
}; };
struct cdns_sierra_phy { struct cdns_sierra_phy {
@ -299,10 +315,14 @@ static int cdns_sierra_phy_init(struct phy *gphy)
{ {
struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev); struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
struct cdns_sierra_data *init_data = phy->init_data;
struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
enum cdns_sierra_phy_type phy_type = ins->phy_type;
enum cdns_sierra_ssc_mode ssc = EXTERNAL_SSC;
const struct cdns_reg_pairs *reg_pairs;
struct regmap *regmap = phy->regmap; struct regmap *regmap = phy->regmap;
u32 num_regs;
int i, j; int i, j;
struct cdns_reg_pairs *cmn_vals, *ln_vals;
u32 num_cmn_regs, num_ln_regs;
/* Initialise the PHY registers, unless auto configured */ /* Initialise the PHY registers, unless auto configured */
if (phy->autoconf) if (phy->autoconf)
@ -311,28 +331,25 @@ static int cdns_sierra_phy_init(struct phy *gphy)
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
if (ins->phy_type == PHY_TYPE_PCIE) { /* PMA common registers configurations */
num_cmn_regs = phy->init_data->pcie_cmn_regs; pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
num_ln_regs = phy->init_data->pcie_ln_regs; if (pma_cmn_vals) {
cmn_vals = phy->init_data->pcie_cmn_vals; reg_pairs = pma_cmn_vals->reg_pairs;
ln_vals = phy->init_data->pcie_ln_vals; num_regs = pma_cmn_vals->num_regs;
} else if (ins->phy_type == PHY_TYPE_USB3) { regmap = phy->regmap_common_cdb;
num_cmn_regs = phy->init_data->usb_cmn_regs; for (i = 0; i < num_regs; i++)
num_ln_regs = phy->init_data->usb_ln_regs; regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
cmn_vals = phy->init_data->usb_cmn_vals;
ln_vals = phy->init_data->usb_ln_vals;
} else {
return -EINVAL;
} }
regmap = phy->regmap_common_cdb; /* PMA TX lane registers configurations */
for (j = 0; j < num_cmn_regs ; j++) pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val); if (pma_ln_vals) {
reg_pairs = pma_ln_vals->reg_pairs;
for (i = 0; i < ins->num_lanes; i++) { num_regs = pma_ln_vals->num_regs;
for (j = 0; j < num_ln_regs ; j++) { for (i = 0; i < ins->num_lanes; i++) {
regmap = phy->regmap_lane_cdb[i + ins->mlane]; regmap = phy->regmap_lane_cdb[i + ins->mlane];
regmap_write(regmap, ln_vals[j].off, ln_vals[j].val); for (j = 0; j < num_regs; j++)
regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
} }
} }
@ -507,15 +524,28 @@ static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp)
static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
ofnode child) ofnode child)
{ {
u32 phy_type;
if (ofnode_read_u32(child, "reg", &inst->mlane)) if (ofnode_read_u32(child, "reg", &inst->mlane))
return -EINVAL; return -EINVAL;
if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
return -EINVAL; return -EINVAL;
if (ofnode_read_u32(child, "cdns,phy-type", &inst->phy_type)) if (ofnode_read_u32(child, "cdns,phy-type", &phy_type))
return -EINVAL; return -EINVAL;
switch (phy_type) {
case PHY_TYPE_PCIE:
inst->phy_type = TYPE_PCIE;
break;
case PHY_TYPE_USB3:
inst->phy_type = TYPE_USB;
break;
default:
return -EINVAL;
}
return 0; return 0;
} }
@ -873,6 +903,16 @@ static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG} {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
}; };
static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
.reg_pairs = cdns_pcie_cmn_regs_ext_ssc,
.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
};
static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = {
.reg_pairs = cdns_pcie_ln_regs_ext_ssc,
.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
};
/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
@ -980,32 +1020,74 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
}; };
static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = {
.reg_pairs = cdns_usb_cmn_regs_ext_ssc,
.num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
};
static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = {
.reg_pairs = cdns_usb_ln_regs_ext_ssc,
.num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
};
static const struct cdns_sierra_data cdns_map_sierra = { static const struct cdns_sierra_data cdns_map_sierra = {
SIERRA_MACRO_ID, .id_value = SIERRA_MACRO_ID,
0x2, .block_offset_shift = 0x2,
0x2, .reg_offset_shift = 0x2,
ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), .pma_cmn_vals = {
ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), [TYPE_PCIE] = {
ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), [TYPE_NONE] = {
ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
cdns_pcie_cmn_regs_ext_ssc, },
cdns_pcie_ln_regs_ext_ssc, },
cdns_usb_cmn_regs_ext_ssc, [TYPE_USB] = {
cdns_usb_ln_regs_ext_ssc, [TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
},
},
},
.pma_ln_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
},
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
},
},
},
}; };
static const struct cdns_sierra_data cdns_ti_map_sierra = { static const struct cdns_sierra_data cdns_ti_map_sierra = {
SIERRA_MACRO_ID, .id_value = SIERRA_MACRO_ID,
0x0, .block_offset_shift = 0x0,
0x1, .reg_offset_shift = 0x1,
ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), .pma_cmn_vals = {
ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), [TYPE_PCIE] = {
ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), [TYPE_NONE] = {
ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
cdns_pcie_cmn_regs_ext_ssc, },
cdns_pcie_ln_regs_ext_ssc, },
cdns_usb_cmn_regs_ext_ssc, [TYPE_USB] = {
cdns_usb_ln_regs_ext_ssc, [TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
},
},
},
.pma_ln_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
},
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
},
},
},
}; };
static const struct udevice_id cdns_sierra_id_table[] = { static const struct udevice_id cdns_sierra_id_table[] = {